sti_hdmi.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) STMicroelectronics SA 2014
  4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
  5 */
  6
  7#ifndef _STI_HDMI_H_
  8#define _STI_HDMI_H_
  9
 10#include <linux/hdmi.h>
 11#include <linux/platform_device.h>
 12
 13#include <media/cec-notifier.h>
 14
 15#include <drm/drm_bridge.h>
 16#include <drm/drm_modes.h>
 17#include <drm/drm_property.h>
 18
 19#define HDMI_STA           0x0010
 20#define HDMI_STA_DLL_LCK   BIT(5)
 21#define HDMI_STA_HOT_PLUG  BIT(4)
 22
 23struct sti_hdmi;
 24
 25struct hdmi_phy_ops {
 26	bool (*start)(struct sti_hdmi *hdmi);
 27	void (*stop)(struct sti_hdmi *hdmi);
 28};
 29
 30struct hdmi_audio_params {
 31	bool enabled;
 32	unsigned int sample_width;
 33	unsigned int sample_rate;
 34	struct hdmi_audio_infoframe cea;
 35};
 36
 37#define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB
 38
 39/**
 40 * STI hdmi structure
 41 *
 42 * @dev: driver device
 43 * @drm_dev: pointer to drm device
 44 * @mode: current display mode selected
 45 * @regs: hdmi register
 46 * @syscfg: syscfg register for pll rejection configuration
 47 * @clk_pix: hdmi pixel clock
 48 * @clk_tmds: hdmi tmds clock
 49 * @clk_phy: hdmi phy clock
 50 * @clk_audio: hdmi audio clock
 51 * @irq: hdmi interrupt number
 52 * @irq_status: interrupt status register
 53 * @phy_ops: phy start/stop operations
 54 * @enabled: true if hdmi is enabled else false
 55 * @hpd: hot plug detect status
 56 * @wait_event: wait event
 57 * @event_received: wait event status
 58 * @reset: reset control of the hdmi phy
 59 * @ddc_adapt: i2c ddc adapter
 60 * @colorspace: current colorspace selected
 61 * @audio_pdev: ASoC hdmi-codec platform device
 62 * @audio: hdmi audio parameters.
 63 * @drm_connector: hdmi connector
 64 * @notifier: hotplug detect notifier
 65 */
 66struct sti_hdmi {
 67	struct device dev;
 68	struct drm_device *drm_dev;
 69	struct drm_display_mode mode;
 70	void __iomem *regs;
 71	void __iomem *syscfg;
 72	struct clk *clk_pix;
 73	struct clk *clk_tmds;
 74	struct clk *clk_phy;
 75	struct clk *clk_audio;
 76	int irq;
 77	u32 irq_status;
 78	struct hdmi_phy_ops *phy_ops;
 79	bool enabled;
 80	bool hpd;
 81	wait_queue_head_t wait_event;
 82	bool event_received;
 83	struct reset_control *reset;
 84	struct i2c_adapter *ddc_adapt;
 85	enum hdmi_colorspace colorspace;
 86	struct platform_device *audio_pdev;
 87	struct hdmi_audio_params audio;
 88	struct drm_connector *drm_connector;
 89	struct cec_notifier *notifier;
 90	struct drm_bridge bridge;
 91};
 92
 93u32 hdmi_read(struct sti_hdmi *hdmi, int offset);
 94void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset);
 95
 96/**
 97 * hdmi phy config structure
 98 *
 99 * A pointer to an array of these structures is passed to a TMDS (HDMI) output
100 * via the control interface to provide board and SoC specific
101 * configurations of the HDMI PHY. Each entry in the array specifies a hardware
102 * specific configuration for a given TMDS clock frequency range.
103 *
104 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to
105 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to
106 * @config: SoC specific register configuration
107 */
108struct hdmi_phy_config {
109	u32 min_tmds_freq;
110	u32 max_tmds_freq;
111	u32 config[4];
112};
113
114#endif