FILE
sti_hdmi.c
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linux-6.19.14/drivers/gpu/drm/sti/sti_hdmi.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. 5 */ 6 7#include <linux/clk.h> 8#include <linux/component.h> 9#include <linux/debugfs.h> 10#include <linux/hdmi.h> 11#include <linux/i2c.h> 12#include <linux/module.h> 13#include <linux/io.h> 14#include <linux/platform_device.h> 15#include <linux/reset.h> 16 17#include <drm/drm_atomic_helper.h> 18#include <drm/drm_bridge.h> 19#include <drm/drm_debugfs.h> 20#include <drm/drm_drv.h> 21#include <drm/drm_edid.h> 22#include <drm/drm_file.h> 23#include <drm/drm_print.h> 24#include <drm/drm_probe_helper.h> 25 26#include <sound/hdmi-codec.h> 27 28#include "sti_hdmi.h" 29#include "sti_hdmi_tx3g4c28phy.h" 30#include "sti_vtg.h" 31 32#define HDMI_CFG 0x0000 33#define HDMI_INT_EN 0x0004 34#define HDMI_INT_STA 0x0008 35#define HDMI_INT_CLR 0x000C 36#define HDMI_STA 0x0010 37#define HDMI_ACTIVE_VID_XMIN 0x0100 38#define HDMI_ACTIVE_VID_XMAX 0x0104 39#define HDMI_ACTIVE_VID_YMIN 0x0108 40#define HDMI_ACTIVE_VID_YMAX 0x010C 41#define HDMI_DFLT_CHL0_DAT 0x0110 42#define HDMI_DFLT_CHL1_DAT 0x0114 43#define HDMI_DFLT_CHL2_DAT 0x0118 44#define HDMI_AUDIO_CFG 0x0200 45#define HDMI_SPDIF_FIFO_STATUS 0x0204 46#define HDMI_SW_DI_1_HEAD_WORD 0x0210 47#define HDMI_SW_DI_1_PKT_WORD0 0x0214 48#define HDMI_SW_DI_1_PKT_WORD1 0x0218 49#define HDMI_SW_DI_1_PKT_WORD2 0x021C 50#define HDMI_SW_DI_1_PKT_WORD3 0x0220 51#define HDMI_SW_DI_1_PKT_WORD4 0x0224 52#define HDMI_SW_DI_1_PKT_WORD5 0x0228 53#define HDMI_SW_DI_1_PKT_WORD6 0x022C 54#define HDMI_SW_DI_CFG 0x0230 55#define HDMI_SAMPLE_FLAT_MASK 0x0244 56#define HDMI_AUDN 0x0400 57#define HDMI_AUD_CTS 0x0404 58#define HDMI_SW_DI_2_HEAD_WORD 0x0600 59#define HDMI_SW_DI_2_PKT_WORD0 0x0604 60#define HDMI_SW_DI_2_PKT_WORD1 0x0608 61#define HDMI_SW_DI_2_PKT_WORD2 0x060C 62#define HDMI_SW_DI_2_PKT_WORD3 0x0610 63#define HDMI_SW_DI_2_PKT_WORD4 0x0614 64#define HDMI_SW_DI_2_PKT_WORD5 0x0618 65#define HDMI_SW_DI_2_PKT_WORD6 0x061C 66#define HDMI_SW_DI_3_HEAD_WORD 0x0620 67#define HDMI_SW_DI_3_PKT_WORD0 0x0624 68#define HDMI_SW_DI_3_PKT_WORD1 0x0628 69#define HDMI_SW_DI_3_PKT_WORD2 0x062C 70#define HDMI_SW_DI_3_PKT_WORD3 0x0630 71#define HDMI_SW_DI_3_PKT_WORD4 0x0634 72#define HDMI_SW_DI_3_PKT_WORD5 0x0638 73#define HDMI_SW_DI_3_PKT_WORD6 0x063C 74 75#define HDMI_IFRAME_SLOT_AVI 1 76#define HDMI_IFRAME_SLOT_AUDIO 2 77#define HDMI_IFRAME_SLOT_VENDOR 3 78 79#define XCAT(prefix, x, suffix) prefix ## x ## suffix 80#define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD) 81#define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0) 82#define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1) 83#define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2) 84#define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3) 85#define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4) 86#define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5) 87#define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6) 88 89#define HDMI_SW_DI_MAX_WORD 7 90 91#define HDMI_IFRAME_DISABLED 0x0 92#define HDMI_IFRAME_SINGLE_SHOT 0x1 93#define HDMI_IFRAME_FIELD 0x2 94#define HDMI_IFRAME_FRAME 0x3 95#define HDMI_IFRAME_MASK 0x3 96#define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */ 97 98#define HDMI_CFG_DEVICE_EN BIT(0) 99#define HDMI_CFG_HDMI_NOT_DVI BIT(1) 100#define HDMI_CFG_HDCP_EN BIT(2) 101#define HDMI_CFG_ESS_NOT_OESS BIT(3) 102#define HDMI_CFG_H_SYNC_POL_NEG BIT(4) 103#define HDMI_CFG_V_SYNC_POL_NEG BIT(6) 104#define HDMI_CFG_422_EN BIT(8) 105#define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12) 106#define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13) 107#define HDMI_CFG_SW_RST_EN BIT(31) 108 109#define HDMI_INT_GLOBAL BIT(0) 110#define HDMI_INT_SW_RST BIT(1) 111#define HDMI_INT_PIX_CAP BIT(3) 112#define HDMI_INT_HOT_PLUG BIT(4) 113#define HDMI_INT_DLL_LCK BIT(5) 114#define HDMI_INT_NEW_FRAME BIT(6) 115#define HDMI_INT_GENCTRL_PKT BIT(7) 116#define HDMI_INT_AUDIO_FIFO_XRUN BIT(8) 117#define HDMI_INT_SINK_TERM_PRESENT BIT(11) 118 119#define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \ 120 | HDMI_INT_DLL_LCK \ 121 | HDMI_INT_HOT_PLUG \ 122 | HDMI_INT_GLOBAL) 123 124#define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \ 125 | HDMI_INT_AUDIO_FIFO_XRUN \ 126 | HDMI_INT_GENCTRL_PKT \ 127 | HDMI_INT_NEW_FRAME \ 128 | HDMI_INT_DLL_LCK \ 129 | HDMI_INT_HOT_PLUG \ 130 | HDMI_INT_PIX_CAP \ 131 | HDMI_INT_SW_RST \ 132 | HDMI_INT_GLOBAL) 133 134#define HDMI_STA_SW_RST BIT(1) 135 136#define HDMI_AUD_CFG_8CH BIT(0) 137#define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1) 138#define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2) 139#define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2)) 140#define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12) 141#define HDMI_AUD_CFG_DTS_INVALID BIT(16) 142#define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21)) 143#define HDMI_AUD_CFG_CH12_VALID BIT(28) 144#define HDMI_AUD_CFG_CH34_VALID BIT(29) 145#define HDMI_AUD_CFG_CH56_VALID BIT(30) 146#define HDMI_AUD_CFG_CH78_VALID BIT(31) 147 148/* sample flat mask */ 149#define HDMI_SAMPLE_FLAT_NO 0 150#define HDMI_SAMPLE_FLAT_SP0 BIT(0) 151#define HDMI_SAMPLE_FLAT_SP1 BIT(1) 152#define HDMI_SAMPLE_FLAT_SP2 BIT(2) 153#define HDMI_SAMPLE_FLAT_SP3 BIT(3) 154#define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\ 155 HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3) 156 157#define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) 158#define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) 159#define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) 160 161struct sti_hdmi_connector { 162 struct drm_connector drm_connector; 163 struct drm_encoder *encoder; 164 struct sti_hdmi *hdmi; 165 struct drm_property *colorspace_property; 166}; 167 168#define to_sti_hdmi_connector(x) \ 169 container_of(x, struct sti_hdmi_connector, drm_connector) 170 171static struct sti_hdmi *drm_bridge_to_sti_hdmi(struct drm_bridge *bridge) 172{ 173 return container_of(bridge, struct sti_hdmi, bridge); 174} 175 176static const struct drm_prop_enum_list colorspace_mode_names[] = { 177 { HDMI_COLORSPACE_RGB, "rgb" }, 178 { HDMI_COLORSPACE_YUV422, "yuv422" }, 179 { HDMI_COLORSPACE_YUV444, "yuv444" }, 180}; 181 182u32 hdmi_read(struct sti_hdmi *hdmi, int offset) 183{ 184 return readl(hdmi->regs + offset); 185} 186 187void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset) 188{ 189 writel(val, hdmi->regs + offset); 190} 191 192/* 193 * HDMI interrupt handler threaded 194 * 195 * @irq: irq number 196 * @arg: connector structure 197 */ 198static irqreturn_t hdmi_irq_thread(int irq, void *arg) 199{ 200 struct sti_hdmi *hdmi = arg; 201 202 /* Hot plug/unplug IRQ */ 203 if (hdmi->irq_status & HDMI_INT_HOT_PLUG) { 204 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; 205 if (hdmi->drm_dev) 206 drm_helper_hpd_irq_event(hdmi->drm_dev); 207 } 208 209 /* Sw reset and PLL lock are exclusive so we can use the same 210 * event to signal them 211 */ 212 if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) { 213 hdmi->event_received = true; 214 wake_up_interruptible(&hdmi->wait_event); 215 } 216 217 /* Audio FIFO underrun IRQ */ 218 if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN) 219 DRM_INFO("Warning: audio FIFO underrun occurs!\n"); 220 221 return IRQ_HANDLED; 222} 223 224/* 225 * HDMI interrupt handler 226 * 227 * @irq: irq number 228 * @arg: connector structure 229 */ 230static irqreturn_t hdmi_irq(int irq, void *arg) 231{ 232 struct sti_hdmi *hdmi = arg; 233 234 /* read interrupt status */ 235 hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA); 236 237 /* clear interrupt status */ 238 hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR); 239 240 /* force sync bus write */ 241 hdmi_read(hdmi, HDMI_INT_STA); 242 243 return IRQ_WAKE_THREAD; 244} 245 246/* 247 * Set hdmi active area depending on the drm display mode selected 248 * 249 * @hdmi: pointer on the hdmi internal structure 250 */ 251static void hdmi_active_area(struct sti_hdmi *hdmi) 252{ 253 u32 xmin, xmax; 254 u32 ymin, ymax; 255 256 xmin = sti_vtg_get_pixel_number(hdmi->mode, 1); 257 xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay); 258 ymin = sti_vtg_get_line_number(hdmi->mode, 0); 259 ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1); 260 261 hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN); 262 hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX); 263 hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN); 264 hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX); 265} 266 267/* 268 * Overall hdmi configuration 269 * 270 * @hdmi: pointer on the hdmi internal structure 271 */ 272static void hdmi_config(struct sti_hdmi *hdmi) 273{ 274 struct drm_connector *connector = hdmi->drm_connector; 275 u32 conf; 276 277 DRM_DEBUG_DRIVER("\n"); 278 279 /* Clear overrun and underrun fifo */ 280 conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR; 281 282 /* Select encryption type and the framing mode */ 283 conf |= HDMI_CFG_ESS_NOT_OESS; 284 if (connector->display_info.is_hdmi) 285 conf |= HDMI_CFG_HDMI_NOT_DVI; 286 287 /* Set Hsync polarity */ 288 if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) { 289 DRM_DEBUG_DRIVER("H Sync Negative\n"); 290 conf |= HDMI_CFG_H_SYNC_POL_NEG; 291 } 292 293 /* Set Vsync polarity */ 294 if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) { 295 DRM_DEBUG_DRIVER("V Sync Negative\n"); 296 conf |= HDMI_CFG_V_SYNC_POL_NEG; 297 } 298 299 /* Enable HDMI */ 300 conf |= HDMI_CFG_DEVICE_EN; 301 302 hdmi_write(hdmi, conf, HDMI_CFG); 303} 304 305/* 306 * Helper to reset info frame 307 * 308 * @hdmi: pointer on the hdmi internal structure 309 * @slot: infoframe to reset 310 */ 311static void hdmi_infoframe_reset(struct sti_hdmi *hdmi, 312 u32 slot) 313{ 314 u32 val, i; 315 u32 head_offset, pack_offset; 316 317 switch (slot) { 318 case HDMI_IFRAME_SLOT_AVI: 319 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); 320 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); 321 break; 322 case HDMI_IFRAME_SLOT_AUDIO: 323 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); 324 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); 325 break; 326 case HDMI_IFRAME_SLOT_VENDOR: 327 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); 328 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); 329 break; 330 default: 331 DRM_ERROR("unsupported infoframe slot: %#x\n", slot); 332 return; 333 } 334 335 /* Disable transmission for the selected slot */ 336 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 337 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); 338 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 339 340 /* Reset info frame registers */ 341 hdmi_write(hdmi, 0x0, head_offset); 342 for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32)) 343 hdmi_write(hdmi, 0x0, pack_offset + i); 344} 345 346/* 347 * Helper to concatenate infoframe in 32 bits word 348 * 349 * @ptr: pointer on the hdmi internal structure 350 * @size: size to write 351 */ 352static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size) 353{ 354 unsigned long value = 0; 355 size_t i; 356 357 for (i = size; i > 0; i--) 358 value = (value << 8) | ptr[i - 1]; 359 360 return value; 361} 362 363/* 364 * Helper to write info frame 365 * 366 * @hdmi: pointer on the hdmi internal structure 367 * @data: infoframe to write 368 * @size: size to write 369 */ 370static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi, 371 const u8 *data, 372 size_t size) 373{ 374 const u8 *ptr = data; 375 u32 val, slot, mode, i; 376 u32 head_offset, pack_offset; 377 378 switch (*ptr) { 379 case HDMI_INFOFRAME_TYPE_AVI: 380 slot = HDMI_IFRAME_SLOT_AVI; 381 mode = HDMI_IFRAME_FIELD; 382 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); 383 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); 384 break; 385 case HDMI_INFOFRAME_TYPE_AUDIO: 386 slot = HDMI_IFRAME_SLOT_AUDIO; 387 mode = HDMI_IFRAME_FRAME; 388 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); 389 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); 390 break; 391 case HDMI_INFOFRAME_TYPE_VENDOR: 392 slot = HDMI_IFRAME_SLOT_VENDOR; 393 mode = HDMI_IFRAME_FRAME; 394 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); 395 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); 396 break; 397 default: 398 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr); 399 return; 400 } 401 402 /* Disable transmission slot for updated infoframe */ 403 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 404 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); 405 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 406 407 val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++); 408 val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++); 409 val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++); 410 writel(val, hdmi->regs + head_offset); 411 412 /* 413 * Each subpack contains 4 bytes 414 * The First Bytes of the first subpacket must contain the checksum 415 * Packet size is increase by one. 416 */ 417 size = size - HDMI_INFOFRAME_HEADER_SIZE + 1; 418 for (i = 0; i < size; i += sizeof(u32)) { 419 size_t num; 420 421 num = min_t(size_t, size - i, sizeof(u32)); 422 val = hdmi_infoframe_subpack(ptr, num); 423 ptr += sizeof(u32); 424 writel(val, hdmi->regs + pack_offset + i); 425 } 426 427 /* Enable transmission slot for updated infoframe */ 428 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 429 val |= HDMI_IFRAME_CFG_DI_N(mode, slot); 430 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 431} 432 433/* 434 * Prepare and configure the AVI infoframe 435 * 436 * AVI infoframe are transmitted at least once per two video field and 437 * contains information about HDMI transmission mode such as color space, 438 * colorimetry, ... 439 * 440 * @hdmi: pointer on the hdmi internal structure 441 * 442 * Return negative value if error occurs 443 */ 444static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi) 445{ 446 struct drm_display_mode *mode = &hdmi->mode; 447 struct hdmi_avi_infoframe infoframe; 448 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 449 int ret; 450 451 DRM_DEBUG_DRIVER("\n"); 452 453 ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, 454 hdmi->drm_connector, mode); 455 if (ret < 0) { 456 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret); 457 return ret; 458 } 459 460 /* fixed infoframe configuration not linked to the mode */ 461 infoframe.colorspace = hdmi->colorspace; 462 infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 463 infoframe.colorimetry = HDMI_COLORIMETRY_NONE; 464 465 ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer)); 466 if (ret < 0) { 467 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); 468 return ret; 469 } 470 471 hdmi_infoframe_write_infopack(hdmi, buffer, ret); 472 473 return 0; 474} 475 476/* 477 * Prepare and configure the AUDIO infoframe 478 * 479 * AUDIO infoframe are transmitted once per frame and 480 * contains information about HDMI transmission mode such as audio codec, 481 * sample size, ... 482 * 483 * @hdmi: pointer on the hdmi internal structure 484 * 485 * Return negative value if error occurs 486 */ 487static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi) 488{ 489 struct hdmi_audio_params *audio = &hdmi->audio; 490 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 491 int ret, val; 492 493 DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__, 494 audio->enabled ? "enable" : "disable"); 495 if (audio->enabled) { 496 /* set audio parameters stored*/ 497 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer, 498 sizeof(buffer)); 499 if (ret < 0) { 500 DRM_ERROR("failed to pack audio infoframe: %d\n", ret); 501 return ret; 502 } 503 hdmi_infoframe_write_infopack(hdmi, buffer, ret); 504 } else { 505 /*disable audio info frame transmission */ 506 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 507 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 508 HDMI_IFRAME_SLOT_AUDIO); 509 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 510 } 511 512 return 0; 513} 514 515/* 516 * Prepare and configure the VS infoframe 517 * 518 * Vendor Specific infoframe are transmitted once per frame and 519 * contains vendor specific information. 520 * 521 * @hdmi: pointer on the hdmi internal structure 522 * 523 * Return negative value if error occurs 524 */ 525#define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6 526static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi) 527{ 528 struct drm_display_mode *mode = &hdmi->mode; 529 struct hdmi_vendor_infoframe infoframe; 530 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE]; 531 int ret; 532 533 DRM_DEBUG_DRIVER("\n"); 534 535 ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe, 536 hdmi->drm_connector, 537 mode); 538 if (ret < 0) { 539 /* 540 * Going into that statement does not means vendor infoframe 541 * fails. It just informed us that vendor infoframe is not 542 * needed for the selected mode. Only 4k or stereoscopic 3D 543 * mode requires vendor infoframe. So just simply return 0. 544 */ 545 return 0; 546 } 547 548 ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer)); 549 if (ret < 0) { 550 DRM_ERROR("failed to pack VS infoframe: %d\n", ret); 551 return ret; 552 } 553 554 hdmi_infoframe_write_infopack(hdmi, buffer, ret); 555 556 return 0; 557} 558 559#define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */ 560 561/* 562 * Software reset of the hdmi subsystem 563 * 564 * @hdmi: pointer on the hdmi internal structure 565 * 566 */ 567static void hdmi_swreset(struct sti_hdmi *hdmi) 568{ 569 u32 val; 570 571 DRM_DEBUG_DRIVER("\n"); 572 573 /* Enable hdmi_audio clock only during hdmi reset */ 574 if (clk_prepare_enable(hdmi->clk_audio)) 575 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n"); 576 577 /* Sw reset */ 578 hdmi->event_received = false; 579 580 val = hdmi_read(hdmi, HDMI_CFG); 581 val |= HDMI_CFG_SW_RST_EN; 582 hdmi_write(hdmi, val, HDMI_CFG); 583 584 /* Wait reset completed */ 585 wait_event_interruptible_timeout(hdmi->wait_event, 586 hdmi->event_received, 587 msecs_to_jiffies 588 (HDMI_TIMEOUT_SWRESET)); 589 590 /* 591 * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is 592 * set to '1' and clk_audio is running. 593 */ 594 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0) 595 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n"); 596 597 val = hdmi_read(hdmi, HDMI_CFG); 598 val &= ~HDMI_CFG_SW_RST_EN; 599 hdmi_write(hdmi, val, HDMI_CFG); 600 601 /* Disable hdmi_audio clock. Not used anymore for drm purpose */ 602 clk_disable_unprepare(hdmi->clk_audio); 603} 604 605#define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2) 606#define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2) 607#define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \ 608 hdmi_read(hdmi, reg)) 609#define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot)) 610 611static void hdmi_dbg_cfg(struct seq_file *s, int val) 612{ 613 int tmp; 614 615 seq_putc(s, '\t'); 616 tmp = val & HDMI_CFG_HDMI_NOT_DVI; 617 DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI"); 618 seq_puts(s, "\t\t\t\t\t"); 619 tmp = val & HDMI_CFG_HDCP_EN; 620 DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable"); 621 seq_puts(s, "\t\t\t\t\t"); 622 tmp = val & HDMI_CFG_ESS_NOT_OESS; 623 DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable"); 624 seq_puts(s, "\t\t\t\t\t"); 625 tmp = val & HDMI_CFG_H_SYNC_POL_NEG; 626 DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal"); 627 seq_puts(s, "\t\t\t\t\t"); 628 tmp = val & HDMI_CFG_V_SYNC_POL_NEG; 629 DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal"); 630 seq_puts(s, "\t\t\t\t\t"); 631 tmp = val & HDMI_CFG_422_EN; 632 DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable"); 633} 634 635static void hdmi_dbg_sta(struct seq_file *s, int val) 636{ 637 int tmp; 638 639 seq_putc(s, '\t'); 640 tmp = (val & HDMI_STA_DLL_LCK); 641 DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked"); 642 seq_puts(s, "\t\t\t\t\t"); 643 tmp = (val & HDMI_STA_HOT_PLUG); 644 DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected"); 645} 646 647static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val) 648{ 649 int tmp; 650 char *const en_di[] = {"no transmission", 651 "single transmission", 652 "once every field", 653 "once every frame"}; 654 655 seq_putc(s, '\t'); 656 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1)); 657 DBGFS_PRINT_STR("Data island 1:", en_di[tmp]); 658 seq_puts(s, "\t\t\t\t\t"); 659 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4; 660 DBGFS_PRINT_STR("Data island 2:", en_di[tmp]); 661 seq_puts(s, "\t\t\t\t\t"); 662 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8; 663 DBGFS_PRINT_STR("Data island 3:", en_di[tmp]); 664 seq_puts(s, "\t\t\t\t\t"); 665 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12; 666 DBGFS_PRINT_STR("Data island 4:", en_di[tmp]); 667 seq_puts(s, "\t\t\t\t\t"); 668 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16; 669 DBGFS_PRINT_STR("Data island 5:", en_di[tmp]); 670 seq_puts(s, "\t\t\t\t\t"); 671 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20; 672 DBGFS_PRINT_STR("Data island 6:", en_di[tmp]); 673} 674 675static int hdmi_dbg_show(struct seq_file *s, void *data) 676{ 677 struct drm_info_node *node = s->private; 678 struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data; 679 680 seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs); 681 DBGFS_DUMP("\n", HDMI_CFG); 682 hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG)); 683 DBGFS_DUMP("", HDMI_INT_EN); 684 DBGFS_DUMP("\n", HDMI_STA); 685 hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA)); 686 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN); 687 seq_putc(s, '\t'); 688 DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN)); 689 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX); 690 seq_putc(s, '\t'); 691 DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX)); 692 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN); 693 seq_putc(s, '\t'); 694 DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN)); 695 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX); 696 seq_putc(s, '\t'); 697 DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX)); 698 DBGFS_DUMP("", HDMI_SW_DI_CFG); 699 hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG)); 700 701 DBGFS_DUMP("\n", HDMI_AUDIO_CFG); 702 DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS); 703 DBGFS_DUMP("\n", HDMI_AUDN); 704 705 seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):", 706 HDMI_IFRAME_SLOT_AVI); 707 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI); 708 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI); 709 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI); 710 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI); 711 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI); 712 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI); 713 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI); 714 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI); 715 seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):", 716 HDMI_IFRAME_SLOT_AUDIO); 717 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO); 718 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO); 719 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO); 720 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO); 721 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO); 722 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO); 723 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO); 724 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO); 725 seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):", 726 HDMI_IFRAME_SLOT_VENDOR); 727 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR); 728 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR); 729 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR); 730 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR); 731 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR); 732 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR); 733 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR); 734 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR); 735 seq_putc(s, '\n'); 736 return 0; 737} 738 739static struct drm_info_list hdmi_debugfs_files[] = { 740 { "hdmi", hdmi_dbg_show, 0, NULL }, 741}; 742 743static void hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor) 744{ 745 unsigned int i; 746 747 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++) 748 hdmi_debugfs_files[i].data = hdmi; 749 750 drm_debugfs_create_files(hdmi_debugfs_files, 751 ARRAY_SIZE(hdmi_debugfs_files), 752 minor->debugfs_root, minor); 753} 754 755static void sti_hdmi_disable(struct drm_bridge *bridge) 756{ 757 struct sti_hdmi *hdmi = drm_bridge_to_sti_hdmi(bridge); 758 759 u32 val = hdmi_read(hdmi, HDMI_CFG); 760 761 if (!hdmi->enabled) 762 return; 763 764 DRM_DEBUG_DRIVER("\n"); 765 766 /* Disable HDMI */ 767 val &= ~HDMI_CFG_DEVICE_EN; 768 hdmi_write(hdmi, val, HDMI_CFG); 769 770 hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR); 771 772 /* Stop the phy */ 773 hdmi->phy_ops->stop(hdmi); 774 775 /* Reset info frame transmission */ 776 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI); 777 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO); 778 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR); 779 780 /* Set the default channel data to be a dark red */ 781 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT); 782 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT); 783 hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT); 784 785 /* Disable/unprepare hdmi clock */ 786 clk_disable_unprepare(hdmi->clk_phy); 787 clk_disable_unprepare(hdmi->clk_tmds); 788 clk_disable_unprepare(hdmi->clk_pix); 789 790 hdmi->enabled = false; 791 792 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID); 793} 794 795/* 796 * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent 797 * clocks. None-coherent clocks means that audio and TMDS clocks have not the 798 * same source (drifts between clocks). In this case assumption is that CTS is 799 * automatically calculated by hardware. 800 * 801 * @audio_fs: audio frame clock frequency in Hz 802 * 803 * Values computed are based on table described in HDMI specification 1.4b 804 * 805 * Returns n value. 806 */ 807static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs) 808{ 809 unsigned int n; 810 811 switch (audio_fs) { 812 case 32000: 813 n = 4096; 814 break; 815 case 44100: 816 n = 6272; 817 break; 818 case 48000: 819 n = 6144; 820 break; 821 case 88200: 822 n = 6272 * 2; 823 break; 824 case 96000: 825 n = 6144 * 2; 826 break; 827 case 176400: 828 n = 6272 * 4; 829 break; 830 case 192000: 831 n = 6144 * 4; 832 break; 833 default: 834 /* Not pre-defined, recommended value: 128 * fs / 1000 */ 835 n = (audio_fs * 128) / 1000; 836 } 837 838 return n; 839} 840 841static int hdmi_audio_configure(struct sti_hdmi *hdmi) 842{ 843 int audio_cfg, n; 844 struct hdmi_audio_params *params = &hdmi->audio; 845 struct hdmi_audio_infoframe *info = ¶ms->cea; 846 847 DRM_DEBUG_DRIVER("\n"); 848 849 if (!hdmi->enabled) 850 return 0; 851 852 /* update N parameter */ 853 n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate); 854 855 DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n", 856 params->sample_rate, hdmi->mode.clock * 1000, n); 857 hdmi_write(hdmi, n, HDMI_AUDN); 858 859 /* update HDMI registers according to configuration */ 860 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | 861 HDMI_AUD_CFG_ONE_BIT_INVALID; 862 863 switch (info->channels) { 864 case 8: 865 audio_cfg |= HDMI_AUD_CFG_CH78_VALID; 866 fallthrough; 867 case 6: 868 audio_cfg |= HDMI_AUD_CFG_CH56_VALID; 869 fallthrough; 870 case 4: 871 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH; 872 fallthrough; 873 case 2: 874 audio_cfg |= HDMI_AUD_CFG_CH12_VALID; 875 break; 876 default: 877 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n", 878 info->channels); 879 return -EINVAL; 880 } 881 882 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); 883 884 return hdmi_audio_infoframe_config(hdmi); 885} 886 887static void sti_hdmi_pre_enable(struct drm_bridge *bridge) 888{ 889 struct sti_hdmi *hdmi = drm_bridge_to_sti_hdmi(bridge); 890 891 DRM_DEBUG_DRIVER("\n"); 892 893 if (hdmi->enabled) 894 return; 895 896 /* Prepare/enable clocks */ 897 if (clk_prepare_enable(hdmi->clk_pix)) 898 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n"); 899 if (clk_prepare_enable(hdmi->clk_tmds)) 900 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n"); 901 if (clk_prepare_enable(hdmi->clk_phy)) 902 DRM_ERROR("Failed to prepare/enable hdmi_rejection_pll clk\n"); 903 904 hdmi->enabled = true; 905 906 /* Program hdmi serializer and start phy */ 907 if (!hdmi->phy_ops->start(hdmi)) { 908 DRM_ERROR("Unable to start hdmi phy\n"); 909 return; 910 } 911 912 /* Program hdmi active area */ 913 hdmi_active_area(hdmi); 914 915 /* Enable working interrupts */ 916 hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN); 917 918 /* Program hdmi config */ 919 hdmi_config(hdmi); 920 921 /* Program AVI infoframe */ 922 if (hdmi_avi_infoframe_config(hdmi)) 923 DRM_ERROR("Unable to configure AVI infoframe\n"); 924 925 if (hdmi->audio.enabled) { 926 if (hdmi_audio_configure(hdmi)) 927 DRM_ERROR("Unable to configure audio\n"); 928 } else { 929 hdmi_audio_infoframe_config(hdmi); 930 } 931 932 /* Program VS infoframe */ 933 if (hdmi_vendor_infoframe_config(hdmi)) 934 DRM_ERROR("Unable to configure VS infoframe\n"); 935 936 /* Sw reset */ 937 hdmi_swreset(hdmi); 938} 939 940static void sti_hdmi_set_mode(struct drm_bridge *bridge, 941 const struct drm_display_mode *mode, 942 const struct drm_display_mode *adjusted_mode) 943{ 944 struct sti_hdmi *hdmi = drm_bridge_to_sti_hdmi(bridge); 945 int ret; 946 947 DRM_DEBUG_DRIVER("\n"); 948 949 /* Copy the drm display mode in the connector local structure */ 950 drm_mode_copy(&hdmi->mode, mode); 951 952 /* Update clock framerate according to the selected mode */ 953 ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000); 954 if (ret < 0) { 955 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n", 956 mode->clock * 1000); 957 return; 958 } 959 ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000); 960 if (ret < 0) { 961 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n", 962 mode->clock * 1000); 963 return; 964 } 965} 966 967static void sti_hdmi_bridge_nope(struct drm_bridge *bridge) 968{ 969 /* do nothing */ 970} 971 972static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = { 973 .pre_enable = sti_hdmi_pre_enable, 974 .enable = sti_hdmi_bridge_nope, 975 .disable = sti_hdmi_disable, 976 .post_disable = sti_hdmi_bridge_nope, 977 .mode_set = sti_hdmi_set_mode, 978}; 979 980static int sti_hdmi_connector_get_modes(struct drm_connector *connector) 981{ 982 const struct drm_display_info *info = &connector->display_info; 983 struct sti_hdmi_connector *hdmi_connector 984 = to_sti_hdmi_connector(connector); 985 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 986 const struct drm_edid *drm_edid; 987 int count; 988 989 DRM_DEBUG_DRIVER("\n"); 990 991 drm_edid = drm_edid_read(connector); 992 993 drm_edid_connector_update(connector, drm_edid); 994 995 cec_notifier_set_phys_addr(hdmi->notifier, 996 connector->display_info.source_physical_address); 997 998 if (!drm_edid) 999 goto fail; 1000 1001 count = drm_edid_connector_add_modes(connector); 1002 1003 DRM_DEBUG_KMS("%s : %dx%d cm\n", 1004 info->is_hdmi ? "hdmi monitor" : "dvi monitor", 1005 info->width_mm / 10, info->height_mm / 10); 1006 1007 drm_edid_free(drm_edid); 1008 return count; 1009 1010fail: 1011 DRM_ERROR("Can't read HDMI EDID\n"); 1012 return 0; 1013} 1014 1015#define CLK_TOLERANCE_HZ 50 1016 1017static enum drm_mode_status 1018sti_hdmi_connector_mode_valid(struct drm_connector *connector, 1019 const struct drm_display_mode *mode) 1020{ 1021 int target = mode->clock * 1000; 1022 int target_min = target - CLK_TOLERANCE_HZ; 1023 int target_max = target + CLK_TOLERANCE_HZ; 1024 int result; 1025 struct sti_hdmi_connector *hdmi_connector 1026 = to_sti_hdmi_connector(connector); 1027 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1028 1029 1030 result = clk_round_rate(hdmi->clk_pix, target); 1031 1032 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", 1033 target, result); 1034 1035 if ((result < target_min) || (result > target_max)) { 1036 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target); 1037 return MODE_BAD; 1038 } 1039 1040 return MODE_OK; 1041} 1042 1043static const 1044struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = { 1045 .get_modes = sti_hdmi_connector_get_modes, 1046 .mode_valid = sti_hdmi_connector_mode_valid, 1047}; 1048 1049/* get detection status of display device */ 1050static enum drm_connector_status 1051sti_hdmi_connector_detect(struct drm_connector *connector, bool force) 1052{ 1053 struct sti_hdmi_connector *hdmi_connector 1054 = to_sti_hdmi_connector(connector); 1055 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1056 1057 DRM_DEBUG_DRIVER("\n"); 1058 1059 if (hdmi->hpd) { 1060 DRM_DEBUG_DRIVER("hdmi cable connected\n"); 1061 return connector_status_connected; 1062 } 1063 1064 DRM_DEBUG_DRIVER("hdmi cable disconnected\n"); 1065 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID); 1066 return connector_status_disconnected; 1067} 1068 1069static void sti_hdmi_connector_init_property(struct drm_device *drm_dev, 1070 struct drm_connector *connector) 1071{ 1072 struct sti_hdmi_connector *hdmi_connector 1073 = to_sti_hdmi_connector(connector); 1074 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1075 struct drm_property *prop; 1076 1077 /* colorspace property */ 1078 hdmi->colorspace = DEFAULT_COLORSPACE_MODE; 1079 prop = drm_property_create_enum(drm_dev, 0, "colorspace", 1080 colorspace_mode_names, 1081 ARRAY_SIZE(colorspace_mode_names)); 1082 if (!prop) { 1083 DRM_ERROR("fails to create colorspace property\n"); 1084 return; 1085 } 1086 hdmi_connector->colorspace_property = prop; 1087 drm_object_attach_property(&connector->base, prop, hdmi->colorspace); 1088} 1089 1090static int 1091sti_hdmi_connector_set_property(struct drm_connector *connector, 1092 struct drm_connector_state *state, 1093 struct drm_property *property, 1094 uint64_t val) 1095{ 1096 struct sti_hdmi_connector *hdmi_connector 1097 = to_sti_hdmi_connector(connector); 1098 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1099 1100 if (property == hdmi_connector->colorspace_property) { 1101 hdmi->colorspace = val; 1102 return 0; 1103 } 1104 1105 DRM_ERROR("failed to set hdmi connector property\n"); 1106 return -EINVAL; 1107} 1108 1109static int 1110sti_hdmi_connector_get_property(struct drm_connector *connector, 1111 const struct drm_connector_state *state, 1112 struct drm_property *property, 1113 uint64_t *val) 1114{ 1115 struct sti_hdmi_connector *hdmi_connector 1116 = to_sti_hdmi_connector(connector); 1117 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1118 1119 if (property == hdmi_connector->colorspace_property) { 1120 *val = hdmi->colorspace; 1121 return 0; 1122 } 1123 1124 DRM_ERROR("failed to get hdmi connector property\n"); 1125 return -EINVAL; 1126} 1127 1128static int sti_hdmi_late_register(struct drm_connector *connector) 1129{ 1130 struct sti_hdmi_connector *hdmi_connector 1131 = to_sti_hdmi_connector(connector); 1132 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1133 1134 hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary); 1135 1136 return 0; 1137} 1138 1139static const struct drm_connector_funcs sti_hdmi_connector_funcs = { 1140 .fill_modes = drm_helper_probe_single_connector_modes, 1141 .detect = sti_hdmi_connector_detect, 1142 .destroy = drm_connector_cleanup, 1143 .reset = drm_atomic_helper_connector_reset, 1144 .atomic_set_property = sti_hdmi_connector_set_property, 1145 .atomic_get_property = sti_hdmi_connector_get_property, 1146 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1147 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1148 .late_register = sti_hdmi_late_register, 1149}; 1150 1151static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev) 1152{ 1153 struct drm_encoder *encoder; 1154 1155 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1156 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1157 return encoder; 1158 } 1159 1160 return NULL; 1161} 1162 1163static void hdmi_audio_shutdown(struct device *dev, void *data) 1164{ 1165 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1166 int audio_cfg; 1167 1168 DRM_DEBUG_DRIVER("\n"); 1169 1170 /* disable audio */ 1171 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | 1172 HDMI_AUD_CFG_ONE_BIT_INVALID; 1173 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); 1174 1175 hdmi->audio.enabled = false; 1176 hdmi_audio_infoframe_config(hdmi); 1177} 1178 1179static int hdmi_audio_hw_params(struct device *dev, 1180 void *data, 1181 struct hdmi_codec_daifmt *daifmt, 1182 struct hdmi_codec_params *params) 1183{ 1184 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1185 int ret; 1186 1187 DRM_DEBUG_DRIVER("\n"); 1188 1189 if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv || 1190 daifmt->frame_clk_inv || daifmt->bit_clk_provider || 1191 daifmt->frame_clk_provider) { 1192 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1193 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1194 daifmt->bit_clk_provider, 1195 daifmt->frame_clk_provider); 1196 return -EINVAL; 1197 } 1198 1199 hdmi->audio.sample_width = params->sample_width; 1200 hdmi->audio.sample_rate = params->sample_rate; 1201 hdmi->audio.cea = params->cea; 1202 1203 hdmi->audio.enabled = true; 1204 1205 ret = hdmi_audio_configure(hdmi); 1206 if (ret < 0) 1207 return ret; 1208 1209 return 0; 1210} 1211 1212static int hdmi_audio_mute(struct device *dev, void *data, 1213 bool enable, int direction) 1214{ 1215 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1216 1217 DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable"); 1218 1219 if (enable) 1220 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK); 1221 else 1222 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK); 1223 1224 return 0; 1225} 1226 1227static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1228{ 1229 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1230 struct drm_connector *connector = hdmi->drm_connector; 1231 1232 DRM_DEBUG_DRIVER("\n"); 1233 mutex_lock(&connector->eld_mutex); 1234 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1235 mutex_unlock(&connector->eld_mutex); 1236 1237 return 0; 1238} 1239 1240static const struct hdmi_codec_ops audio_codec_ops = { 1241 .hw_params = hdmi_audio_hw_params, 1242 .audio_shutdown = hdmi_audio_shutdown, 1243 .mute_stream = hdmi_audio_mute, 1244 .get_eld = hdmi_audio_get_eld, 1245}; 1246 1247static int sti_hdmi_register_audio_driver(struct device *dev, 1248 struct sti_hdmi *hdmi) 1249{ 1250 struct hdmi_codec_pdata codec_data = { 1251 .ops = &audio_codec_ops, 1252 .max_i2s_channels = 8, 1253 .i2s = 1, 1254 .no_capture_mute = 1, 1255 }; 1256 1257 DRM_DEBUG_DRIVER("\n"); 1258 1259 hdmi->audio.enabled = false; 1260 1261 hdmi->audio_pdev = platform_device_register_data( 1262 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1263 &codec_data, sizeof(codec_data)); 1264 1265 if (IS_ERR(hdmi->audio_pdev)) 1266 return PTR_ERR(hdmi->audio_pdev); 1267 1268 DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev)); 1269 1270 return 0; 1271} 1272 1273static int sti_hdmi_bind(struct device *dev, struct device *master, void *data) 1274{ 1275 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1276 struct drm_device *drm_dev = data; 1277 struct drm_encoder *encoder; 1278 struct sti_hdmi_connector *connector; 1279 struct cec_connector_info conn_info; 1280 struct drm_connector *drm_connector; 1281 int err; 1282 1283 /* Set the drm device handle */ 1284 hdmi->drm_dev = drm_dev; 1285 1286 encoder = sti_hdmi_find_encoder(drm_dev); 1287 if (!encoder) 1288 return -EINVAL; 1289 1290 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); 1291 if (!connector) 1292 return -EINVAL; 1293 1294 connector->hdmi = hdmi; 1295 1296 drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 1297 1298 connector->encoder = encoder; 1299 1300 drm_connector = (struct drm_connector *)connector; 1301 1302 drm_connector->polled = DRM_CONNECTOR_POLL_HPD; 1303 1304 drm_connector_init_with_ddc(drm_dev, drm_connector, 1305 &sti_hdmi_connector_funcs, 1306 DRM_MODE_CONNECTOR_HDMIA, 1307 hdmi->ddc_adapt); 1308 drm_connector_helper_add(drm_connector, 1309 &sti_hdmi_connector_helper_funcs); 1310 1311 /* initialise property */ 1312 sti_hdmi_connector_init_property(drm_dev, drm_connector); 1313 1314 hdmi->drm_connector = drm_connector; 1315 1316 err = drm_connector_attach_encoder(drm_connector, encoder); 1317 if (err) { 1318 DRM_ERROR("Failed to attach a connector to a encoder\n"); 1319 goto err_sysfs; 1320 } 1321 1322 err = sti_hdmi_register_audio_driver(dev, hdmi); 1323 if (err) { 1324 DRM_ERROR("Failed to attach an audio codec\n"); 1325 goto err_sysfs; 1326 } 1327 1328 /* Initialize audio infoframe */ 1329 err = hdmi_audio_infoframe_init(&hdmi->audio.cea); 1330 if (err) { 1331 DRM_ERROR("Failed to init audio infoframe\n"); 1332 goto err_sysfs; 1333 } 1334 1335 cec_fill_conn_info_from_drm(&conn_info, drm_connector); 1336 hdmi->notifier = cec_notifier_conn_register(&hdmi->dev, NULL, 1337 &conn_info); 1338 if (!hdmi->notifier) { 1339 hdmi->drm_connector = NULL; 1340 return -ENOMEM; 1341 } 1342 1343 /* Enable default interrupts */ 1344 hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN); 1345 1346 return 0; 1347 1348err_sysfs: 1349 hdmi->drm_connector = NULL; 1350 return -EINVAL; 1351} 1352 1353static void sti_hdmi_unbind(struct device *dev, 1354 struct device *master, void *data) 1355{ 1356 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1357 1358 cec_notifier_conn_unregister(hdmi->notifier); 1359} 1360 1361static const struct component_ops sti_hdmi_ops = { 1362 .bind = sti_hdmi_bind, 1363 .unbind = sti_hdmi_unbind, 1364}; 1365 1366static const struct of_device_id hdmi_of_match[] = { 1367 { 1368 .compatible = "st,stih407-hdmi", 1369 .data = &tx3g4c28phy_ops, 1370 }, { 1371 /* end node */ 1372 } 1373}; 1374MODULE_DEVICE_TABLE(of, hdmi_of_match); 1375 1376static int sti_hdmi_probe(struct platform_device *pdev) 1377{ 1378 struct device *dev = &pdev->dev; 1379 struct sti_hdmi *hdmi; 1380 struct device_node *np = dev->of_node; 1381 struct device_node *ddc; 1382 int ret; 1383 1384 DRM_INFO("%s\n", __func__); 1385 1386 hdmi = devm_drm_bridge_alloc(dev, struct sti_hdmi, bridge, &sti_hdmi_bridge_funcs); 1387 if (IS_ERR(hdmi)) 1388 return PTR_ERR(hdmi); 1389 1390 ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0); 1391 if (ddc) { 1392 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc); 1393 of_node_put(ddc); 1394 if (!hdmi->ddc_adapt) 1395 return -EPROBE_DEFER; 1396 } 1397 1398 hdmi->dev = pdev->dev; 1399 hdmi->regs = devm_platform_ioremap_resource_byname(pdev, "hdmi-reg"); 1400 if (IS_ERR(hdmi->regs)) { 1401 ret = PTR_ERR(hdmi->regs); 1402 goto release_adapter; 1403 } 1404 1405 hdmi->phy_ops = (struct hdmi_phy_ops *) 1406 of_match_node(hdmi_of_match, np)->data; 1407 1408 /* Get clock resources */ 1409 hdmi->clk_pix = devm_clk_get(dev, "pix"); 1410 if (IS_ERR(hdmi->clk_pix)) { 1411 DRM_ERROR("Cannot get hdmi_pix clock\n"); 1412 ret = PTR_ERR(hdmi->clk_pix); 1413 goto release_adapter; 1414 } 1415 1416 hdmi->clk_tmds = devm_clk_get(dev, "tmds"); 1417 if (IS_ERR(hdmi->clk_tmds)) { 1418 DRM_ERROR("Cannot get hdmi_tmds clock\n"); 1419 ret = PTR_ERR(hdmi->clk_tmds); 1420 goto release_adapter; 1421 } 1422 1423 hdmi->clk_phy = devm_clk_get(dev, "phy"); 1424 if (IS_ERR(hdmi->clk_phy)) { 1425 DRM_ERROR("Cannot get hdmi_phy clock\n"); 1426 ret = PTR_ERR(hdmi->clk_phy); 1427 goto release_adapter; 1428 } 1429 1430 hdmi->clk_audio = devm_clk_get(dev, "audio"); 1431 if (IS_ERR(hdmi->clk_audio)) { 1432 DRM_ERROR("Cannot get hdmi_audio clock\n"); 1433 ret = PTR_ERR(hdmi->clk_audio); 1434 goto release_adapter; 1435 } 1436 1437 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; 1438 1439 init_waitqueue_head(&hdmi->wait_event); 1440 1441 hdmi->irq = platform_get_irq_byname(pdev, "irq"); 1442 if (hdmi->irq < 0) { 1443 DRM_ERROR("Cannot get HDMI irq\n"); 1444 ret = hdmi->irq; 1445 goto release_adapter; 1446 } 1447 1448 ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq, 1449 hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi); 1450 if (ret) { 1451 DRM_ERROR("Failed to register HDMI interrupt\n"); 1452 goto release_adapter; 1453 } 1454 1455 hdmi->reset = devm_reset_control_get(dev, "hdmi"); 1456 /* Take hdmi out of reset */ 1457 if (!IS_ERR(hdmi->reset)) 1458 reset_control_deassert(hdmi->reset); 1459 1460 platform_set_drvdata(pdev, hdmi); 1461 1462 drm_bridge_add(&hdmi->bridge); 1463 return component_add(&pdev->dev, &sti_hdmi_ops); 1464 1465 release_adapter: 1466 i2c_put_adapter(hdmi->ddc_adapt); 1467 1468 return ret; 1469} 1470 1471static void sti_hdmi_remove(struct platform_device *pdev) 1472{ 1473 struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev); 1474 1475 i2c_put_adapter(hdmi->ddc_adapt); 1476 if (hdmi->audio_pdev) 1477 platform_device_unregister(hdmi->audio_pdev); 1478 component_del(&pdev->dev, &sti_hdmi_ops); 1479 drm_bridge_remove(&hdmi->bridge); 1480} 1481 1482struct platform_driver sti_hdmi_driver = { 1483 .driver = { 1484 .name = "sti-hdmi", 1485 .of_match_table = hdmi_of_match, 1486 }, 1487 .probe = sti_hdmi_probe, 1488 .remove = sti_hdmi_remove, 1489}; 1490 1491MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 1492MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 1493MODULE_LICENSE("GPL");
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