File Index
Files and directories
Sign in
FILE

sti_hda.c

File preview with syntax highlighting.

linux-6.19.14/drivers/gpu/drm/sti/sti_hda.c C 
  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) STMicroelectronics SA 2014
  4 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
  5 */
  6
  7#include <linux/clk.h>
  8#include <linux/component.h>
  9#include <linux/io.h>
 10#include <linux/mod_devicetable.h>
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <linux/seq_file.h>
 14
 15#include <drm/drm_atomic_helper.h>
 16#include <drm/drm_bridge.h>
 17#include <drm/drm_debugfs.h>
 18#include <drm/drm_device.h>
 19#include <drm/drm_file.h>
 20#include <drm/drm_print.h>
 21#include <drm/drm_probe_helper.h>
 22
 23/* HDformatter registers */
 24#define HDA_ANA_CFG                     0x0000
 25#define HDA_ANA_SCALE_CTRL_Y            0x0004
 26#define HDA_ANA_SCALE_CTRL_CB           0x0008
 27#define HDA_ANA_SCALE_CTRL_CR           0x000C
 28#define HDA_ANA_ANC_CTRL                0x0010
 29#define HDA_ANA_SRC_Y_CFG               0x0014
 30#define HDA_COEFF_Y_PH1_TAP123          0x0018
 31#define HDA_COEFF_Y_PH1_TAP456          0x001C
 32#define HDA_COEFF_Y_PH2_TAP123          0x0020
 33#define HDA_COEFF_Y_PH2_TAP456          0x0024
 34#define HDA_COEFF_Y_PH3_TAP123          0x0028
 35#define HDA_COEFF_Y_PH3_TAP456          0x002C
 36#define HDA_COEFF_Y_PH4_TAP123          0x0030
 37#define HDA_COEFF_Y_PH4_TAP456          0x0034
 38#define HDA_ANA_SRC_C_CFG               0x0040
 39#define HDA_COEFF_C_PH1_TAP123          0x0044
 40#define HDA_COEFF_C_PH1_TAP456          0x0048
 41#define HDA_COEFF_C_PH2_TAP123          0x004C
 42#define HDA_COEFF_C_PH2_TAP456          0x0050
 43#define HDA_COEFF_C_PH3_TAP123          0x0054
 44#define HDA_COEFF_C_PH3_TAP456          0x0058
 45#define HDA_COEFF_C_PH4_TAP123          0x005C
 46#define HDA_COEFF_C_PH4_TAP456          0x0060
 47#define HDA_SYNC_AWGI                   0x0300
 48
 49/* HDA_ANA_CFG */
 50#define CFG_AWG_ASYNC_EN                BIT(0)
 51#define CFG_AWG_ASYNC_HSYNC_MTD         BIT(1)
 52#define CFG_AWG_ASYNC_VSYNC_MTD         BIT(2)
 53#define CFG_AWG_SYNC_DEL                BIT(3)
 54#define CFG_AWG_FLTR_MODE_SHIFT         4
 55#define CFG_AWG_FLTR_MODE_MASK          (0xF << CFG_AWG_FLTR_MODE_SHIFT)
 56#define CFG_AWG_FLTR_MODE_SD            (0 << CFG_AWG_FLTR_MODE_SHIFT)
 57#define CFG_AWG_FLTR_MODE_ED            (1 << CFG_AWG_FLTR_MODE_SHIFT)
 58#define CFG_AWG_FLTR_MODE_HD            (2 << CFG_AWG_FLTR_MODE_SHIFT)
 59#define CFG_SYNC_ON_PBPR_MASK           BIT(8)
 60#define CFG_PREFILTER_EN_MASK           BIT(9)
 61#define CFG_PBPR_SYNC_OFF_SHIFT         16
 62#define CFG_PBPR_SYNC_OFF_MASK          (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
 63#define CFG_PBPR_SYNC_OFF_VAL           0x117 /* Voltage dependent. stiH416 */
 64
 65/* Default scaling values */
 66#define SCALE_CTRL_Y_DFLT               0x00C50256
 67#define SCALE_CTRL_CB_DFLT              0x00DB0249
 68#define SCALE_CTRL_CR_DFLT              0x00DB0249
 69
 70/* Video DACs control */
 71#define DAC_CFG_HD_HZUVW_OFF_MASK       BIT(1)
 72
 73/* Upsampler values for the alternative 2X Filter */
 74#define SAMPLER_COEF_NB                 8
 75#define HDA_ANA_SRC_Y_CFG_ALT_2X        0x01130000
 76static u32 coef_y_alt_2x[] = {
 77	0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
 78	0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
 79};
 80
 81#define HDA_ANA_SRC_C_CFG_ALT_2X        0x01750004
 82static u32 coef_c_alt_2x[] = {
 83	0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
 84	0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
 85};
 86
 87/* Upsampler values for the 4X Filter */
 88#define HDA_ANA_SRC_Y_CFG_4X            0x01ED0005
 89#define HDA_ANA_SRC_C_CFG_4X            0x01ED0004
 90static u32 coef_yc_4x[] = {
 91	0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
 92	0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
 93};
 94
 95/* AWG instructions for some video modes */
 96#define AWG_MAX_INST                    64
 97
 98/* 720p@50 */
 99static u32 AWGi_720p_50[] = {
100	0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
101	0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
102	0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
103	0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
104	0x00000104, 0x00001AE8
105};
106
107#define NN_720p_50 ARRAY_SIZE(AWGi_720p_50)
108
109/* 720p@60 */
110static u32 AWGi_720p_60[] = {
111	0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
112	0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
113	0x00000C44, 0x00000104, 0x00001804, 0x00000971,
114	0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
115	0x00000104, 0x00001AE8
116};
117
118#define NN_720p_60 ARRAY_SIZE(AWGi_720p_60)
119
120/* 1080p@30 */
121static u32 AWGi_1080p_30[] = {
122	0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
123	0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
124	0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
125	0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
126	0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
127	0x00001C52
128};
129
130#define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30)
131
132/* 1080p@25 */
133static u32 AWGi_1080p_25[] = {
134	0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
135	0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
136	0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
137	0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
138	0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
139	0x00001C52
140};
141
142#define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25)
143
144/* 1080p@24 */
145static u32 AWGi_1080p_24[] = {
146	0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
147	0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
148	0x00000E50, 0x00000104, 0x00001804, 0x00000971,
149	0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
150	0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
151	0x00001C52
152};
153
154#define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24)
155
156/* 720x480p@60 */
157static u32 AWGi_720x480p_60[] = {
158	0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
159	0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
160};
161
162#define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60)
163
164/* Video mode category */
165enum sti_hda_vid_cat {
166	VID_SD,
167	VID_ED,
168	VID_HD_74M,
169	VID_HD_148M
170};
171
172struct sti_hda_video_config {
173	struct drm_display_mode mode;
174	u32 *awg_instr;
175	int nb_instr;
176	enum sti_hda_vid_cat vid_cat;
177};
178
179/* HD analog supported modes
180 * Interlaced modes may be added when supported by the whole display chain
181 */
182static const struct sti_hda_video_config hda_supported_modes[] = {
183	/* 1080p30 74.250Mhz */
184	{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
185		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
186		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
187	 AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
188	/* 1080p30 74.176Mhz */
189	{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008,
190		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
191		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
192	 AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
193	/* 1080p24 74.250Mhz */
194	{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
195		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
196		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
197	 AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
198	/* 1080p24 74.176Mhz */
199	{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558,
200		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
201		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
202	 AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
203	/* 1080p25 74.250Mhz */
204	{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
205		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
206		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
207	 AWGi_1080p_25, NN_1080p_25, VID_HD_74M},
208	/* 720p60 74.250Mhz */
209	{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
210		   1430, 1650, 0, 720, 725, 730, 750, 0,
211		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
212	 AWGi_720p_60, NN_720p_60, VID_HD_74M},
213	/* 720p60 74.176Mhz */
214	{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
215		   1430, 1650, 0, 720, 725, 730, 750, 0,
216		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
217	 AWGi_720p_60, NN_720p_60, VID_HD_74M},
218	/* 720p50 74.250Mhz */
219	{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
220		   1760, 1980, 0, 720, 725, 730, 750, 0,
221		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
222	 AWGi_720p_50, NN_720p_50, VID_HD_74M},
223	/* 720x480p60 27.027Mhz */
224	{{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736,
225		   798, 858, 0, 480, 489, 495, 525, 0,
226		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
227	 AWGi_720x480p_60, NN_720x480p_60, VID_ED},
228	/* 720x480p60 27.000Mhz */
229	{{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
230		   798, 858, 0, 480, 489, 495, 525, 0,
231		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
232	 AWGi_720x480p_60, NN_720x480p_60, VID_ED}
233};
234
235/*
236 * STI hd analog structure
237 *
238 * @dev: driver device
239 * @drm_dev: pointer to drm device
240 * @mode: current display mode selected
241 * @regs: HD analog register
242 * @video_dacs_ctrl: video DACS control register
243 * @enabled: true if HD analog is enabled else false
244 */
245struct sti_hda {
246	struct device dev;
247	struct drm_device *drm_dev;
248	struct drm_display_mode mode;
249	struct drm_bridge bridge;
250	void __iomem *regs;
251	void __iomem *video_dacs_ctrl;
252	struct clk *clk_pix;
253	struct clk *clk_hddac;
254	bool enabled;
255};
256
257struct sti_hda_connector {
258	struct drm_connector drm_connector;
259	struct drm_encoder *encoder;
260	struct sti_hda *hda;
261};
262
263#define to_sti_hda_connector(x) \
264	container_of(x, struct sti_hda_connector, drm_connector)
265
266static struct sti_hda *drm_bridge_to_sti_hda(struct drm_bridge *bridge)
267{
268	return container_of(bridge, struct sti_hda, bridge);
269}
270
271static u32 hda_read(struct sti_hda *hda, int offset)
272{
273	return readl(hda->regs + offset);
274}
275
276static void hda_write(struct sti_hda *hda, u32 val, int offset)
277{
278	writel(val, hda->regs + offset);
279}
280
281/**
282 * hda_get_mode_idx - Search for a video mode in the supported modes table
283 *
284 * @mode: mode being searched
285 * @idx: index of the found mode
286 *
287 * Return true if mode is found
288 */
289static bool hda_get_mode_idx(const struct drm_display_mode *mode, int *idx)
290{
291	unsigned int i;
292
293	for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++)
294		if (drm_mode_equal(&hda_supported_modes[i].mode, mode)) {
295			*idx = i;
296			return true;
297		}
298	return false;
299}
300
301/**
302 * hda_enable_hd_dacs - Enable the HD DACS
303 *
304 * @hda: pointer to HD analog structure
305 * @enable: true if HD DACS need to be enabled, else false
306 */
307static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
308{
309	if (hda->video_dacs_ctrl) {
310		u32 val;
311
312		val = readl(hda->video_dacs_ctrl);
313		if (enable)
314			val &= ~DAC_CFG_HD_HZUVW_OFF_MASK;
315		else
316			val |= DAC_CFG_HD_HZUVW_OFF_MASK;
317
318		writel(val, hda->video_dacs_ctrl);
319	}
320}
321
322#define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
323				   readl(hda->regs + reg))
324
325static void hda_dbg_cfg(struct seq_file *s, int val)
326{
327	seq_puts(s, "\tAWG ");
328	seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled");
329}
330
331static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
332{
333	unsigned int i;
334
335	seq_puts(s, "\n\n  HDA AWG microcode:");
336	for (i = 0; i < AWG_MAX_INST; i++) {
337		if (i % 8 == 0)
338			seq_printf(s, "\n  %04X:", i);
339		seq_printf(s, " %04X", readl(reg + i * 4));
340	}
341}
342
343static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
344{
345	u32 val = readl(reg);
346
347	seq_printf(s, "\n\n  %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
348	seq_puts(s, "\tHD DACs ");
349	seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled");
350}
351
352static int hda_dbg_show(struct seq_file *s, void *data)
353{
354	struct drm_info_node *node = s->private;
355	struct sti_hda *hda = (struct sti_hda *)node->info_ent->data;
356
357	seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs);
358	DBGFS_DUMP(HDA_ANA_CFG);
359	hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG));
360	DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y);
361	DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB);
362	DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR);
363	DBGFS_DUMP(HDA_ANA_ANC_CTRL);
364	DBGFS_DUMP(HDA_ANA_SRC_Y_CFG);
365	DBGFS_DUMP(HDA_ANA_SRC_C_CFG);
366	hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI);
367	if (hda->video_dacs_ctrl)
368		hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl);
369	seq_putc(s, '\n');
370	return 0;
371}
372
373static struct drm_info_list hda_debugfs_files[] = {
374	{ "hda", hda_dbg_show, 0, NULL },
375};
376
377static void hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor)
378{
379	unsigned int i;
380
381	for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++)
382		hda_debugfs_files[i].data = hda;
383
384	drm_debugfs_create_files(hda_debugfs_files,
385				 ARRAY_SIZE(hda_debugfs_files),
386				 minor->debugfs_root, minor);
387}
388
389/**
390 * sti_hda_configure_awg - Configure AWG, writing instructions
391 *
392 * @hda: pointer to HD analog structure
393 * @awg_instr: pointer to AWG instructions table
394 * @nb: nb of AWG instructions
395 */
396static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb)
397{
398	unsigned int i;
399
400	DRM_DEBUG_DRIVER("\n");
401
402	for (i = 0; i < nb; i++)
403		hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4);
404	for (i = nb; i < AWG_MAX_INST; i++)
405		hda_write(hda, 0, HDA_SYNC_AWGI + i * 4);
406}
407
408static void sti_hda_disable(struct drm_bridge *bridge)
409{
410	struct sti_hda *hda = drm_bridge_to_sti_hda(bridge);
411	u32 val;
412
413	if (!hda->enabled)
414		return;
415
416	DRM_DEBUG_DRIVER("\n");
417
418	/* Disable HD DAC and AWG */
419	val = hda_read(hda, HDA_ANA_CFG);
420	val &= ~CFG_AWG_ASYNC_EN;
421	hda_write(hda, val, HDA_ANA_CFG);
422	hda_write(hda, 0, HDA_ANA_ANC_CTRL);
423
424	hda_enable_hd_dacs(hda, false);
425
426	/* Disable/unprepare hda clock */
427	clk_disable_unprepare(hda->clk_hddac);
428	clk_disable_unprepare(hda->clk_pix);
429
430	hda->enabled = false;
431}
432
433static void sti_hda_pre_enable(struct drm_bridge *bridge)
434{
435	struct sti_hda *hda = drm_bridge_to_sti_hda(bridge);
436	u32 val, i, mode_idx;
437	u32 src_filter_y, src_filter_c;
438	u32 *coef_y, *coef_c;
439	u32 filter_mode;
440
441	DRM_DEBUG_DRIVER("\n");
442
443	if (hda->enabled)
444		return;
445
446	/* Prepare/enable clocks */
447	if (clk_prepare_enable(hda->clk_pix))
448		DRM_ERROR("Failed to prepare/enable hda_pix clk\n");
449	if (clk_prepare_enable(hda->clk_hddac))
450		DRM_ERROR("Failed to prepare/enable hda_hddac clk\n");
451
452	if (!hda_get_mode_idx(&hda->mode, &mode_idx)) {
453		DRM_ERROR("Undefined mode\n");
454		return;
455	}
456
457	switch (hda_supported_modes[mode_idx].vid_cat) {
458	case VID_HD_148M:
459		DRM_ERROR("Beyond HD analog capabilities\n");
460		return;
461	case VID_HD_74M:
462		/* HD use alternate 2x filter */
463		filter_mode = CFG_AWG_FLTR_MODE_HD;
464		src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X;
465		src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X;
466		coef_y = coef_y_alt_2x;
467		coef_c = coef_c_alt_2x;
468		break;
469	case VID_ED:
470		/* ED uses 4x filter */
471		filter_mode = CFG_AWG_FLTR_MODE_ED;
472		src_filter_y = HDA_ANA_SRC_Y_CFG_4X;
473		src_filter_c = HDA_ANA_SRC_C_CFG_4X;
474		coef_y = coef_yc_4x;
475		coef_c = coef_yc_4x;
476		break;
477	case VID_SD:
478		DRM_ERROR("Not supported\n");
479		return;
480	default:
481		DRM_ERROR("Undefined resolution\n");
482		return;
483	}
484	DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx);
485
486	/* Enable HD Video DACs */
487	hda_enable_hd_dacs(hda, true);
488
489	/* Configure scaler */
490	hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y);
491	hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB);
492	hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR);
493
494	/* Configure sampler */
495	hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG);
496	hda_write(hda, src_filter_c,  HDA_ANA_SRC_C_CFG);
497	for (i = 0; i < SAMPLER_COEF_NB; i++) {
498		hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4);
499		hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4);
500	}
501
502	/* Configure main HDFormatter */
503	val = 0;
504	val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ?
505	    0 : CFG_AWG_ASYNC_VSYNC_MTD;
506	val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT);
507	val |= filter_mode;
508	hda_write(hda, val, HDA_ANA_CFG);
509
510	/* Configure AWG */
511	sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr,
512			      hda_supported_modes[mode_idx].nb_instr);
513
514	/* Enable AWG */
515	val = hda_read(hda, HDA_ANA_CFG);
516	val |= CFG_AWG_ASYNC_EN;
517	hda_write(hda, val, HDA_ANA_CFG);
518
519	hda->enabled = true;
520}
521
522static void sti_hda_set_mode(struct drm_bridge *bridge,
523			     const struct drm_display_mode *mode,
524			     const struct drm_display_mode *adjusted_mode)
525{
526	struct sti_hda *hda = drm_bridge_to_sti_hda(bridge);
527	u32 mode_idx;
528	int hddac_rate;
529	int ret;
530
531	DRM_DEBUG_DRIVER("\n");
532
533	drm_mode_copy(&hda->mode, mode);
534
535	if (!hda_get_mode_idx(&hda->mode, &mode_idx)) {
536		DRM_ERROR("Undefined mode\n");
537		return;
538	}
539
540	switch (hda_supported_modes[mode_idx].vid_cat) {
541	case VID_HD_74M:
542		/* HD use alternate 2x filter */
543		hddac_rate = mode->clock * 1000 * 2;
544		break;
545	case VID_ED:
546		/* ED uses 4x filter */
547		hddac_rate = mode->clock * 1000 * 4;
548		break;
549	default:
550		DRM_ERROR("Undefined mode\n");
551		return;
552	}
553
554	/* HD DAC = 148.5Mhz or 108 Mhz */
555	ret = clk_set_rate(hda->clk_hddac, hddac_rate);
556	if (ret < 0)
557		DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n",
558			  hddac_rate);
559
560	/* HDformatter clock = compositor clock */
561	ret = clk_set_rate(hda->clk_pix, mode->clock * 1000);
562	if (ret < 0)
563		DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n",
564			  mode->clock * 1000);
565}
566
567static void sti_hda_bridge_nope(struct drm_bridge *bridge)
568{
569	/* do nothing */
570}
571
572static const struct drm_bridge_funcs sti_hda_bridge_funcs = {
573	.pre_enable = sti_hda_pre_enable,
574	.enable = sti_hda_bridge_nope,
575	.disable = sti_hda_disable,
576	.post_disable = sti_hda_bridge_nope,
577	.mode_set = sti_hda_set_mode,
578};
579
580static int sti_hda_connector_get_modes(struct drm_connector *connector)
581{
582	unsigned int i;
583	int count = 0;
584	struct sti_hda_connector *hda_connector
585		= to_sti_hda_connector(connector);
586	struct sti_hda *hda = hda_connector->hda;
587
588	DRM_DEBUG_DRIVER("\n");
589
590	for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) {
591		struct drm_display_mode *mode =
592			drm_mode_duplicate(hda->drm_dev,
593					&hda_supported_modes[i].mode);
594		if (!mode)
595			continue;
596
597		/* the first mode is the preferred mode */
598		if (i == 0)
599			mode->type |= DRM_MODE_TYPE_PREFERRED;
600
601		drm_mode_probed_add(connector, mode);
602		count++;
603	}
604
605	return count;
606}
607
608#define CLK_TOLERANCE_HZ 50
609
610static enum drm_mode_status
611sti_hda_connector_mode_valid(struct drm_connector *connector,
612			     const struct drm_display_mode *mode)
613{
614	int target = mode->clock * 1000;
615	int target_min = target - CLK_TOLERANCE_HZ;
616	int target_max = target + CLK_TOLERANCE_HZ;
617	int result;
618	int idx;
619	struct sti_hda_connector *hda_connector
620		= to_sti_hda_connector(connector);
621	struct sti_hda *hda = hda_connector->hda;
622
623	if (!hda_get_mode_idx(mode, &idx)) {
624		return MODE_BAD;
625	} else {
626		result = clk_round_rate(hda->clk_pix, target);
627
628		DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
629				 target, result);
630
631		if ((result < target_min) || (result > target_max)) {
632			DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n",
633					 target);
634			return MODE_BAD;
635		}
636	}
637
638	return MODE_OK;
639}
640
641static const
642struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = {
643	.get_modes = sti_hda_connector_get_modes,
644	.mode_valid = sti_hda_connector_mode_valid,
645};
646
647static int sti_hda_late_register(struct drm_connector *connector)
648{
649	struct sti_hda_connector *hda_connector
650		= to_sti_hda_connector(connector);
651	struct sti_hda *hda = hda_connector->hda;
652
653	hda_debugfs_init(hda, hda->drm_dev->primary);
654
655	return 0;
656}
657
658static const struct drm_connector_funcs sti_hda_connector_funcs = {
659	.fill_modes = drm_helper_probe_single_connector_modes,
660	.destroy = drm_connector_cleanup,
661	.reset = drm_atomic_helper_connector_reset,
662	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
663	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
664	.late_register = sti_hda_late_register,
665};
666
667static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev)
668{
669	struct drm_encoder *encoder;
670
671	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
672		if (encoder->encoder_type == DRM_MODE_ENCODER_DAC)
673			return encoder;
674	}
675
676	return NULL;
677}
678
679static int sti_hda_bind(struct device *dev, struct device *master, void *data)
680{
681	struct sti_hda *hda = dev_get_drvdata(dev);
682	struct drm_device *drm_dev = data;
683	struct drm_encoder *encoder;
684	struct sti_hda_connector *connector;
685	struct drm_connector *drm_connector;
686	int err;
687
688	/* Set the drm device handle */
689	hda->drm_dev = drm_dev;
690
691	encoder = sti_hda_find_encoder(drm_dev);
692	if (!encoder)
693		return -ENOMEM;
694
695	connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
696	if (!connector)
697		return -ENOMEM;
698
699	connector->hda = hda;
700
701	drm_bridge_attach(encoder, &hda->bridge, NULL, 0);
702
703	connector->encoder = encoder;
704
705	drm_connector = (struct drm_connector *)connector;
706
707	drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
708
709	drm_connector_init(drm_dev, drm_connector,
710			&sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component);
711	drm_connector_helper_add(drm_connector,
712			&sti_hda_connector_helper_funcs);
713
714	err = drm_connector_attach_encoder(drm_connector, encoder);
715	if (err) {
716		DRM_ERROR("Failed to attach a connector to a encoder\n");
717		goto err_sysfs;
718	}
719
720	/* force to disable hd dacs at startup */
721	hda_enable_hd_dacs(hda, false);
722
723	return 0;
724
725err_sysfs:
726	return -EINVAL;
727}
728
729static void sti_hda_unbind(struct device *dev,
730		struct device *master, void *data)
731{
732}
733
734static const struct component_ops sti_hda_ops = {
735	.bind = sti_hda_bind,
736	.unbind = sti_hda_unbind,
737};
738
739static int sti_hda_probe(struct platform_device *pdev)
740{
741	struct device *dev = &pdev->dev;
742	struct sti_hda *hda;
743	struct resource *res;
744
745	DRM_INFO("%s\n", __func__);
746
747	hda = devm_drm_bridge_alloc(dev, struct sti_hda, bridge, &sti_hda_bridge_funcs);
748	if (IS_ERR(hda))
749		return PTR_ERR(hda);
750
751	hda->dev = pdev->dev;
752	hda->regs = devm_platform_ioremap_resource_byname(pdev, "hda-reg");
753	if (IS_ERR(hda->regs))
754		return PTR_ERR(hda->regs);
755
756	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
757			"video-dacs-ctrl");
758	if (res) {
759		hda->video_dacs_ctrl = devm_ioremap(dev, res->start,
760				resource_size(res));
761		if (!hda->video_dacs_ctrl)
762			return -ENOMEM;
763	} else {
764		/* If no existing video-dacs-ctrl resource continue the probe */
765		DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n");
766		hda->video_dacs_ctrl = NULL;
767	}
768
769	/* Get clock resources */
770	hda->clk_pix = devm_clk_get(dev, "pix");
771	if (IS_ERR(hda->clk_pix)) {
772		DRM_ERROR("Cannot get hda_pix clock\n");
773		return PTR_ERR(hda->clk_pix);
774	}
775
776	hda->clk_hddac = devm_clk_get(dev, "hddac");
777	if (IS_ERR(hda->clk_hddac)) {
778		DRM_ERROR("Cannot get hda_hddac clock\n");
779		return PTR_ERR(hda->clk_hddac);
780	}
781
782	drm_bridge_add(&hda->bridge);
783
784	platform_set_drvdata(pdev, hda);
785
786	return component_add(&pdev->dev, &sti_hda_ops);
787}
788
789static void sti_hda_remove(struct platform_device *pdev)
790{
791	struct sti_hda *hda = platform_get_drvdata(pdev);
792
793	component_del(&pdev->dev, &sti_hda_ops);
794	drm_bridge_remove(&hda->bridge);
795}
796
797static const struct of_device_id hda_of_match[] = {
798	{ .compatible = "st,stih416-hda", },
799	{ .compatible = "st,stih407-hda", },
800	{ /* end node */ }
801};
802MODULE_DEVICE_TABLE(of, hda_of_match);
803
804struct platform_driver sti_hda_driver = {
805	.driver = {
806		.name = "sti-hda",
807		.of_match_table = hda_of_match,
808	},
809	.probe = sti_hda_probe,
810	.remove = sti_hda_remove,
811};
812
813MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
814MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
815MODULE_LICENSE("GPL");
~/ Read-only file preview.