rockchip_drm_vop2.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) Rockchip Electronics Co., Ltd.
  4 * Author:Mark Yao <mark.yao@rock-chips.com>
  5 */
  6
  7#ifndef _ROCKCHIP_DRM_VOP2_H
  8#define _ROCKCHIP_DRM_VOP2_H
  9
 10#include <linux/regmap.h>
 11#include <drm/drm_modes.h>
 12#include <dt-bindings/soc/rockchip,vop2.h>
 13#include "rockchip_drm_drv.h"
 14#include "rockchip_drm_vop.h"
 15
 16#define VOP2_VERSION(major, minor, build)	((major) << 24 | (minor) << 16 | (build))
 17
 18/* The VOP version of new SoC is bigger than the old */
 19#define VOP_VERSION_RK3568	VOP2_VERSION(0x40, 0x15, 0x8023)
 20#define VOP_VERSION_RK3588	VOP2_VERSION(0x40, 0x17, 0x6786)
 21#define VOP_VERSION_RK3528	VOP2_VERSION(0x50, 0x17, 0x1263)
 22#define VOP_VERSION_RK3562	VOP2_VERSION(0x50, 0x17, 0x4350)
 23#define VOP_VERSION_RK3576	VOP2_VERSION(0x50, 0x19, 0x9765)
 24
 25#define VOP2_VP_FEATURE_OUTPUT_10BIT        BIT(0)
 26
 27#define VOP2_FEATURE_HAS_SYS_GRF	BIT(0)
 28#define VOP2_FEATURE_HAS_VO0_GRF	BIT(1)
 29#define VOP2_FEATURE_HAS_VO1_GRF	BIT(2)
 30#define VOP2_FEATURE_HAS_VOP_GRF	BIT(3)
 31#define VOP2_FEATURE_HAS_SYS_PMU	BIT(4)
 32
 33#define WIN_FEATURE_AFBDC		BIT(0)
 34#define WIN_FEATURE_CLUSTER		BIT(1)
 35
 36/*
 37 *  the delay number of a window in different mode.
 38 */
 39enum win_dly_mode {
 40	VOP2_DLY_MODE_DEFAULT,   /**< default mode */
 41	VOP2_DLY_MODE_HISO_S,    /** HDR in SDR out mode, as a SDR window */
 42	VOP2_DLY_MODE_HIHO_H,    /** HDR in HDR out mode, as a HDR window */
 43	VOP2_DLY_MODE_MAX,
 44};
 45
 46enum vop2_dly_module {
 47	VOP2_DLY_WIN,           /** Win delay cycle for this VP */
 48	VOP2_DLY_LAYER_MIX,     /** Layer Mix delay cycle for this VP */
 49	VOP2_DLY_HDR_MIX,       /** HDR delay cycle for this VP */
 50	VOP2_DLY_MAX,
 51};
 52
 53enum vop2_scale_up_mode {
 54	VOP2_SCALE_UP_NRST_NBOR,
 55	VOP2_SCALE_UP_BIL,
 56	VOP2_SCALE_UP_BIC,
 57};
 58
 59enum vop2_scale_down_mode {
 60	VOP2_SCALE_DOWN_NRST_NBOR,
 61	VOP2_SCALE_DOWN_BIL,
 62	VOP2_SCALE_DOWN_AVG,
 63};
 64
 65/*
 66 * vop2 internal power domain id,
 67 * should be all none zero, 0 will be treat as invalid;
 68 */
 69#define VOP2_PD_CLUSTER0	BIT(0)
 70#define VOP2_PD_CLUSTER1	BIT(1)
 71#define VOP2_PD_CLUSTER2	BIT(2)
 72#define VOP2_PD_CLUSTER3	BIT(3)
 73#define VOP2_PD_DSC_8K		BIT(5)
 74#define VOP2_PD_DSC_4K		BIT(6)
 75#define VOP2_PD_ESMART		BIT(7)
 76
 77#define vop2_output_if_is_hdmi(x)	((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
 78					 (x) == ROCKCHIP_VOP2_EP_HDMI1)
 79
 80#define vop2_output_if_is_dp(x)		((x) == ROCKCHIP_VOP2_EP_DP0 || \
 81					 (x) == ROCKCHIP_VOP2_EP_DP1)
 82
 83#define vop2_output_if_is_edp(x)	((x) == ROCKCHIP_VOP2_EP_EDP0 || \
 84					 (x) == ROCKCHIP_VOP2_EP_EDP1)
 85
 86#define vop2_output_if_is_mipi(x)	((x) == ROCKCHIP_VOP2_EP_MIPI0 || \
 87					 (x) == ROCKCHIP_VOP2_EP_MIPI1)
 88
 89#define vop2_output_if_is_lvds(x)	((x) == ROCKCHIP_VOP2_EP_LVDS0 || \
 90					 (x) == ROCKCHIP_VOP2_EP_LVDS1)
 91
 92#define vop2_output_if_is_dpi(x)	((x) == ROCKCHIP_VOP2_EP_RGB0)
 93
 94enum vop2_win_regs {
 95	VOP2_WIN_ENABLE,
 96	VOP2_WIN_FORMAT,
 97	VOP2_WIN_CSC_MODE,
 98	VOP2_WIN_XMIRROR,
 99	VOP2_WIN_YMIRROR,
100	VOP2_WIN_RB_SWAP,
101	VOP2_WIN_UV_SWAP,
102	VOP2_WIN_ACT_INFO,
103	VOP2_WIN_DSP_INFO,
104	VOP2_WIN_DSP_ST,
105	VOP2_WIN_YRGB_MST,
106	VOP2_WIN_UV_MST,
107	VOP2_WIN_YRGB_VIR,
108	VOP2_WIN_UV_VIR,
109	VOP2_WIN_YUV_CLIP,
110	VOP2_WIN_Y2R_EN,
111	VOP2_WIN_R2Y_EN,
112	VOP2_WIN_COLOR_KEY,
113	VOP2_WIN_COLOR_KEY_EN,
114	VOP2_WIN_DITHER_UP,
115	VOP2_WIN_AXI_BUS_ID,
116	VOP2_WIN_AXI_YRGB_R_ID,
117	VOP2_WIN_AXI_UV_R_ID,
118
119	/* scale regs */
120	VOP2_WIN_SCALE_YRGB_X,
121	VOP2_WIN_SCALE_YRGB_Y,
122	VOP2_WIN_SCALE_CBCR_X,
123	VOP2_WIN_SCALE_CBCR_Y,
124	VOP2_WIN_YRGB_HOR_SCL_MODE,
125	VOP2_WIN_YRGB_HSCL_FILTER_MODE,
126	VOP2_WIN_YRGB_VER_SCL_MODE,
127	VOP2_WIN_YRGB_VSCL_FILTER_MODE,
128	VOP2_WIN_CBCR_VER_SCL_MODE,
129	VOP2_WIN_CBCR_HSCL_FILTER_MODE,
130	VOP2_WIN_CBCR_HOR_SCL_MODE,
131	VOP2_WIN_CBCR_VSCL_FILTER_MODE,
132	VOP2_WIN_VSD_CBCR_GT2,
133	VOP2_WIN_VSD_CBCR_GT4,
134	VOP2_WIN_VSD_YRGB_GT2,
135	VOP2_WIN_VSD_YRGB_GT4,
136	VOP2_WIN_BIC_COE_SEL,
137
138	/* cluster regs */
139	VOP2_WIN_CLUSTER_ENABLE,
140	VOP2_WIN_AFBC_ENABLE,
141	VOP2_WIN_CLUSTER_LB_MODE,
142
143	/* afbc regs */
144	VOP2_WIN_AFBC_FORMAT,
145	VOP2_WIN_AFBC_RB_SWAP,
146	VOP2_WIN_AFBC_UV_SWAP,
147	VOP2_WIN_AFBC_AUTO_GATING_EN,
148	VOP2_WIN_AFBC_BLOCK_SPLIT_EN,
149	VOP2_WIN_AFBC_PLD_OFFSET_EN,
150	VOP2_WIN_AFBC_PIC_VIR_WIDTH,
151	VOP2_WIN_AFBC_TILE_NUM,
152	VOP2_WIN_AFBC_PIC_OFFSET,
153	VOP2_WIN_AFBC_PIC_SIZE,
154	VOP2_WIN_AFBC_DSP_OFFSET,
155	VOP2_WIN_AFBC_PLD_OFFSET,
156	VOP2_WIN_TRANSFORM_OFFSET,
157	VOP2_WIN_AFBC_HDR_PTR,
158	VOP2_WIN_AFBC_HALF_BLOCK_EN,
159	VOP2_WIN_AFBC_ROTATE_270,
160	VOP2_WIN_AFBC_ROTATE_90,
161
162	VOP2_WIN_VP_SEL,
163	VOP2_WIN_DLY_NUM,
164
165	VOP2_WIN_MAX_REG,
166};
167
168struct vop2_regs_dump {
169	const char *name;
170	u32 base;
171	u32 size;
172	u32 en_reg;
173	u32 en_val;
174	u32 en_mask;
175};
176
177struct vop2_win_data {
178	const char *name;
179	unsigned int phys_id;
180
181	u32 base;
182	u32 possible_vp_mask;
183	enum drm_plane_type type;
184
185	u32 nformats;
186	const u32 *formats;
187	const uint64_t *format_modifiers;
188	const unsigned int supported_rotations;
189
190	/**
191	 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL or PORTn_LAYER_SEL
192	 */
193	unsigned int layer_sel_id[ROCKCHIP_MAX_CRTC];
194	uint64_t feature;
195
196	uint8_t axi_bus_id;
197	uint8_t axi_yrgb_r_id;
198	uint8_t axi_uv_r_id;
199
200	unsigned int max_upscale_factor;
201	unsigned int max_downscale_factor;
202	const u8 dly[VOP2_DLY_MODE_MAX];
203};
204
205struct vop2_win {
206	struct vop2 *vop2;
207	struct drm_plane base;
208	const struct vop2_win_data *data;
209	struct regmap_field *reg[VOP2_WIN_MAX_REG];
210
211	/**
212	 * @win_id: graphic window id, a cluster may be split into two
213	 * graphics windows.
214	 */
215	u8 win_id;
216	u8 delay;
217	u32 offset;
218
219	enum drm_plane_type type;
220};
221
222struct vop2_video_port_data {
223	unsigned int id;
224	u32 feature;
225	u16 gamma_lut_len;
226	u16 cubic_lut_len;
227	struct vop_rect max_output;
228	const u8 pre_scan_max_dly[4];
229	unsigned int offset;
230	/**
231	 * @pixel_rate: pixel per cycle
232	 */
233	u8 pixel_rate;
234};
235
236struct vop2_video_port {
237	struct drm_crtc crtc;
238	struct vop2 *vop2;
239	struct clk *dclk;
240	struct clk *dclk_src;
241	unsigned int id;
242	const struct vop2_video_port_data *data;
243
244	struct completion dsp_hold_completion;
245
246	/**
247	 * @win_mask: Bitmask of windows attached to the video port;
248	 */
249	u32 win_mask;
250
251	struct vop2_win *primary_plane;
252	struct drm_pending_vblank_event *event;
253
254	unsigned int nlayers;
255};
256
257/**
258 * struct vop2_ops - helper operations for vop2 hardware
259 *
260 * These hooks are used by the common part of the vop2 driver to
261 * implement the proper behaviour of different variants.
262 */
263struct vop2_ops {
264	unsigned long (*setup_intf_mux)(struct vop2_video_port *vp, int ep_id, u32 polflags);
265	void (*setup_bg_dly)(struct vop2_video_port *vp);
266	void (*setup_overlay)(struct vop2_video_port *vp);
267};
268
269struct vop2_data {
270	u8 nr_vps;
271	u64 feature;
272	u32 version;
273	const struct vop2_ops *ops;
274	const struct vop2_win_data *win;
275	const struct vop2_video_port_data *vp;
276	const struct reg_field *cluster_reg;
277	const struct reg_field *smart_reg;
278	const struct vop2_regs_dump *regs_dump;
279	struct vop_rect max_input;
280	struct vop_rect max_output;
281
282	unsigned int nr_cluster_regs;
283	unsigned int nr_smart_regs;
284	unsigned int win_size;
285	unsigned int regs_dump_size;
286	unsigned int soc_id;
287};
288
289struct vop2 {
290	u32 version;
291	struct device *dev;
292	struct drm_device *drm;
293	struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
294
295	const struct vop2_data *data;
296	const struct vop2_ops *ops;
297	/*
298	 * Number of windows that are registered as plane, may be less than the
299	 * total number of hardware windows.
300	 */
301	u32 registered_num_wins;
302
303	struct resource *res;
304	void __iomem *regs;
305	struct regmap *map;
306
307	struct regmap *sys_grf;
308	struct regmap *vop_grf;
309	struct regmap *vo1_grf;
310	struct regmap *sys_pmu;
311
312	/* physical map length of vop2 register */
313	u32 len;
314
315	void __iomem *lut_regs;
316
317	/* protects crtc enable/disable */
318	struct mutex vop2_lock;
319
320	int irq;
321
322	/*
323	 * Some global resources are shared between all video ports(crtcs), so
324	 * we need a ref counter here.
325	 */
326	unsigned int enable_count;
327	struct clk *hclk;
328	struct clk *aclk;
329	struct clk *pclk;
330	struct clk *pll_hdmiphy0;
331	struct clk *pll_hdmiphy1;
332
333	/* optional internal rgb encoder */
334	struct rockchip_rgb *rgb;
335
336	/*
337	 * Used to record layer selection configuration on rk356x/rk3588
338	 * as register RK3568_OVL_LAYER_SEL and RK3568_OVL_PORT_SEL are
339	 * shared for all the Video Ports.
340	 */
341	u32 old_layer_sel;
342	u32 old_port_sel;
343	/*
344	 * Ensure that the updates to these two registers(RKK3568_OVL_LAYER_SEL/RK3568_OVL_PORT_SEL)
345	 * take effect in sequence.
346	 */
347	struct mutex ovl_lock;
348
349	/* must be put at the end of the struct */
350	struct vop2_win win[];
351};
352
353/* interrupt define */
354#define FS_NEW_INTR			BIT(4)
355#define ADDR_SAME_INTR			BIT(5)
356#define LINE_FLAG1_INTR			BIT(6)
357#define WIN0_EMPTY_INTR			BIT(7)
358#define WIN1_EMPTY_INTR			BIT(8)
359#define WIN2_EMPTY_INTR			BIT(9)
360#define WIN3_EMPTY_INTR			BIT(10)
361#define HWC_EMPTY_INTR			BIT(11)
362#define POST_BUF_EMPTY_INTR		BIT(12)
363#define PWM_GEN_INTR			BIT(13)
364#define DMA_FINISH_INTR			BIT(14)
365#define FS_FIELD_INTR			BIT(15)
366#define FE_INTR				BIT(16)
367#define WB_UV_FIFO_FULL_INTR		BIT(17)
368#define WB_YRGB_FIFO_FULL_INTR		BIT(18)
369#define WB_COMPLETE_INTR		BIT(19)
370
371
372enum vop_csc_format {
373	CSC_BT601L,
374	CSC_BT709L,
375	CSC_BT601F,
376	CSC_BT2020,
377};
378
379enum src_factor_mode {
380	SRC_FAC_ALPHA_ZERO,
381	SRC_FAC_ALPHA_ONE,
382	SRC_FAC_ALPHA_DST,
383	SRC_FAC_ALPHA_DST_INVERSE,
384	SRC_FAC_ALPHA_SRC,
385	SRC_FAC_ALPHA_SRC_GLOBAL,
386};
387
388enum dst_factor_mode {
389	DST_FAC_ALPHA_ZERO,
390	DST_FAC_ALPHA_ONE,
391	DST_FAC_ALPHA_SRC,
392	DST_FAC_ALPHA_SRC_INVERSE,
393	DST_FAC_ALPHA_DST,
394	DST_FAC_ALPHA_DST_GLOBAL,
395};
396
397#define RK3568_GRF_VO_CON1			0x0364
398
399#define RK3588_GRF_SOC_CON1			0x0304
400#define RK3588_GRF_VOP_CON2			0x08
401#define RK3588_GRF_VO1_CON0			0x00
402
403/* System registers definition */
404#define RK3568_REG_CFG_DONE			0x000
405#define RK3568_VERSION_INFO			0x004
406#define RK3568_SYS_AUTO_GATING_CTRL		0x008
407#define RK3576_SYS_MMU_CTRL_IMD			0x020
408#define RK3568_SYS_AXI_LUT_CTRL			0x024
409#define RK3568_DSP_IF_EN			0x028
410#define RK3576_SYS_PORT_CTRL_IMD		0x028
411#define RK3568_DSP_IF_CTRL			0x02c
412#define RK3568_DSP_IF_POL			0x030
413#define RK3576_SYS_CLUSTER_PD_CTRL_IMD		0x030
414#define RK3588_SYS_PD_CTRL			0x034
415#define RK3568_WB_CTRL				0x40
416#define RK3568_WB_XSCAL_FACTOR			0x44
417#define RK3568_WB_YRGB_MST			0x48
418#define RK3568_WB_CBR_MST			0x4C
419#define RK3568_OTP_WIN_EN			0x050
420#define RK3568_LUT_PORT_SEL			0x058
421#define RK3568_SYS_STATUS0			0x060
422#define RK3568_VP_LINE_FLAG(vp)			(0x70 + (vp) * 0x4)
423#define RK3568_SYS0_INT_EN			0x80
424#define RK3568_SYS0_INT_CLR			0x84
425#define RK3568_SYS0_INT_STATUS			0x88
426#define RK3568_SYS1_INT_EN			0x90
427#define RK3568_SYS1_INT_CLR			0x94
428#define RK3568_SYS1_INT_STATUS			0x98
429#define RK3568_VP_INT_EN(vp)			(0xA0 + (vp) * 0x10)
430#define RK3568_VP_INT_CLR(vp)			(0xA4 + (vp) * 0x10)
431#define RK3568_VP_INT_STATUS(vp)		(0xA8 + (vp) * 0x10)
432#define RK3568_VP_INT_RAW_STATUS(vp)		(0xAC + (vp) * 0x10)
433#define RK3576_WB_CTRL				0x100
434#define RK3576_WB_XSCAL_FACTOR			0x104
435#define RK3576_WB_YRGB_MST			0x108
436#define RK3576_WB_CBR_MST			0x10C
437#define RK3576_WB_VIR_STRIDE			0x110
438#define RK3576_WB_TIMEOUT_CTRL			0x114
439#define RK3576_MIPI0_IF_CTRL			0x180
440#define RK3576_HDMI0_IF_CTRL			0x184
441#define RK3576_EDP0_IF_CTRL			0x188
442#define RK3576_DP0_IF_CTRL			0x18C
443#define RK3576_RGB_IF_CTRL			0x194
444#define RK3576_DP1_IF_CTRL			0x1A4
445#define RK3576_DP2_IF_CTRL			0x1B0
446
447/* Extra OVL register definition */
448#define RK3576_SYS_EXTRA_ALPHA_CTRL		0x500
449#define RK3576_CLUSTER0_MIX_SRC_COLOR_CTRL	0x530
450#define RK3576_CLUSTER0_MIX_DST_COLOR_CTRL	0x534
451#define RK3576_CLUSTER0_MIX_SRC_ALPHA_CTRL	0x538
452#define RK3576_CLUSTER0_MIX_DST_ALPHA_CTRL	0x53c
453#define RK3576_CLUSTER1_MIX_SRC_COLOR_CTRL	0x540
454#define RK3576_CLUSTER1_MIX_DST_COLOR_CTRL	0x544
455#define RK3576_CLUSTER1_MIX_SRC_ALPHA_CTRL	0x548
456#define RK3576_CLUSTER1_MIX_DST_ALPHA_CTRL	0x54c
457
458/* OVL registers for Video Port definition */
459#define RK3576_OVL_CTRL(vp)			(0x600 + (vp) * 0x100)
460#define RK3576_OVL_LAYER_SEL(vp)		(0x604 + (vp) * 0x100)
461#define RK3576_OVL_MIX0_SRC_COLOR_CTRL(vp)	(0x620 + (vp) * 0x100)
462#define RK3576_OVL_MIX0_DST_COLOR_CTRL(vp)	(0x624 + (vp) * 0x100)
463#define RK3576_OVL_MIX0_SRC_ALPHA_CTRL(vp)	(0x628 + (vp) * 0x100)
464#define RK3576_OVL_MIX0_DST_ALPHA_CTRL(vp)	(0x62C + (vp) * 0x100)
465#define RK3576_OVL_MIX1_SRC_COLOR_CTRL(vp)	(0x630 + (vp) * 0x100)
466#define RK3576_OVL_MIX1_DST_COLOR_CTRL(vp)	(0x634 + (vp) * 0x100)
467#define RK3576_OVL_MIX1_SRC_ALPHA_CTRL(vp)	(0x638 + (vp) * 0x100)
468#define RK3576_OVL_MIX1_DST_ALPHA_CTRL(vp)	(0x63C + (vp) * 0x100)
469#define RK3576_OVL_MIX2_SRC_COLOR_CTRL(vp)	(0x640 + (vp) * 0x100)
470#define RK3576_OVL_MIX2_DST_COLOR_CTRL(vp)	(0x644 + (vp) * 0x100)
471#define RK3576_OVL_MIX2_SRC_ALPHA_CTRL(vp)	(0x648 + (vp) * 0x100)
472#define RK3576_OVL_MIX2_DST_ALPHA_CTRL(vp)	(0x64C + (vp) * 0x100)
473#define RK3576_EXTRA_OVL_SRC_COLOR_CTRL(vp)	(0x650 + (vp) * 0x100)
474#define RK3576_EXTRA_OVL_DST_COLOR_CTRL(vp)	(0x654 + (vp) * 0x100)
475#define RK3576_EXTRA_OVL_SRC_ALPHA_CTRL(vp)	(0x658 + (vp) * 0x100)
476#define RK3576_EXTRA_OVL_DST_ALPHA_CTRL(vp)	(0x65C + (vp) * 0x100)
477#define RK3576_OVL_HDR_SRC_COLOR_CTRL(vp)	(0x660 + (vp) * 0x100)
478#define RK3576_OVL_HDR_DST_COLOR_CTRL(vp)	(0x664 + (vp) * 0x100)
479#define RK3576_OVL_HDR_SRC_ALPHA_CTRL(vp)	(0x668 + (vp) * 0x100)
480#define RK3576_OVL_HDR_DST_ALPHA_CTRL(vp)	(0x66C + (vp) * 0x100)
481#define RK3576_OVL_BG_MIX_CTRL(vp)		(0x670 + (vp) * 0x100)
482
483/* Video Port registers definition */
484#define RK3568_VP0_CTRL_BASE			0x0C00
485#define RK3568_VP1_CTRL_BASE			0x0D00
486#define RK3568_VP2_CTRL_BASE			0x0E00
487#define RK3588_VP3_CTRL_BASE			0x0F00
488#define RK3568_VP_DSP_CTRL			0x00
489#define RK3568_VP_MIPI_CTRL			0x04
490#define RK3568_VP_COLOR_BAR_CTRL		0x08
491#define RK3588_VP_CLK_CTRL			0x0C
492#define RK3568_VP_3D_LUT_CTRL			0x10
493#define RK3568_VP_3D_LUT_MST			0x20
494#define RK3568_VP_DSP_BG			0x2C
495#define RK3568_VP_PRE_SCAN_HTIMING		0x30
496#define RK3568_VP_POST_DSP_HACT_INFO		0x34
497#define RK3568_VP_POST_DSP_VACT_INFO		0x38
498#define RK3568_VP_POST_SCL_FACTOR_YRGB		0x3C
499#define RK3568_VP_POST_SCL_CTRL			0x40
500#define RK3568_VP_POST_DSP_VACT_INFO_F1		0x44
501#define RK3568_VP_DSP_HTOTAL_HS_END		0x48
502#define RK3568_VP_DSP_HACT_ST_END		0x4C
503#define RK3568_VP_DSP_VTOTAL_VS_END		0x50
504#define RK3568_VP_DSP_VACT_ST_END		0x54
505#define RK3568_VP_DSP_VS_ST_END_F1		0x58
506#define RK3568_VP_DSP_VACT_ST_END_F1		0x5C
507#define RK3568_VP_BCSH_CTRL			0x60
508#define RK3568_VP_BCSH_BCS			0x64
509#define RK3568_VP_BCSH_H			0x68
510#define RK3568_VP_BCSH_COLOR_BAR		0x6C
511
512/* Overlay registers definition    */
513#define RK3568_OVL_CTRL				0x600
514#define RK3568_OVL_LAYER_SEL			0x604
515#define RK3568_OVL_PORT_SEL			0x608
516#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL	0x610
517#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL	0x614
518#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL	0x618
519#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL	0x61C
520#define RK3568_MIX0_SRC_COLOR_CTRL		0x650
521#define RK3568_MIX0_DST_COLOR_CTRL		0x654
522#define RK3568_MIX0_SRC_ALPHA_CTRL		0x658
523#define RK3568_MIX0_DST_ALPHA_CTRL		0x65C
524#define RK3568_HDR0_SRC_COLOR_CTRL		0x6C0
525#define RK3568_HDR0_DST_COLOR_CTRL		0x6C4
526#define RK3568_HDR0_SRC_ALPHA_CTRL		0x6C8
527#define RK3568_HDR0_DST_ALPHA_CTRL		0x6CC
528#define RK3568_VP_BG_MIX_CTRL(vp)		(0x6E0 + (vp) * 4)
529#define RK3568_CLUSTER_DLY_NUM			0x6F0
530#define RK3568_SMART_DLY_NUM			0x6F8
531
532/* Cluster register definition, offset relative to window base */
533#define RK3568_CLUSTER0_CTRL_BASE		0x1000
534#define RK3568_CLUSTER1_CTRL_BASE		0x1200
535#define RK3588_CLUSTER2_CTRL_BASE		0x1400
536#define RK3588_CLUSTER3_CTRL_BASE		0x1600
537#define RK3568_ESMART0_CTRL_BASE		0x1800
538#define RK3568_ESMART1_CTRL_BASE		0x1A00
539#define RK3568_SMART0_CTRL_BASE			0x1C00
540#define RK3568_SMART1_CTRL_BASE			0x1E00
541#define RK3588_ESMART2_CTRL_BASE		0x1C00
542#define RK3588_ESMART3_CTRL_BASE		0x1E00
543
544#define RK3568_CLUSTER_WIN_CTRL0		0x00
545#define RK3568_CLUSTER_WIN_CTRL1		0x04
546#define RK3568_CLUSTER_WIN_CTRL2		0x08
547#define RK3568_CLUSTER_WIN_YRGB_MST		0x10
548#define RK3568_CLUSTER_WIN_CBR_MST		0x14
549#define RK3568_CLUSTER_WIN_VIR			0x18
550#define RK3568_CLUSTER_WIN_ACT_INFO		0x20
551#define RK3568_CLUSTER_WIN_DSP_INFO		0x24
552#define RK3568_CLUSTER_WIN_DSP_ST		0x28
553#define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB	0x30
554#define RK3568_CLUSTER_WIN_TRANSFORM_OFFSET	0x3C
555#define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL	0x50
556#define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE	0x54
557#define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR	0x58
558#define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH	0x5C
559#define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE	0x60
560#define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET	0x64
561#define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET	0x68
562#define RK3568_CLUSTER_WIN_AFBCD_CTRL		0x6C
563
564#define RK3576_CLUSTER_WIN_AFBCD_PLD_PTR_OFFSET	0x78
565
566#define RK3568_CLUSTER_CTRL			0x100
567#define RK3576_CLUSTER_PORT_SEL_IMD		0x1F4
568#define RK3576_CLUSTER_DLY_NUM			0x1F8
569
570/* (E)smart register definition, offset relative to window base */
571#define RK3568_SMART_CTRL0			0x00
572#define RK3568_SMART_CTRL1			0x04
573#define RK3588_SMART_AXI_CTRL			0x08
574#define RK3568_SMART_REGION0_CTRL		0x10
575#define RK3568_SMART_REGION0_YRGB_MST		0x14
576#define RK3568_SMART_REGION0_CBR_MST		0x18
577#define RK3568_SMART_REGION0_VIR		0x1C
578#define RK3568_SMART_REGION0_ACT_INFO		0x20
579#define RK3568_SMART_REGION0_DSP_INFO		0x24
580#define RK3568_SMART_REGION0_DSP_ST		0x28
581#define RK3568_SMART_REGION0_SCL_CTRL		0x30
582#define RK3568_SMART_REGION0_SCL_FACTOR_YRGB	0x34
583#define RK3568_SMART_REGION0_SCL_FACTOR_CBR	0x38
584#define RK3568_SMART_REGION0_SCL_OFFSET		0x3C
585#define RK3568_SMART_REGION1_CTRL		0x40
586#define RK3568_SMART_REGION1_YRGB_MST		0x44
587#define RK3568_SMART_REGION1_CBR_MST		0x48
588#define RK3568_SMART_REGION1_VIR		0x4C
589#define RK3568_SMART_REGION1_ACT_INFO		0x50
590#define RK3568_SMART_REGION1_DSP_INFO		0x54
591#define RK3568_SMART_REGION1_DSP_ST		0x58
592#define RK3568_SMART_REGION1_SCL_CTRL		0x60
593#define RK3568_SMART_REGION1_SCL_FACTOR_YRGB	0x64
594#define RK3568_SMART_REGION1_SCL_FACTOR_CBR	0x68
595#define RK3568_SMART_REGION1_SCL_OFFSET		0x6C
596#define RK3568_SMART_REGION2_CTRL		0x70
597#define RK3568_SMART_REGION2_YRGB_MST		0x74
598#define RK3568_SMART_REGION2_CBR_MST		0x78
599#define RK3568_SMART_REGION2_VIR		0x7C
600#define RK3568_SMART_REGION2_ACT_INFO		0x80
601#define RK3568_SMART_REGION2_DSP_INFO		0x84
602#define RK3568_SMART_REGION2_DSP_ST		0x88
603#define RK3568_SMART_REGION2_SCL_CTRL		0x90
604#define RK3568_SMART_REGION2_SCL_FACTOR_YRGB	0x94
605#define RK3568_SMART_REGION2_SCL_FACTOR_CBR	0x98
606#define RK3568_SMART_REGION2_SCL_OFFSET		0x9C
607#define RK3568_SMART_REGION3_CTRL		0xA0
608#define RK3568_SMART_REGION3_YRGB_MST		0xA4
609#define RK3568_SMART_REGION3_CBR_MST		0xA8
610#define RK3568_SMART_REGION3_VIR		0xAC
611#define RK3568_SMART_REGION3_ACT_INFO		0xB0
612#define RK3568_SMART_REGION3_DSP_INFO		0xB4
613#define RK3568_SMART_REGION3_DSP_ST		0xB8
614#define RK3568_SMART_REGION3_SCL_CTRL		0xC0
615#define RK3568_SMART_REGION3_SCL_FACTOR_YRGB	0xC4
616#define RK3568_SMART_REGION3_SCL_FACTOR_CBR	0xC8
617#define RK3568_SMART_REGION3_SCL_OFFSET		0xCC
618#define RK3568_SMART_COLOR_KEY_CTRL		0xD0
619#define RK3576_SMART_ALPHA_MAP			0xD8
620#define RK3576_SMART_PORT_SEL_IMD		0xF4
621#define RK3576_SMART_DLY_NUM			0xF8
622
623/* HDR register definition */
624#define RK3568_HDR_LUT_CTRL			0x2000
625#define RK3568_HDR_LUT_MST			0x2004
626#define RK3568_SDR2HDR_CTRL			0x2010
627#define RK3568_HDR2SDR_CTRL			0x2020
628#define RK3568_HDR2SDR_SRC_RANGE		0x2024
629#define RK3568_HDR2SDR_NORMFACEETF		0x2028
630#define RK3568_HDR2SDR_DST_RANGE		0x202C
631#define RK3568_HDR2SDR_NORMFACCGAMMA		0x2030
632#define RK3568_HDR_EETF_OETF_Y0			0x203C
633#define RK3568_HDR_SAT_Y0			0x20C0
634#define RK3568_HDR_EOTF_OETF_Y0			0x20F0
635#define RK3568_HDR_OETF_DX_POW1			0x2200
636#define RK3568_HDR_OETF_XN1			0x2300
637
638#define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN		BIT(15)
639
640#define RK3568_VP_DSP_CTRL__STANDBY			BIT(31)
641#define RK3568_VP_DSP_CTRL__DSP_LUT_EN			BIT(28)
642#define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE		BIT(20)
643#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL		GENMASK(19, 18)
644#define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN		BIT(17)
645#define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN		BIT(16)
646#define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y		BIT(15)
647#define RK3568_VP_DSP_CTRL__DSP_RG_SWAP			BIT(10)
648#define RK3568_VP_DSP_CTRL__DSP_RB_SWAP			BIT(9)
649#define RK3568_VP_DSP_CTRL__DSP_BG_SWAP			BIT(8)
650#define RK3568_VP_DSP_CTRL__DSP_INTERLACE		BIT(7)
651#define RK3568_VP_DSP_CTRL__DSP_FILED_POL		BIT(6)
652#define RK3568_VP_DSP_CTRL__P2I_EN			BIT(5)
653#define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV		BIT(4)
654#define RK3568_VP_DSP_CTRL__OUT_MODE			GENMASK(3, 0)
655
656#define RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN		BIT(22)
657
658#define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV		GENMASK(3, 2)
659#define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV		GENMASK(1, 0)
660
661#define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN		BIT(1)
662#define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN		BIT(0)
663
664#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX		GENMASK(26, 25)
665#define RK3568_SYS_DSP_INFACE_EN_LVDS1			BIT(24)
666#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX		GENMASK(22, 21)
667#define RK3568_SYS_DSP_INFACE_EN_MIPI1			BIT(20)
668#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX		GENMASK(19, 18)
669#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX		GENMASK(17, 16)
670#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX		GENMASK(15, 14)
671#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX		GENMASK(11, 10)
672#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX		GENMASK(9, 8)
673#define RK3568_SYS_DSP_INFACE_EN_LVDS0			BIT(5)
674#define RK3568_SYS_DSP_INFACE_EN_MIPI0			BIT(4)
675#define RK3568_SYS_DSP_INFACE_EN_EDP			BIT(3)
676#define RK3568_SYS_DSP_INFACE_EN_HDMI			BIT(1)
677#define RK3568_SYS_DSP_INFACE_EN_RGB			BIT(0)
678
679#define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX		GENMASK(22, 21)
680#define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX		GENMASK(20, 20)
681#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX		GENMASK(19, 18)
682#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX		GENMASK(17, 16)
683#define RK3588_SYS_DSP_INFACE_EN_DP1_MUX		GENMASK(15, 14)
684#define RK3588_SYS_DSP_INFACE_EN_DP0_MUX		GENMASK(13, 12)
685#define RK3588_SYS_DSP_INFACE_EN_DPI			GENMASK(9, 8)
686#define RK3588_SYS_DSP_INFACE_EN_MIPI1			BIT(7)
687#define RK3588_SYS_DSP_INFACE_EN_MIPI0			BIT(6)
688#define RK3588_SYS_DSP_INFACE_EN_HDMI1			BIT(5)
689#define RK3588_SYS_DSP_INFACE_EN_EDP1			BIT(4)
690#define RK3588_SYS_DSP_INFACE_EN_HDMI0			BIT(3)
691#define RK3588_SYS_DSP_INFACE_EN_EDP0			BIT(2)
692#define RK3588_SYS_DSP_INFACE_EN_DP1			BIT(1)
693#define RK3588_SYS_DSP_INFACE_EN_DP0			BIT(0)
694
695#define RK3588_DSP_IF_MIPI1_PCLK_DIV			GENMASK(27, 26)
696#define RK3588_DSP_IF_MIPI0_PCLK_DIV			GENMASK(25, 24)
697#define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV		GENMASK(22, 22)
698#define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV		GENMASK(21, 20)
699#define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV		GENMASK(18, 18)
700#define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV		GENMASK(17, 16)
701
702#define RK3568_DSP_IF_POL__MIPI_PIN_POL			GENMASK(19, 16)
703#define RK3568_DSP_IF_POL__EDP_PIN_POL			GENMASK(15, 12)
704#define RK3568_DSP_IF_POL__HDMI_PIN_POL			GENMASK(7, 4)
705#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL		GENMASK(3, 0)
706
707#define RK3588_DSP_IF_POL__DP1_PIN_POL			GENMASK(14, 12)
708#define RK3588_DSP_IF_POL__DP0_PIN_POL			GENMASK(10, 8)
709
710#define RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL	GENMASK(13, 12)
711
712#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK	BIT(5)
713#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2			BIT(4)
714
715#define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN	BIT(31)
716
717#define RK3568_DSP_IF_POL__CFG_DONE_IMD			BIT(28)
718
719#define VOP2_SYS_AXI_BUS_NUM				2
720
721#define VOP2_CLUSTER_YUV444_10				0x12
722
723#define VOP2_COLOR_KEY_MASK				BIT(31)
724
725#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL		GENMASK(31, 30)
726#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD		BIT(28)
727#define RK3568_OVL_CTRL__YUV_MODE(vp)			BIT(vp)
728
729#define RK3568_VP_BG_MIX_CTRL__BG_DLY			GENMASK(31, 24)
730
731#define RK3568_OVL_PORT_SEL__SEL_PORT			GENMASK(31, 16)
732#define RK3568_OVL_PORT_SEL__SMART1			GENMASK(31, 30)
733#define RK3568_OVL_PORT_SEL__SMART0			GENMASK(29, 28)
734#define RK3588_OVL_PORT_SEL__ESMART3			GENMASK(31, 30)
735#define RK3588_OVL_PORT_SEL__ESMART2			GENMASK(29, 28)
736#define RK3568_OVL_PORT_SEL__ESMART1			GENMASK(27, 26)
737#define RK3568_OVL_PORT_SEL__ESMART0			GENMASK(25, 24)
738#define RK3588_OVL_PORT_SEL__CLUSTER3			GENMASK(23, 22)
739#define RK3588_OVL_PORT_SEL__CLUSTER2			GENMASK(21, 20)
740#define RK3568_OVL_PORT_SEL__CLUSTER1			GENMASK(19, 18)
741#define RK3568_OVL_PORT_SEL__CLUSTER0			GENMASK(17, 16)
742#define RK3588_OVL_PORT_SET__PORT3_MUX			GENMASK(15, 12)
743#define RK3568_OVL_PORT_SET__PORT2_MUX			GENMASK(11, 8)
744#define RK3568_OVL_PORT_SET__PORT1_MUX			GENMASK(7, 4)
745#define RK3568_OVL_PORT_SET__PORT0_MUX			GENMASK(3, 0)
746#define RK3568_OVL_LAYER_SEL__LAYER(layer, x)		((x) << ((layer) * 4))
747
748#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1		GENMASK(31, 24)
749#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0		GENMASK(23, 16)
750#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1		GENMASK(15, 8)
751#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0		GENMASK(7, 0)
752
753#define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN		BIT(0)
754
755#define RK3568_SMART_REGION0_CTRL__WIN0_EN		BIT(0)
756
757#define RK3568_SMART_DLY_NUM__SMART1			GENMASK(31, 24)
758#define RK3568_SMART_DLY_NUM__SMART0			GENMASK(23, 16)
759#define RK3568_SMART_DLY_NUM__ESMART1			GENMASK(15, 8)
760#define RK3568_SMART_DLY_NUM__ESMART0			GENMASK(7, 0)
761
762#define VP_INT_DSP_HOLD_VALID	BIT(6)
763#define VP_INT_FS_FIELD		BIT(5)
764#define VP_INT_POST_BUF_EMPTY	BIT(4)
765#define VP_INT_LINE_FLAG1	BIT(3)
766#define VP_INT_LINE_FLAG0	BIT(2)
767#define VOP2_INT_BUS_ERRPR	BIT(1)
768#define VP_INT_FS		BIT(0)
769
770#define POLFLAG_DCLK_INV	BIT(3)
771
772#define RK3576_OVL_CTRL__YUV_MODE			BIT(0)
773#define RK3576_OVL_BG_MIX_CTRL__BG_DLY			GENMASK(31, 24)
774
775#define RK3576_DSP_IF_CFG_DONE_IMD			BIT(31)
776#define RK3576_DSP_IF_DCLK_SEL_OUT			BIT(21)
777#define RK3576_DSP_IF_PCLK_DIV				BIT(20)
778#define RK3576_DSP_IF_PIN_POL				GENMASK(5, 4)
779#define RK3576_DSP_IF_MUX				GENMASK(3, 2)
780#define RK3576_DSP_IF_CLK_OUT_EN			BIT(1)
781#define RK3576_DSP_IF_EN				BIT(0)
782
783enum vop2_layer_phy_id {
784	ROCKCHIP_VOP2_CLUSTER0 = 0,
785	ROCKCHIP_VOP2_CLUSTER1,
786	ROCKCHIP_VOP2_ESMART0,
787	ROCKCHIP_VOP2_ESMART1,
788	ROCKCHIP_VOP2_SMART0,
789	ROCKCHIP_VOP2_SMART1,
790	ROCKCHIP_VOP2_CLUSTER2,
791	ROCKCHIP_VOP2_CLUSTER3,
792	ROCKCHIP_VOP2_ESMART2,
793	ROCKCHIP_VOP2_ESMART3,
794	ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
795};
796
797extern const struct component_ops vop2_component_ops;
798
799static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
800{
801	regmap_write(vop2->map, offset, v);
802}
803
804static inline void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
805{
806	regmap_write(vp->vop2->map, vp->data->offset + offset, v);
807}
808
809static inline u32 vop2_readl(struct vop2 *vop2, u32 offset)
810{
811	u32 val;
812
813	regmap_read(vop2->map, offset, &val);
814
815	return val;
816}
817
818static inline u32 vop2_vp_read(struct vop2_video_port *vp, u32 offset)
819{
820	u32 val;
821
822	regmap_read(vp->vop2->map, vp->data->offset + offset, &val);
823
824	return val;
825}
826
827static inline void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
828{
829	regmap_field_write(win->reg[reg], v);
830}
831
832static inline bool vop2_cluster_window(const struct vop2_win *win)
833{
834	return win->data->feature & WIN_FEATURE_CLUSTER;
835}
836
837static inline struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
838{
839	return container_of(crtc, struct vop2_video_port, crtc);
840}
841
842static inline struct vop2_win *to_vop2_win(struct drm_plane *p)
843{
844	return container_of(p, struct vop2_win, base);
845}
846
847/*
848 * Note:
849 * The write mask function is documented but missing on rk3566/8, writes
850 * to these bits have no effect. For newer soc(rk3588 and following) the
851 * write mask is needed for register writes.
852 *
853 * GLB_CFG_DONE_EN has no write mask bit.
854 *
855 */
856static inline void vop2_cfg_done(struct vop2_video_port *vp)
857{
858	struct vop2 *vop2 = vp->vop2;
859	u32 val = RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN;
860
861	val |= BIT(vp->id) | (BIT(vp->id) << 16);
862
863	regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val);
864}
865
866#endif /* _ROCKCHIP_DRM_VOP2_H */