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rk3066_hdmi.c
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linux-6.19.14/drivers/gpu/drm/rockchip/rk3066_hdmi.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Zheng Yang <zhengyang@rock-chips.com> 5 */ 6 7#include <drm/drm_atomic.h> 8#include <drm/drm_bridge_connector.h> 9#include <drm/display/drm_hdmi_helper.h> 10#include <drm/display/drm_hdmi_state_helper.h> 11#include <drm/drm_edid.h> 12#include <drm/drm_of.h> 13#include <drm/drm_print.h> 14#include <drm/drm_probe_helper.h> 15#include <drm/drm_simple_kms_helper.h> 16 17#include <linux/clk.h> 18#include <linux/mfd/syscon.h> 19#include <linux/platform_device.h> 20#include <linux/regmap.h> 21 22#include "rk3066_hdmi.h" 23 24#include "rockchip_drm_drv.h" 25 26#define DEFAULT_PLLA_RATE 30000000 27 28struct hdmi_data_info { 29 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ 30 unsigned int enc_out_format; 31 unsigned int colorimetry; 32}; 33 34struct rk3066_hdmi_i2c { 35 struct i2c_adapter adap; 36 37 u8 ddc_addr; 38 u8 segment_addr; 39 u8 stat; 40 41 struct mutex i2c_lock; /* For i2c operation. */ 42 struct completion cmpltn; 43}; 44 45struct rk3066_hdmi { 46 struct device *dev; 47 struct drm_device *drm_dev; 48 struct regmap *grf_regmap; 49 int irq; 50 struct clk *hclk; 51 void __iomem *regs; 52 53 struct drm_bridge bridge; 54 struct drm_connector *connector; 55 struct rockchip_encoder encoder; 56 57 struct rk3066_hdmi_i2c *i2c; 58 59 unsigned int tmdsclk; 60 61 struct hdmi_data_info hdmi_data; 62}; 63 64static struct rk3066_hdmi *bridge_to_rk3066_hdmi(struct drm_bridge *bridge) 65{ 66 return container_of(bridge, struct rk3066_hdmi, bridge); 67} 68 69static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) 70{ 71 return readl_relaxed(hdmi->regs + offset); 72} 73 74static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) 75{ 76 writel_relaxed(val, hdmi->regs + offset); 77} 78 79static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, 80 u32 msk, u32 val) 81{ 82 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 83 84 temp |= val & msk; 85 hdmi_writeb(hdmi, offset, temp); 86} 87 88static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi) 89{ 90 int ddc_bus_freq; 91 92 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; 93 94 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 95 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 96 97 /* Clear the EDID interrupt flag and mute the interrupt. */ 98 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 99 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK); 100} 101 102static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi) 103{ 104 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK; 105} 106 107static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode) 108{ 109 u8 current_mode, next_mode; 110 u8 i = 0; 111 112 current_mode = rk3066_hdmi_get_power_mode(hdmi); 113 114 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode); 115 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode); 116 117 if (current_mode == mode) 118 return; 119 120 do { 121 if (current_mode > mode) { 122 next_mode = current_mode / 2; 123 } else { 124 if (current_mode < HDMI_SYS_POWER_MODE_A) 125 next_mode = HDMI_SYS_POWER_MODE_A; 126 else 127 next_mode = current_mode * 2; 128 } 129 130 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode); 131 132 if (next_mode != HDMI_SYS_POWER_MODE_D) { 133 hdmi_modb(hdmi, HDMI_SYS_CTRL, 134 HDMI_SYS_POWER_MODE_MASK, next_mode); 135 } else { 136 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 137 HDMI_SYS_POWER_MODE_D | 138 HDMI_SYS_PLL_RESET_MASK); 139 usleep_range(90, 100); 140 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 141 HDMI_SYS_POWER_MODE_D | 142 HDMI_SYS_PLLB_RESET); 143 usleep_range(90, 100); 144 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 145 HDMI_SYS_POWER_MODE_D); 146 } 147 current_mode = next_mode; 148 i = i + 1; 149 } while ((next_mode != mode) && (i < 5)); 150 151 /* 152 * When the IP controller isn't configured with accurate video timing, 153 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz, 154 * so we need to init the TMDS rate to the PCLK rate and reconfigure 155 * the DDC clock. 156 */ 157 if (mode < HDMI_SYS_POWER_MODE_D) 158 hdmi->tmdsclk = DEFAULT_PLLA_RATE; 159} 160 161static int rk3066_hdmi_bridge_clear_infoframe(struct drm_bridge *bridge, 162 enum hdmi_infoframe_type type) 163{ 164 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 165 166 if (type != HDMI_INFOFRAME_TYPE_AVI) { 167 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type); 168 return 0; 169 } 170 171 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, HDMI_INFOFRAME_AVI); 172 173 return 0; 174} 175 176static int 177rk3066_hdmi_bridge_write_infoframe(struct drm_bridge *bridge, 178 enum hdmi_infoframe_type type, 179 const u8 *buffer, size_t len) 180{ 181 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 182 ssize_t i; 183 184 if (type != HDMI_INFOFRAME_TYPE_AVI) { 185 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type); 186 return 0; 187 } 188 189 rk3066_hdmi_bridge_clear_infoframe(bridge, type); 190 191 for (i = 0; i < len; i++) 192 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, buffer[i]); 193 194 return 0; 195} 196 197static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi, 198 struct drm_display_mode *mode) 199{ 200 int value, vsync_offset; 201 202 /* Set the details for the external polarity and interlace mode. */ 203 value = HDMI_EXT_VIDEO_SET_EN; 204 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 205 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW; 206 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 207 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW; 208 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 209 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE; 210 211 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) 212 vsync_offset = 6; 213 else 214 vsync_offset = 0; 215 216 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT; 217 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value); 218 219 /* Set the details for the external video timing. */ 220 value = mode->htotal; 221 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF); 222 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF); 223 224 value = mode->htotal - mode->hdisplay; 225 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF); 226 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF); 227 228 value = mode->htotal - mode->hsync_start; 229 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF); 230 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF); 231 232 value = mode->hsync_end - mode->hsync_start; 233 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF); 234 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF); 235 236 value = mode->vtotal; 237 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF); 238 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF); 239 240 value = mode->vtotal - mode->vdisplay; 241 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF); 242 243 value = mode->vtotal - mode->vsync_start + vsync_offset; 244 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF); 245 246 value = mode->vsync_end - mode->vsync_start; 247 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF); 248 249 return 0; 250} 251 252static void 253rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value) 254{ 255 hdmi_writeb(hdmi, offset, value); 256 hdmi_modb(hdmi, HDMI_SYS_CTRL, 257 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET); 258 usleep_range(90, 100); 259 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0); 260 usleep_range(900, 1000); 261} 262 263static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi) 264{ 265 /* TMDS uses the same frequency as dclk. */ 266 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22); 267 268 /* 269 * The semi-public documentation does not describe the hdmi registers 270 * used by the function rk3066_hdmi_phy_write(), so we keep using 271 * these magic values for now. 272 */ 273 if (hdmi->tmdsclk > 100000000) { 274 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E); 275 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 276 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 277 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 278 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA); 279 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1); 280 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 281 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22); 282 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 283 } else if (hdmi->tmdsclk > 50000000) { 284 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06); 285 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 286 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 287 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 288 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA); 289 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3); 290 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 291 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 292 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 293 } else { 294 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02); 295 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 296 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 297 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 298 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2); 299 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2); 300 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 301 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 302 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 303 } 304} 305 306static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, 307 struct drm_atomic_state *state) 308{ 309 struct drm_bridge *bridge = &hdmi->bridge; 310 struct drm_connector *connector; 311 struct drm_display_info *display; 312 struct drm_display_mode *mode; 313 struct drm_connector_state *new_conn_state; 314 struct drm_crtc_state *new_crtc_state; 315 316 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 317 318 new_conn_state = drm_atomic_get_new_connector_state(state, connector); 319 if (WARN_ON(!new_conn_state)) 320 return -EINVAL; 321 322 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 323 if (WARN_ON(!new_crtc_state)) 324 return -EINVAL; 325 326 display = &connector->display_info; 327 mode = &new_crtc_state->adjusted_mode; 328 329 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); 330 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; 331 332 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || 333 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || 334 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || 335 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) 336 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; 337 else 338 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; 339 340 hdmi->tmdsclk = mode->clock * 1000; 341 342 /* Mute video and audio output. */ 343 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, 344 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE); 345 346 /* Set power state to mode B. */ 347 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B) 348 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 349 350 /* Input video mode is RGB 24 bit. Use external data enable signal. */ 351 hdmi_modb(hdmi, HDMI_AV_CTRL1, 352 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE); 353 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1, 354 HDMI_VIDEO_OUTPUT_RGB444 | 355 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT | 356 HDMI_VIDEO_INPUT_COLOR_RGB); 357 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20); 358 359 rk3066_hdmi_config_video_timing(hdmi, mode); 360 361 if (display->is_hdmi) { 362 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 363 HDMI_VIDEO_MODE_HDMI); 364 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 365 } else { 366 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0); 367 } 368 369 rk3066_hdmi_config_phy(hdmi); 370 371 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E); 372 373 /* 374 * When the IP controller is configured with accurate video 375 * timing, the TMDS clock source should be switched to 376 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode 377 * clock rate and reconfigure the DDC clock. 378 */ 379 rk3066_hdmi_i2c_init(hdmi); 380 381 /* Unmute video output. */ 382 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 383 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE); 384 return 0; 385} 386 387static void rk3066_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 388 struct drm_atomic_state *state) 389{ 390 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 391 struct drm_connector_state *conn_state; 392 struct drm_crtc_state *crtc_state; 393 int mux, val; 394 395 conn_state = drm_atomic_get_new_connector_state(state, hdmi->connector); 396 if (WARN_ON(!conn_state)) 397 return; 398 399 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 400 if (WARN_ON(!crtc_state)) 401 return; 402 403 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, &hdmi->encoder.encoder); 404 if (mux) 405 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL; 406 else 407 val = HDMI_VIDEO_SEL << 16; 408 409 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val); 410 411 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n", 412 (mux) ? "1" : "0"); 413 414 rk3066_hdmi_setup(hdmi, state); 415} 416 417static void rk3066_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 418 struct drm_atomic_state *state) 419{ 420 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 421 422 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); 423 424 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) { 425 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2, 426 HDMI_VIDEO_AUDIO_DISABLE_MASK); 427 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 428 HDMI_AUDIO_CP_LOGIC_RESET_MASK, 429 HDMI_AUDIO_CP_LOGIC_RESET); 430 usleep_range(500, 510); 431 } 432 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 433} 434 435static int 436rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 437 struct drm_crtc_state *crtc_state, 438 struct drm_connector_state *conn_state) 439{ 440 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 441 442 s->output_mode = ROCKCHIP_OUT_MODE_P888; 443 s->output_type = DRM_MODE_CONNECTOR_HDMIA; 444 445 return 0; 446} 447 448static const 449struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { 450 .atomic_check = rk3066_hdmi_encoder_atomic_check, 451}; 452 453static enum drm_connector_status 454rk3066_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 455{ 456 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 457 458 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? 459 connector_status_connected : connector_status_disconnected; 460} 461 462static const struct drm_edid * 463rk3066_hdmi_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) 464{ 465 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 466 const struct drm_edid *drm_edid; 467 468 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 469 if (!drm_edid) 470 dev_dbg(hdmi->dev, "failed to get edid\n"); 471 472 return drm_edid; 473} 474 475static enum drm_mode_status 476rk3066_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 477 const struct drm_display_info *info, 478 const struct drm_display_mode *mode) 479{ 480 u32 vic = drm_match_cea_mode(mode); 481 482 if (vic > 1) 483 return MODE_OK; 484 else 485 return MODE_BAD; 486} 487 488static const struct drm_bridge_funcs rk3066_hdmi_bridge_funcs = { 489 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 490 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 491 .atomic_reset = drm_atomic_helper_bridge_reset, 492 .atomic_enable = rk3066_hdmi_bridge_atomic_enable, 493 .atomic_disable = rk3066_hdmi_bridge_atomic_disable, 494 .detect = rk3066_hdmi_bridge_detect, 495 .edid_read = rk3066_hdmi_bridge_edid_read, 496 .hdmi_clear_infoframe = rk3066_hdmi_bridge_clear_infoframe, 497 .hdmi_write_infoframe = rk3066_hdmi_bridge_write_infoframe, 498 .mode_valid = rk3066_hdmi_bridge_mode_valid, 499}; 500 501 502static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id) 503{ 504 struct rk3066_hdmi *hdmi = dev_id; 505 irqreturn_t ret = IRQ_NONE; 506 u8 interrupt; 507 508 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A) 509 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B); 510 511 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1); 512 if (interrupt) 513 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt); 514 515 if (interrupt & HDMI_INTR_EDID_MASK) { 516 hdmi->i2c->stat = interrupt; 517 complete(&hdmi->i2c->cmpltn); 518 } 519 520 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS)) 521 ret = IRQ_WAKE_THREAD; 522 523 return ret; 524} 525 526static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id) 527{ 528 struct rk3066_hdmi *hdmi = dev_id; 529 530 drm_helper_hpd_irq_event(hdmi->connector->dev); 531 532 return IRQ_HANDLED; 533} 534 535static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 536{ 537 int length = msgs->len; 538 u8 *buf = msgs->buf; 539 int ret; 540 541 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10); 542 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR) 543 return -EAGAIN; 544 545 while (length--) 546 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR); 547 548 return 0; 549} 550 551static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 552{ 553 /* 554 * The DDC module only supports read EDID message, so 555 * we assume that each word write to this i2c adapter 556 * should be the offset of the EDID word address. 557 */ 558 if (msgs->len != 1 || 559 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) 560 return -EINVAL; 561 562 reinit_completion(&hdmi->i2c->cmpltn); 563 564 if (msgs->addr == DDC_SEGMENT_ADDR) 565 hdmi->i2c->segment_addr = msgs->buf[0]; 566 if (msgs->addr == DDC_ADDR) 567 hdmi->i2c->ddc_addr = msgs->buf[0]; 568 569 /* Set edid fifo first address. */ 570 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00); 571 572 /* Set edid word address 0x00/0x80. */ 573 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 574 575 /* Set edid segment pointer. */ 576 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 577 578 return 0; 579} 580 581static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap, 582 struct i2c_msg *msgs, int num) 583{ 584 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap); 585 struct rk3066_hdmi_i2c *i2c = hdmi->i2c; 586 int i, ret = 0; 587 588 mutex_lock(&i2c->i2c_lock); 589 590 rk3066_hdmi_i2c_init(hdmi); 591 592 /* Unmute HDMI EDID interrupt. */ 593 hdmi_modb(hdmi, HDMI_INTR_MASK1, 594 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK); 595 i2c->stat = 0; 596 597 for (i = 0; i < num; i++) { 598 DRM_DEV_DEBUG(hdmi->dev, 599 "xfer: num: %d/%d, len: %d, flags: %#x\n", 600 i + 1, num, msgs[i].len, msgs[i].flags); 601 602 if (msgs[i].flags & I2C_M_RD) 603 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]); 604 else 605 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]); 606 607 if (ret < 0) 608 break; 609 } 610 611 if (!ret) 612 ret = num; 613 614 /* Mute HDMI EDID interrupt. */ 615 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 616 617 mutex_unlock(&i2c->i2c_lock); 618 619 return ret; 620} 621 622static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter) 623{ 624 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 625} 626 627static const struct i2c_algorithm rk3066_hdmi_algorithm = { 628 .master_xfer = rk3066_hdmi_i2c_xfer, 629 .functionality = rk3066_hdmi_i2c_func, 630}; 631 632static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi) 633{ 634 struct i2c_adapter *adap; 635 struct rk3066_hdmi_i2c *i2c; 636 int ret; 637 638 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 639 if (!i2c) 640 return ERR_PTR(-ENOMEM); 641 642 mutex_init(&i2c->i2c_lock); 643 init_completion(&i2c->cmpltn); 644 645 adap = &i2c->adap; 646 adap->owner = THIS_MODULE; 647 adap->dev.parent = hdmi->dev; 648 adap->dev.of_node = hdmi->dev->of_node; 649 adap->algo = &rk3066_hdmi_algorithm; 650 strscpy(adap->name, "RK3066 HDMI", sizeof(adap->name)); 651 i2c_set_adapdata(adap, hdmi); 652 653 ret = devm_i2c_add_adapter(hdmi->dev, adap); 654 if (ret) { 655 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n", 656 adap->name); 657 devm_kfree(hdmi->dev, i2c); 658 return ERR_PTR(ret); 659 } 660 661 hdmi->i2c = i2c; 662 663 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 664 665 return adap; 666} 667 668static int 669rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) 670{ 671 struct drm_encoder *encoder = &hdmi->encoder.encoder; 672 struct device *dev = hdmi->dev; 673 int ret; 674 675 encoder->possible_crtcs = 676 drm_of_find_possible_crtcs(drm, dev->of_node); 677 678 /* 679 * If we failed to find the CRTC(s) which this encoder is 680 * supposed to be connected to, it's because the CRTC has 681 * not been registered yet. Defer probing, and hope that 682 * the required CRTC is added later. 683 */ 684 if (encoder->possible_crtcs == 0) 685 return -EPROBE_DEFER; 686 687 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs); 688 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 689 690 hdmi->bridge.driver_private = hdmi; 691 hdmi->bridge.funcs = &rk3066_hdmi_bridge_funcs; 692 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 693 DRM_BRIDGE_OP_EDID | 694 DRM_BRIDGE_OP_HDMI | 695 DRM_BRIDGE_OP_HPD; 696 hdmi->bridge.of_node = hdmi->dev->of_node; 697 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 698 hdmi->bridge.vendor = "Rockchip"; 699 hdmi->bridge.product = "RK3066 HDMI"; 700 701 hdmi->bridge.ddc = rk3066_hdmi_i2c_adapter(hdmi); 702 if (IS_ERR(hdmi->bridge.ddc)) 703 return PTR_ERR(hdmi->bridge.ddc); 704 705 if (IS_ERR(hdmi->bridge.ddc)) 706 return PTR_ERR(hdmi->bridge.ddc); 707 708 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 709 if (ret) 710 return ret; 711 712 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 713 if (ret) 714 return ret; 715 716 hdmi->connector = drm_bridge_connector_init(drm, encoder); 717 if (IS_ERR(hdmi->connector)) { 718 ret = PTR_ERR(hdmi->connector); 719 dev_err(hdmi->dev, "failed to init bridge connector: %d\n", ret); 720 return ret; 721 } 722 723 drm_connector_attach_encoder(hdmi->connector, encoder); 724 725 return 0; 726} 727 728static int rk3066_hdmi_bind(struct device *dev, struct device *master, 729 void *data) 730{ 731 struct platform_device *pdev = to_platform_device(dev); 732 struct drm_device *drm = data; 733 struct rk3066_hdmi *hdmi; 734 int irq; 735 int ret; 736 737 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 738 if (!hdmi) 739 return -ENOMEM; 740 741 hdmi->dev = dev; 742 hdmi->drm_dev = drm; 743 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 744 if (IS_ERR(hdmi->regs)) 745 return PTR_ERR(hdmi->regs); 746 747 irq = platform_get_irq(pdev, 0); 748 if (irq < 0) 749 return irq; 750 751 hdmi->hclk = devm_clk_get(dev, "hclk"); 752 if (IS_ERR(hdmi->hclk)) { 753 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n"); 754 return PTR_ERR(hdmi->hclk); 755 } 756 757 ret = clk_prepare_enable(hdmi->hclk); 758 if (ret) { 759 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret); 760 return ret; 761 } 762 763 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 764 "rockchip,grf"); 765 if (IS_ERR(hdmi->grf_regmap)) { 766 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n"); 767 ret = PTR_ERR(hdmi->grf_regmap); 768 goto err_disable_hclk; 769 } 770 771 /* internal hclk = hdmi_hclk / 25 */ 772 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25); 773 774 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 775 usleep_range(999, 1000); 776 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG); 777 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0); 778 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0); 779 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0); 780 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 781 782 ret = rk3066_hdmi_register(drm, hdmi); 783 if (ret) 784 goto err_disable_hclk; 785 786 dev_set_drvdata(dev, hdmi); 787 788 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq, 789 rk3066_hdmi_irq, IRQF_SHARED, 790 dev_name(dev), hdmi); 791 if (ret) { 792 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret); 793 goto err_cleanup_hdmi; 794 } 795 796 return 0; 797 798err_cleanup_hdmi: 799 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 800err_disable_hclk: 801 clk_disable_unprepare(hdmi->hclk); 802 803 return ret; 804} 805 806static void rk3066_hdmi_unbind(struct device *dev, struct device *master, 807 void *data) 808{ 809 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); 810 811 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 812 813 clk_disable_unprepare(hdmi->hclk); 814} 815 816static const struct component_ops rk3066_hdmi_ops = { 817 .bind = rk3066_hdmi_bind, 818 .unbind = rk3066_hdmi_unbind, 819}; 820 821static int rk3066_hdmi_probe(struct platform_device *pdev) 822{ 823 return component_add(&pdev->dev, &rk3066_hdmi_ops); 824} 825 826static void rk3066_hdmi_remove(struct platform_device *pdev) 827{ 828 component_del(&pdev->dev, &rk3066_hdmi_ops); 829} 830 831static const struct of_device_id rk3066_hdmi_dt_ids[] = { 832 { .compatible = "rockchip,rk3066-hdmi" }, 833 { /* sentinel */ }, 834}; 835MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids); 836 837struct platform_driver rk3066_hdmi_driver = { 838 .probe = rk3066_hdmi_probe, 839 .remove = rk3066_hdmi_remove, 840 .driver = { 841 .name = "rockchip-rk3066-hdmi", 842 .of_match_table = rk3066_hdmi_dt_ids, 843 }, 844};
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