inno_hdmi.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) Rockchip Electronics Co., Ltd.
   4 *    Zheng Yang <zhengyang@rock-chips.com>
   5 *    Yakir Yang <ykk@rock-chips.com>
   6 */
   7
   8#include <linux/irq.h>
   9#include <linux/clk.h>
  10#include <linux/delay.h>
  11#include <linux/err.h>
  12#include <linux/hdmi.h>
  13#include <linux/hw_bitfield.h>
  14#include <linux/mfd/syscon.h>
  15#include <linux/mod_devicetable.h>
  16#include <linux/module.h>
  17#include <linux/mutex.h>
  18#include <linux/platform_device.h>
  19#include <linux/regmap.h>
  20
  21#include <drm/drm_atomic.h>
  22#include <drm/drm_atomic_helper.h>
  23#include <drm/drm_edid.h>
  24#include <drm/drm_of.h>
  25#include <drm/drm_print.h>
  26#include <drm/drm_probe_helper.h>
  27#include <drm/drm_simple_kms_helper.h>
  28
  29#include <drm/display/drm_hdmi_helper.h>
  30#include <drm/display/drm_hdmi_state_helper.h>
  31
  32#include "rockchip_drm_drv.h"
  33
  34#define INNO_HDMI_MIN_TMDS_CLOCK  25000000U
  35
  36#define DDC_SEGMENT_ADDR		0x30
  37
  38#define HDMI_SCL_RATE			(100 * 1000)
  39
  40#define DDC_BUS_FREQ_L			0x4b
  41#define DDC_BUS_FREQ_H			0x4c
  42
  43#define HDMI_SYS_CTRL			0x00
  44#define m_RST_ANALOG			BIT(6)
  45#define v_RST_ANALOG			(0 << 6)
  46#define v_NOT_RST_ANALOG		BIT(6)
  47#define m_RST_DIGITAL			BIT(5)
  48#define v_RST_DIGITAL			(0 << 5)
  49#define v_NOT_RST_DIGITAL		BIT(5)
  50#define m_REG_CLK_INV			BIT(4)
  51#define v_REG_CLK_NOT_INV		(0 << 4)
  52#define v_REG_CLK_INV			BIT(4)
  53#define m_VCLK_INV			BIT(3)
  54#define v_VCLK_NOT_INV			(0 << 3)
  55#define v_VCLK_INV			BIT(3)
  56#define m_REG_CLK_SOURCE		BIT(2)
  57#define v_REG_CLK_SOURCE_TMDS		(0 << 2)
  58#define v_REG_CLK_SOURCE_SYS		BIT(2)
  59#define m_POWER				BIT(1)
  60#define v_PWR_ON			(0 << 1)
  61#define v_PWR_OFF			BIT(1)
  62#define m_INT_POL			BIT(0)
  63#define v_INT_POL_HIGH			1
  64#define v_INT_POL_LOW			0
  65
  66#define HDMI_VIDEO_CONTRL1		0x01
  67#define m_VIDEO_INPUT_FORMAT		(7 << 1)
  68#define m_DE_SOURCE			BIT(0)
  69#define v_VIDEO_INPUT_FORMAT(n)		((n) << 1)
  70#define v_DE_EXTERNAL			1
  71#define v_DE_INTERNAL			0
  72enum {
  73	VIDEO_INPUT_SDR_RGB444 = 0,
  74	VIDEO_INPUT_DDR_RGB444 = 5,
  75	VIDEO_INPUT_DDR_YCBCR422 = 6
  76};
  77
  78#define HDMI_VIDEO_CONTRL2		0x02
  79#define m_VIDEO_OUTPUT_COLOR		(3 << 6)
  80#define m_VIDEO_INPUT_BITS		(3 << 4)
  81#define m_VIDEO_INPUT_CSP		BIT(0)
  82#define v_VIDEO_OUTPUT_COLOR(n)		(((n) & 0x3) << 6)
  83#define v_VIDEO_INPUT_BITS(n)		((n) << 4)
  84#define v_VIDEO_INPUT_CSP(n)		((n) << 0)
  85enum {
  86	VIDEO_INPUT_12BITS = 0,
  87	VIDEO_INPUT_10BITS = 1,
  88	VIDEO_INPUT_REVERT = 2,
  89	VIDEO_INPUT_8BITS = 3,
  90};
  91
  92#define HDMI_VIDEO_CONTRL		0x03
  93#define m_VIDEO_AUTO_CSC		BIT(7)
  94#define v_VIDEO_AUTO_CSC(n)		((n) << 7)
  95#define m_VIDEO_C0_C2_SWAP		BIT(0)
  96#define v_VIDEO_C0_C2_SWAP(n)		((n) << 0)
  97enum {
  98	C0_C2_CHANGE_ENABLE = 0,
  99	C0_C2_CHANGE_DISABLE = 1,
 100	AUTO_CSC_DISABLE = 0,
 101	AUTO_CSC_ENABLE = 1,
 102};
 103
 104#define HDMI_VIDEO_CONTRL3		0x04
 105#define m_COLOR_DEPTH_NOT_INDICATED	BIT(4)
 106#define m_SOF				BIT(3)
 107#define m_COLOR_RANGE			BIT(2)
 108#define m_CSC				BIT(0)
 109#define v_COLOR_DEPTH_NOT_INDICATED(n)	((n) << 4)
 110#define v_SOF_ENABLE			(0 << 3)
 111#define v_SOF_DISABLE			BIT(3)
 112#define v_COLOR_RANGE_FULL		BIT(2)
 113#define v_COLOR_RANGE_LIMITED		(0 << 2)
 114#define v_CSC_ENABLE			1
 115#define v_CSC_DISABLE			0
 116
 117#define HDMI_AV_MUTE			0x05
 118#define m_AVMUTE_CLEAR			BIT(7)
 119#define m_AVMUTE_ENABLE			BIT(6)
 120#define m_AUDIO_MUTE			BIT(1)
 121#define m_VIDEO_BLACK			BIT(0)
 122#define v_AVMUTE_CLEAR(n)		((n) << 7)
 123#define v_AVMUTE_ENABLE(n)		((n) << 6)
 124#define v_AUDIO_MUTE(n)			((n) << 1)
 125#define v_VIDEO_MUTE(n)			((n) << 0)
 126
 127#define HDMI_VIDEO_TIMING_CTL		0x08
 128#define v_HSYNC_POLARITY(n)		((n) << 3)
 129#define v_VSYNC_POLARITY(n)		((n) << 2)
 130#define v_INETLACE(n)			((n) << 1)
 131#define v_EXTERANL_VIDEO(n)		((n) << 0)
 132
 133#define HDMI_VIDEO_EXT_HTOTAL_L		0x09
 134#define HDMI_VIDEO_EXT_HTOTAL_H		0x0a
 135#define HDMI_VIDEO_EXT_HBLANK_L		0x0b
 136#define HDMI_VIDEO_EXT_HBLANK_H		0x0c
 137#define HDMI_VIDEO_EXT_HDELAY_L		0x0d
 138#define HDMI_VIDEO_EXT_HDELAY_H		0x0e
 139#define HDMI_VIDEO_EXT_HDURATION_L	0x0f
 140#define HDMI_VIDEO_EXT_HDURATION_H	0x10
 141#define HDMI_VIDEO_EXT_VTOTAL_L		0x11
 142#define HDMI_VIDEO_EXT_VTOTAL_H		0x12
 143#define HDMI_VIDEO_EXT_VBLANK		0x13
 144#define HDMI_VIDEO_EXT_VDELAY		0x14
 145#define HDMI_VIDEO_EXT_VDURATION	0x15
 146
 147#define HDMI_VIDEO_CSC_COEF		0x18
 148
 149#define HDMI_AUDIO_CTRL1		0x35
 150enum {
 151	CTS_SOURCE_INTERNAL = 0,
 152	CTS_SOURCE_EXTERNAL = 1,
 153};
 154
 155#define v_CTS_SOURCE(n)			((n) << 7)
 156
 157enum {
 158	DOWNSAMPLE_DISABLE = 0,
 159	DOWNSAMPLE_1_2 = 1,
 160	DOWNSAMPLE_1_4 = 2,
 161};
 162
 163#define v_DOWN_SAMPLE(n)		((n) << 5)
 164
 165enum {
 166	AUDIO_SOURCE_IIS = 0,
 167	AUDIO_SOURCE_SPDIF = 1,
 168};
 169
 170#define v_AUDIO_SOURCE(n)		((n) << 3)
 171
 172#define v_MCLK_ENABLE(n)		((n) << 2)
 173
 174enum {
 175	MCLK_128FS = 0,
 176	MCLK_256FS = 1,
 177	MCLK_384FS = 2,
 178	MCLK_512FS = 3,
 179};
 180
 181#define v_MCLK_RATIO(n)			(n)
 182
 183#define AUDIO_SAMPLE_RATE		0x37
 184
 185enum {
 186	AUDIO_32K = 0x3,
 187	AUDIO_441K = 0x0,
 188	AUDIO_48K = 0x2,
 189	AUDIO_882K = 0x8,
 190	AUDIO_96K = 0xa,
 191	AUDIO_1764K = 0xc,
 192	AUDIO_192K = 0xe,
 193};
 194
 195#define AUDIO_I2S_MODE			0x38
 196
 197enum {
 198	I2S_CHANNEL_1_2 = 1,
 199	I2S_CHANNEL_3_4 = 3,
 200	I2S_CHANNEL_5_6 = 7,
 201	I2S_CHANNEL_7_8 = 0xf
 202};
 203
 204#define v_I2S_CHANNEL(n)		((n) << 2)
 205
 206enum {
 207	I2S_STANDARD = 0,
 208	I2S_LEFT_JUSTIFIED = 1,
 209	I2S_RIGHT_JUSTIFIED = 2,
 210};
 211
 212#define v_I2S_MODE(n)			(n)
 213
 214#define AUDIO_I2S_MAP			0x39
 215#define AUDIO_I2S_SWAPS_SPDIF		0x3a
 216#define v_SPIDF_FREQ(n)			(n)
 217
 218#define N_32K				0x1000
 219#define N_441K				0x1880
 220#define N_882K				0x3100
 221#define N_1764K				0x6200
 222#define N_48K				0x1800
 223#define N_96K				0x3000
 224#define N_192K				0x6000
 225
 226#define HDMI_AUDIO_CHANNEL_STATUS	0x3e
 227#define m_AUDIO_STATUS_NLPCM		BIT(7)
 228#define m_AUDIO_STATUS_USE		BIT(6)
 229#define m_AUDIO_STATUS_COPYRIGHT	BIT(5)
 230#define m_AUDIO_STATUS_ADDITION		(3 << 2)
 231#define m_AUDIO_STATUS_CLK_ACCURACY	(2 << 0)
 232#define v_AUDIO_STATUS_NLPCM(n)		(((n) & 1) << 7)
 233#define AUDIO_N_H			0x3f
 234#define AUDIO_N_M			0x40
 235#define AUDIO_N_L			0x41
 236
 237#define HDMI_AUDIO_CTS_H		0x45
 238#define HDMI_AUDIO_CTS_M		0x46
 239#define HDMI_AUDIO_CTS_L		0x47
 240
 241#define HDMI_DDC_CLK_L			0x4b
 242#define HDMI_DDC_CLK_H			0x4c
 243
 244#define HDMI_EDID_SEGMENT_POINTER	0x4d
 245#define HDMI_EDID_WORD_ADDR		0x4e
 246#define HDMI_EDID_FIFO_OFFSET		0x4f
 247#define HDMI_EDID_FIFO_ADDR		0x50
 248
 249#define HDMI_PACKET_SEND_MANUAL		0x9c
 250#define HDMI_PACKET_SEND_AUTO		0x9d
 251#define m_PACKET_GCP_EN			BIT(7)
 252#define m_PACKET_MSI_EN			BIT(6)
 253#define m_PACKET_SDI_EN			BIT(5)
 254#define m_PACKET_VSI_EN			BIT(4)
 255#define v_PACKET_GCP_EN(n)		(((n) & 1) << 7)
 256#define v_PACKET_MSI_EN(n)		(((n) & 1) << 6)
 257#define v_PACKET_SDI_EN(n)		(((n) & 1) << 5)
 258#define v_PACKET_VSI_EN(n)		(((n) & 1) << 4)
 259
 260#define HDMI_CONTROL_PACKET_BUF_INDEX	0x9f
 261
 262enum {
 263	INFOFRAME_VSI = 0x05,
 264	INFOFRAME_AVI = 0x06,
 265	INFOFRAME_AAI = 0x08,
 266};
 267
 268#define HDMI_CONTROL_PACKET_ADDR	0xa0
 269#define HDMI_MAXIMUM_INFO_FRAME_SIZE	0x11
 270
 271enum {
 272	AVI_COLOR_MODE_RGB = 0,
 273	AVI_COLOR_MODE_YCBCR422 = 1,
 274	AVI_COLOR_MODE_YCBCR444 = 2,
 275	AVI_COLORIMETRY_NO_DATA = 0,
 276
 277	AVI_COLORIMETRY_SMPTE_170M = 1,
 278	AVI_COLORIMETRY_ITU709 = 2,
 279	AVI_COLORIMETRY_EXTENDED = 3,
 280
 281	AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
 282	AVI_CODED_FRAME_ASPECT_4_3 = 1,
 283	AVI_CODED_FRAME_ASPECT_16_9 = 2,
 284
 285	ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
 286	ACTIVE_ASPECT_RATE_4_3 = 0x09,
 287	ACTIVE_ASPECT_RATE_16_9 = 0x0A,
 288	ACTIVE_ASPECT_RATE_14_9 = 0x0B,
 289};
 290
 291#define HDMI_HDCP_CTRL			0x52
 292#define m_HDMI_DVI			BIT(1)
 293#define v_HDMI_DVI(n)			((n) << 1)
 294
 295#define HDMI_INTERRUPT_MASK1		0xc0
 296#define HDMI_INTERRUPT_STATUS1		0xc1
 297#define	m_INT_ACTIVE_VSYNC		BIT(5)
 298#define m_INT_EDID_READY		BIT(2)
 299
 300#define HDMI_INTERRUPT_MASK2		0xc2
 301#define HDMI_INTERRUPT_STATUS2		0xc3
 302#define m_INT_HDCP_ERR			BIT(7)
 303#define m_INT_BKSV_FLAG			BIT(6)
 304#define m_INT_HDCP_OK			BIT(4)
 305
 306#define HDMI_STATUS			0xc8
 307#define m_HOTPLUG			BIT(7)
 308#define m_MASK_INT_HOTPLUG		BIT(5)
 309#define m_INT_HOTPLUG			BIT(1)
 310#define v_MASK_INT_HOTPLUG(n)		(((n) & 0x1) << 5)
 311
 312#define HDMI_COLORBAR                   0xc9
 313
 314#define HDMI_PHY_SYNC			0xce
 315#define HDMI_PHY_SYS_CTL		0xe0
 316#define m_TMDS_CLK_SOURCE		BIT(5)
 317#define v_TMDS_FROM_PLL			(0 << 5)
 318#define v_TMDS_FROM_GEN			BIT(5)
 319#define m_PHASE_CLK			BIT(4)
 320#define v_DEFAULT_PHASE			(0 << 4)
 321#define v_SYNC_PHASE			BIT(4)
 322#define m_TMDS_CURRENT_PWR		BIT(3)
 323#define v_TURN_ON_CURRENT		(0 << 3)
 324#define v_CAT_OFF_CURRENT		BIT(3)
 325#define m_BANDGAP_PWR			BIT(2)
 326#define v_BANDGAP_PWR_UP		(0 << 2)
 327#define v_BANDGAP_PWR_DOWN		BIT(2)
 328#define m_PLL_PWR			BIT(1)
 329#define v_PLL_PWR_UP			(0 << 1)
 330#define v_PLL_PWR_DOWN			BIT(1)
 331#define m_TMDS_CHG_PWR			BIT(0)
 332#define v_TMDS_CHG_PWR_UP		(0 << 0)
 333#define v_TMDS_CHG_PWR_DOWN		BIT(0)
 334
 335#define HDMI_PHY_CHG_PWR		0xe1
 336#define v_CLK_CHG_PWR(n)		(((n) & 1) << 3)
 337#define v_DATA_CHG_PWR(n)		(((n) & 7) << 0)
 338
 339#define HDMI_PHY_DRIVER			0xe2
 340#define v_CLK_MAIN_DRIVER(n)		((n) << 4)
 341#define v_DATA_MAIN_DRIVER(n)		((n) << 0)
 342
 343#define HDMI_PHY_PRE_EMPHASIS		0xe3
 344#define v_PRE_EMPHASIS(n)		(((n) & 7) << 4)
 345#define v_CLK_PRE_DRIVER(n)		(((n) & 3) << 2)
 346#define v_DATA_PRE_DRIVER(n)		(((n) & 3) << 0)
 347
 348#define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW		0xe7
 349#define v_FEEDBACK_DIV_LOW(n)			((n) & 0xff)
 350#define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH	0xe8
 351#define v_FEEDBACK_DIV_HIGH(n)			((n) & 1)
 352
 353#define HDMI_PHY_PRE_DIV_RATIO		0xed
 354#define v_PRE_DIV_RATIO(n)		((n) & 0x1f)
 355
 356#define HDMI_CEC_CTRL			0xd0
 357#define m_ADJUST_FOR_HISENSE		BIT(6)
 358#define m_REJECT_RX_BROADCAST		BIT(5)
 359#define m_BUSFREETIME_ENABLE		BIT(2)
 360#define m_REJECT_RX			BIT(1)
 361#define m_START_TX			BIT(0)
 362
 363#define HDMI_CEC_DATA			0xd1
 364#define HDMI_CEC_TX_OFFSET		0xd2
 365#define HDMI_CEC_RX_OFFSET		0xd3
 366#define HDMI_CEC_CLK_H			0xd4
 367#define HDMI_CEC_CLK_L			0xd5
 368#define HDMI_CEC_TX_LENGTH		0xd6
 369#define HDMI_CEC_RX_LENGTH		0xd7
 370#define HDMI_CEC_TX_INT_MASK		0xd8
 371#define m_TX_DONE			BIT(3)
 372#define m_TX_NOACK			BIT(2)
 373#define m_TX_BROADCAST_REJ		BIT(1)
 374#define m_TX_BUSNOTFREE			BIT(0)
 375
 376#define HDMI_CEC_RX_INT_MASK		0xd9
 377#define m_RX_LA_ERR			BIT(4)
 378#define m_RX_GLITCH			BIT(3)
 379#define m_RX_DONE			BIT(0)
 380
 381#define HDMI_CEC_TX_INT			0xda
 382#define HDMI_CEC_RX_INT			0xdb
 383#define HDMI_CEC_BUSFREETIME_L		0xdc
 384#define HDMI_CEC_BUSFREETIME_H		0xdd
 385#define HDMI_CEC_LOGICADDR		0xde
 386
 387#define RK3036_GRF_SOC_CON2	0x148
 388#define RK3036_HDMI_PHSYNC	BIT(4)
 389#define RK3036_HDMI_PVSYNC	BIT(5)
 390
 391enum inno_hdmi_dev_type {
 392	RK3036_HDMI,
 393	RK3128_HDMI,
 394};
 395
 396struct inno_hdmi_phy_config {
 397	unsigned long pixelclock;
 398	u8 pre_emphasis;
 399	u8 voltage_level_control;
 400};
 401
 402struct inno_hdmi_variant {
 403	enum inno_hdmi_dev_type dev_type;
 404	struct inno_hdmi_phy_config *phy_configs;
 405	struct inno_hdmi_phy_config *default_phy_config;
 406};
 407
 408struct inno_hdmi_i2c {
 409	struct i2c_adapter adap;
 410
 411	u8 ddc_addr;
 412	u8 segment_addr;
 413
 414	struct mutex lock;
 415	struct completion cmp;
 416};
 417
 418struct inno_hdmi {
 419	struct device *dev;
 420
 421	struct clk *pclk;
 422	struct clk *refclk;
 423	void __iomem *regs;
 424	struct regmap *grf;
 425
 426	struct drm_connector	connector;
 427	struct rockchip_encoder	encoder;
 428
 429	struct inno_hdmi_i2c *i2c;
 430	struct i2c_adapter *ddc;
 431
 432	const struct inno_hdmi_variant *variant;
 433};
 434
 435struct inno_hdmi_connector_state {
 436	struct drm_connector_state	base;
 437	unsigned int			colorimetry;
 438};
 439
 440static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
 441{
 442	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
 443
 444	return container_of(rkencoder, struct inno_hdmi, encoder);
 445}
 446
 447static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
 448{
 449	return container_of(connector, struct inno_hdmi, connector);
 450}
 451
 452#define to_inno_hdmi_conn_state(conn_state) \
 453	container_of_const(conn_state, struct inno_hdmi_connector_state, base)
 454
 455enum {
 456	CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
 457	CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
 458	CSC_RGB_0_255_TO_RGB_16_235_8BIT,
 459};
 460
 461static const char coeff_csc[][24] = {
 462	/*
 463	 * RGB2YUV:601 SD mode:
 464	 *   Cb = -0.291G - 0.148R + 0.439B + 128
 465	 *   Y  = 0.504G  + 0.257R + 0.098B + 16
 466	 *   Cr = -0.368G + 0.439R - 0.071B + 128
 467	 */
 468	{
 469		0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
 470		0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
 471		0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
 472	},
 473	/*
 474	 * RGB2YUV:709 HD mode:
 475	 *   Cb = - 0.338G - 0.101R + 0.439B + 128
 476	 *   Y  = 0.614G   + 0.183R + 0.062B + 16
 477	 *   Cr = - 0.399G + 0.439R - 0.040B + 128
 478	 */
 479	{
 480		0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
 481		0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
 482		0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
 483	},
 484	/*
 485	 * RGB[0:255]2RGB[16:235]:
 486	 *   R' = R x (235-16)/255 + 16;
 487	 *   G' = G x (235-16)/255 + 16;
 488	 *   B' = B x (235-16)/255 + 16;
 489	 */
 490	{
 491		0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
 492		0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
 493		0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
 494	},
 495};
 496
 497static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
 498	{  74250000, 0x3f, 0xbb },
 499	{ 165000000, 0x6f, 0xbb },
 500	{      ~0UL, 0x00, 0x00 }
 501};
 502
 503static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
 504	{  74250000, 0x3f, 0xaa },
 505	{ 165000000, 0x5f, 0xaa },
 506	{      ~0UL, 0x00, 0x00 }
 507};
 508
 509static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
 510				     unsigned long pixelclk)
 511{
 512	const struct inno_hdmi_phy_config *phy_configs =
 513						hdmi->variant->phy_configs;
 514	int i;
 515
 516	for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
 517		if (pixelclk <= phy_configs[i].pixelclock)
 518			return i;
 519	}
 520
 521	DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
 522		      pixelclk);
 523
 524	return -EINVAL;
 525}
 526
 527static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
 528{
 529	return readl_relaxed(hdmi->regs + (offset) * 0x04);
 530}
 531
 532static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
 533{
 534	writel_relaxed(val, hdmi->regs + (offset) * 0x04);
 535}
 536
 537static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
 538			     u32 msk, u32 val)
 539{
 540	u8 temp = hdmi_readb(hdmi, offset) & ~msk;
 541
 542	temp |= val & msk;
 543	hdmi_writeb(hdmi, offset, temp);
 544}
 545
 546static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate)
 547{
 548	unsigned long long ddc_bus_freq = rate >> 2;
 549
 550	do_div(ddc_bus_freq, HDMI_SCL_RATE);
 551
 552	hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
 553	hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
 554
 555	/* Clear the EDID interrupt flag and mute the interrupt */
 556	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
 557	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
 558}
 559
 560static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
 561{
 562	if (enable)
 563		hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
 564	else
 565		hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
 566}
 567
 568static void inno_hdmi_standby(struct inno_hdmi *hdmi)
 569{
 570	inno_hdmi_sys_power(hdmi, false);
 571
 572	hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
 573	hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
 574	hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
 575	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
 576};
 577
 578static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
 579			       unsigned long mpixelclock)
 580{
 581	struct inno_hdmi_phy_config *phy_config;
 582	int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
 583
 584	if (ret < 0) {
 585		phy_config = hdmi->variant->default_phy_config;
 586		DRM_DEV_ERROR(hdmi->dev,
 587			      "Using default phy configuration for TMDS rate %lu",
 588			      mpixelclock);
 589	} else {
 590		phy_config = &hdmi->variant->phy_configs[ret];
 591	}
 592
 593	inno_hdmi_sys_power(hdmi, false);
 594
 595	hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
 596	hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
 597	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
 598	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
 599	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
 600	hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
 601	hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
 602	hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
 603
 604	inno_hdmi_sys_power(hdmi, true);
 605};
 606
 607static void inno_hdmi_init_hw(struct inno_hdmi *hdmi)
 608{
 609	u32 val;
 610	u32 msk;
 611
 612	hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
 613	usleep_range(100, 150);
 614
 615	hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
 616	usleep_range(100, 150);
 617
 618	msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
 619	val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
 620	hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
 621
 622	inno_hdmi_standby(hdmi);
 623
 624	/*
 625	 * When the controller isn't configured to an accurate
 626	 * video timing and there is no reference clock available,
 627	 * then the TMDS clock source would be switched to PCLK_HDMI,
 628	 * so we need to init the TMDS rate to PCLK rate, and
 629	 * reconfigure the DDC clock.
 630	 */
 631	if (hdmi->refclk)
 632		inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk));
 633	else
 634		inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk));
 635
 636	/* Unmute hotplug interrupt */
 637	hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
 638}
 639
 640static int inno_hdmi_disable_frame(struct drm_connector *connector,
 641				   enum hdmi_infoframe_type type)
 642{
 643	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
 644
 645	if (type != HDMI_INFOFRAME_TYPE_AVI) {
 646		drm_err(connector->dev,
 647			"Unsupported infoframe type: %u\n", type);
 648		return 0;
 649	}
 650
 651	hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI);
 652
 653	return 0;
 654}
 655
 656static int inno_hdmi_upload_frame(struct drm_connector *connector,
 657				  enum hdmi_infoframe_type type,
 658				  const u8 *buffer, size_t len)
 659{
 660	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
 661	ssize_t i;
 662
 663	if (type != HDMI_INFOFRAME_TYPE_AVI) {
 664		drm_err(connector->dev,
 665			"Unsupported infoframe type: %u\n", type);
 666		return 0;
 667	}
 668
 669	inno_hdmi_disable_frame(connector, type);
 670
 671	for (i = 0; i < len; i++)
 672		hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, buffer[i]);
 673
 674	return 0;
 675}
 676
 677static const struct drm_connector_hdmi_funcs inno_hdmi_hdmi_connector_funcs = {
 678	.clear_infoframe	= inno_hdmi_disable_frame,
 679	.write_infoframe	= inno_hdmi_upload_frame,
 680};
 681
 682static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
 683{
 684	struct drm_connector *connector = &hdmi->connector;
 685	struct drm_connector_state *conn_state = connector->state;
 686	struct inno_hdmi_connector_state *inno_conn_state =
 687					to_inno_hdmi_conn_state(conn_state);
 688	int c0_c2_change = 0;
 689	int csc_enable = 0;
 690	int csc_mode = 0;
 691	int auto_csc = 0;
 692	int value;
 693	int i;
 694
 695	/* Input video mode is SDR RGB24bit, data enable signal from external */
 696	hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
 697		    v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
 698
 699	/* Input color hardcode to RGB, and output color hardcode to RGB888 */
 700	value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
 701		v_VIDEO_OUTPUT_COLOR(0) |
 702		v_VIDEO_INPUT_CSP(0);
 703	hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
 704
 705	if (conn_state->hdmi.output_format == HDMI_COLORSPACE_RGB) {
 706		if (conn_state->hdmi.is_limited_range) {
 707			csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
 708			auto_csc = AUTO_CSC_DISABLE;
 709			c0_c2_change = C0_C2_CHANGE_DISABLE;
 710			csc_enable = v_CSC_ENABLE;
 711
 712		} else {
 713			value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
 714			hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
 715
 716			hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
 717				  m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
 718				  v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
 719				  v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
 720			return 0;
 721		}
 722	} else {
 723		if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
 724			if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) {
 725				csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
 726				auto_csc = AUTO_CSC_DISABLE;
 727				c0_c2_change = C0_C2_CHANGE_DISABLE;
 728				csc_enable = v_CSC_ENABLE;
 729			}
 730		} else {
 731			if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) {
 732				csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
 733				auto_csc = AUTO_CSC_DISABLE;
 734				c0_c2_change = C0_C2_CHANGE_DISABLE;
 735				csc_enable = v_CSC_ENABLE;
 736			}
 737		}
 738	}
 739
 740	for (i = 0; i < 24; i++)
 741		hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
 742			    coeff_csc[csc_mode][i]);
 743
 744	value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
 745	hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
 746	hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
 747		  m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
 748		  v_VIDEO_C0_C2_SWAP(c0_c2_change));
 749
 750	return 0;
 751}
 752
 753static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
 754					 struct drm_display_mode *mode)
 755{
 756	int value, psync;
 757
 758	if (hdmi->variant->dev_type == RK3036_HDMI) {
 759		psync = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 : 0;
 760		value = FIELD_PREP_WM16(RK3036_HDMI_PHSYNC, psync);
 761		psync = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 : 0;
 762		value |= FIELD_PREP_WM16(RK3036_HDMI_PVSYNC, psync);
 763		regmap_write(hdmi->grf, RK3036_GRF_SOC_CON2, value);
 764	}
 765
 766	/* Set detail external video timing polarity and interlace mode */
 767	value = v_EXTERANL_VIDEO(1);
 768	value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
 769		 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
 770	value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
 771		 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
 772	value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
 773		 v_INETLACE(1) : v_INETLACE(0);
 774	hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
 775
 776	/* Set detail external video timing */
 777	value = mode->htotal;
 778	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
 779	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
 780
 781	value = mode->htotal - mode->hdisplay;
 782	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
 783	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
 784
 785	value = mode->htotal - mode->hsync_start;
 786	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
 787	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
 788
 789	value = mode->hsync_end - mode->hsync_start;
 790	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
 791	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
 792
 793	value = mode->vtotal;
 794	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
 795	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
 796
 797	value = mode->vtotal - mode->vdisplay;
 798	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
 799
 800	value = mode->vtotal - mode->vsync_start;
 801	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
 802
 803	value = mode->vsync_end - mode->vsync_start;
 804	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
 805
 806	hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
 807	hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
 808	hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
 809
 810	return 0;
 811}
 812
 813static int inno_hdmi_setup(struct inno_hdmi *hdmi,
 814			   struct drm_atomic_state *state)
 815{
 816	struct drm_connector *connector = &hdmi->connector;
 817	struct drm_display_info *display = &connector->display_info;
 818	struct drm_connector_state *new_conn_state;
 819	struct drm_crtc_state *new_crtc_state;
 820
 821	new_conn_state = drm_atomic_get_new_connector_state(state, connector);
 822	if (WARN_ON(!new_conn_state))
 823		return -EINVAL;
 824
 825	new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 826	if (WARN_ON(!new_crtc_state))
 827		return -EINVAL;
 828
 829	/* Mute video and audio output */
 830	hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
 831		  v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
 832
 833	/* Set HDMI Mode */
 834	hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
 835		    v_HDMI_DVI(display->is_hdmi));
 836
 837	inno_hdmi_config_video_timing(hdmi, &new_crtc_state->adjusted_mode);
 838
 839	inno_hdmi_config_video_csc(hdmi);
 840
 841	drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
 842
 843	/*
 844	 * When IP controller have configured to an accurate video
 845	 * timing, then the TMDS clock source would be switched to
 846	 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
 847	 * clock rate, and reconfigure the DDC clock.
 848	 */
 849	inno_hdmi_i2c_init(hdmi, new_conn_state->hdmi.tmds_char_rate);
 850
 851	/* Unmute video and audio output */
 852	hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
 853		  v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
 854
 855	inno_hdmi_power_up(hdmi, new_conn_state->hdmi.tmds_char_rate);
 856
 857	return 0;
 858}
 859
 860static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi,
 861							 const struct drm_display_mode *mode)
 862{
 863	unsigned long mpixelclk, max_tolerance;
 864	long rounded_refclk;
 865
 866	/* No support for double-clock modes */
 867	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 868		return MODE_BAD;
 869
 870	mpixelclk = mode->clock * 1000;
 871
 872	if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK)
 873		return MODE_CLOCK_LOW;
 874
 875	if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0)
 876		return MODE_CLOCK_HIGH;
 877
 878	if (hdmi->refclk) {
 879		rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk);
 880		if (rounded_refclk < 0)
 881			return MODE_BAD;
 882
 883		/* Vesa DMT standard mentions +/- 0.5% max tolerance */
 884		max_tolerance = mpixelclk / 200;
 885		if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance)
 886			return MODE_NOCLOCK;
 887	}
 888
 889	return MODE_OK;
 890}
 891
 892static void inno_hdmi_encoder_enable(struct drm_encoder *encoder,
 893				     struct drm_atomic_state *state)
 894{
 895	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
 896
 897	inno_hdmi_setup(hdmi, state);
 898}
 899
 900static void inno_hdmi_encoder_disable(struct drm_encoder *encoder,
 901				      struct drm_atomic_state *state)
 902{
 903	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
 904
 905	inno_hdmi_standby(hdmi);
 906}
 907
 908static int
 909inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 910			       struct drm_crtc_state *crtc_state,
 911			       struct drm_connector_state *conn_state)
 912{
 913	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 914	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 915	u8 vic = drm_match_cea_mode(mode);
 916	struct inno_hdmi_connector_state *inno_conn_state =
 917					to_inno_hdmi_conn_state(conn_state);
 918
 919	s->output_mode = ROCKCHIP_OUT_MODE_P888;
 920	s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 921
 922	if (vic == 6 || vic == 7 ||
 923	    vic == 21 || vic == 22 ||
 924	    vic == 2 || vic == 3 ||
 925	    vic == 17 || vic == 18)
 926		inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601;
 927	else
 928		inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
 929
 930	return 0;
 931}
 932
 933static const struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
 934	.atomic_check	= inno_hdmi_encoder_atomic_check,
 935	.atomic_enable	= inno_hdmi_encoder_enable,
 936	.atomic_disable	= inno_hdmi_encoder_disable,
 937};
 938
 939static enum drm_connector_status
 940inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
 941{
 942	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
 943
 944	return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
 945		connector_status_connected : connector_status_disconnected;
 946}
 947
 948static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
 949{
 950	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
 951	const struct drm_edid *drm_edid;
 952	int ret = 0;
 953
 954	if (!hdmi->ddc)
 955		return 0;
 956
 957	drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
 958	drm_edid_connector_update(connector, drm_edid);
 959	ret = drm_edid_connector_add_modes(connector);
 960	drm_edid_free(drm_edid);
 961
 962	return ret;
 963}
 964
 965static enum drm_mode_status
 966inno_hdmi_connector_mode_valid(struct drm_connector *connector,
 967			       const struct drm_display_mode *mode)
 968{
 969	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
 970
 971	return  inno_hdmi_display_mode_valid(hdmi, mode);
 972}
 973
 974static void
 975inno_hdmi_connector_destroy_state(struct drm_connector *connector,
 976				  struct drm_connector_state *state)
 977{
 978	struct inno_hdmi_connector_state *inno_conn_state =
 979						to_inno_hdmi_conn_state(state);
 980
 981	__drm_atomic_helper_connector_destroy_state(&inno_conn_state->base);
 982	kfree(inno_conn_state);
 983}
 984
 985static void inno_hdmi_connector_reset(struct drm_connector *connector)
 986{
 987	struct inno_hdmi_connector_state *inno_conn_state;
 988
 989	if (connector->state) {
 990		inno_hdmi_connector_destroy_state(connector, connector->state);
 991		connector->state = NULL;
 992	}
 993
 994	inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL);
 995	if (!inno_conn_state)
 996		return;
 997
 998	__drm_atomic_helper_connector_reset(connector, &inno_conn_state->base);
 999	__drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
1000
1001	inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
1002}
1003
1004static struct drm_connector_state *
1005inno_hdmi_connector_duplicate_state(struct drm_connector *connector)
1006{
1007	struct inno_hdmi_connector_state *inno_conn_state;
1008
1009	if (WARN_ON(!connector->state))
1010		return NULL;
1011
1012	inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state),
1013				  sizeof(*inno_conn_state), GFP_KERNEL);
1014
1015	if (!inno_conn_state)
1016		return NULL;
1017
1018	__drm_atomic_helper_connector_duplicate_state(connector,
1019						      &inno_conn_state->base);
1020
1021	return &inno_conn_state->base;
1022}
1023
1024static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
1025	.fill_modes = drm_helper_probe_single_connector_modes,
1026	.detect = inno_hdmi_connector_detect,
1027	.reset = inno_hdmi_connector_reset,
1028	.atomic_duplicate_state = inno_hdmi_connector_duplicate_state,
1029	.atomic_destroy_state = inno_hdmi_connector_destroy_state,
1030};
1031
1032static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
1033	.atomic_check = drm_atomic_helper_connector_hdmi_check,
1034	.get_modes = inno_hdmi_connector_get_modes,
1035	.mode_valid = inno_hdmi_connector_mode_valid,
1036};
1037
1038static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
1039{
1040	struct drm_encoder *encoder = &hdmi->encoder.encoder;
1041	struct device *dev = hdmi->dev;
1042
1043	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1044
1045	/*
1046	 * If we failed to find the CRTC(s) which this encoder is
1047	 * supposed to be connected to, it's because the CRTC has
1048	 * not been registered yet.  Defer probing, and hope that
1049	 * the required CRTC is added later.
1050	 */
1051	if (encoder->possible_crtcs == 0)
1052		return -EPROBE_DEFER;
1053
1054	drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
1055	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
1056
1057	hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1058
1059	drm_connector_helper_add(&hdmi->connector,
1060				 &inno_hdmi_connector_helper_funcs);
1061	drmm_connector_hdmi_init(drm, &hdmi->connector,
1062				 "Rockchip", "Inno HDMI",
1063				 &inno_hdmi_connector_funcs,
1064				 &inno_hdmi_hdmi_connector_funcs,
1065				 DRM_MODE_CONNECTOR_HDMIA,
1066				 hdmi->ddc,
1067				 BIT(HDMI_COLORSPACE_RGB),
1068				 8);
1069
1070	drm_connector_attach_encoder(&hdmi->connector, encoder);
1071
1072	return 0;
1073}
1074
1075static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
1076{
1077	struct inno_hdmi_i2c *i2c = hdmi->i2c;
1078	u8 stat;
1079
1080	stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
1081	if (!(stat & m_INT_EDID_READY))
1082		return IRQ_NONE;
1083
1084	/* Clear HDMI EDID interrupt flag */
1085	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
1086
1087	complete(&i2c->cmp);
1088
1089	return IRQ_HANDLED;
1090}
1091
1092static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
1093{
1094	struct inno_hdmi *hdmi = dev_id;
1095	irqreturn_t ret = IRQ_NONE;
1096	u8 interrupt;
1097
1098	if (hdmi->i2c)
1099		ret = inno_hdmi_i2c_irq(hdmi);
1100
1101	interrupt = hdmi_readb(hdmi, HDMI_STATUS);
1102	if (interrupt & m_INT_HOTPLUG) {
1103		hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
1104		ret = IRQ_WAKE_THREAD;
1105	}
1106
1107	return ret;
1108}
1109
1110static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
1111{
1112	struct inno_hdmi *hdmi = dev_id;
1113
1114	drm_helper_hpd_irq_event(hdmi->connector.dev);
1115
1116	return IRQ_HANDLED;
1117}
1118
1119static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
1120{
1121	int length = msgs->len;
1122	u8 *buf = msgs->buf;
1123	int ret;
1124
1125	ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
1126	if (!ret)
1127		return -EAGAIN;
1128
1129	while (length--)
1130		*buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
1131
1132	return 0;
1133}
1134
1135static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
1136{
1137	/*
1138	 * The DDC module only support read EDID message, so
1139	 * we assume that each word write to this i2c adapter
1140	 * should be the offset of EDID word address.
1141	 */
1142	if (msgs->len != 1 || (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
1143		return -EINVAL;
1144
1145	reinit_completion(&hdmi->i2c->cmp);
1146
1147	if (msgs->addr == DDC_SEGMENT_ADDR)
1148		hdmi->i2c->segment_addr = msgs->buf[0];
1149	if (msgs->addr == DDC_ADDR)
1150		hdmi->i2c->ddc_addr = msgs->buf[0];
1151
1152	/* Set edid fifo first addr */
1153	hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
1154
1155	/* Set edid word address 0x00/0x80 */
1156	hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
1157
1158	/* Set edid segment pointer */
1159	hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
1160
1161	return 0;
1162}
1163
1164static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
1165			      struct i2c_msg *msgs, int num)
1166{
1167	struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
1168	struct inno_hdmi_i2c *i2c = hdmi->i2c;
1169	int i, ret = 0;
1170
1171	mutex_lock(&i2c->lock);
1172
1173	/* Clear the EDID interrupt flag and unmute the interrupt */
1174	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
1175	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
1176
1177	for (i = 0; i < num; i++) {
1178		DRM_DEV_DEBUG(hdmi->dev,
1179			      "xfer: num: %d/%d, len: %d, flags: %#x\n",
1180			      i + 1, num, msgs[i].len, msgs[i].flags);
1181
1182		if (msgs[i].flags & I2C_M_RD)
1183			ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
1184		else
1185			ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
1186
1187		if (ret < 0)
1188			break;
1189	}
1190
1191	if (!ret)
1192		ret = num;
1193
1194	/* Mute HDMI EDID interrupt */
1195	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
1196
1197	mutex_unlock(&i2c->lock);
1198
1199	return ret;
1200}
1201
1202static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
1203{
1204	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1205}
1206
1207static const struct i2c_algorithm inno_hdmi_algorithm = {
1208	.master_xfer	= inno_hdmi_i2c_xfer,
1209	.functionality	= inno_hdmi_i2c_func,
1210};
1211
1212static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
1213{
1214	struct i2c_adapter *adap;
1215	struct inno_hdmi_i2c *i2c;
1216	int ret;
1217
1218	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
1219	if (!i2c)
1220		return ERR_PTR(-ENOMEM);
1221
1222	mutex_init(&i2c->lock);
1223	init_completion(&i2c->cmp);
1224
1225	adap = &i2c->adap;
1226	adap->owner = THIS_MODULE;
1227	adap->dev.parent = hdmi->dev;
1228	adap->dev.of_node = hdmi->dev->of_node;
1229	adap->algo = &inno_hdmi_algorithm;
1230	strscpy(adap->name, "Inno HDMI", sizeof(adap->name));
1231	i2c_set_adapdata(adap, hdmi);
1232
1233	ret = devm_i2c_add_adapter(hdmi->dev, adap);
1234	if (ret) {
1235		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
1236		return ERR_PTR(ret);
1237	}
1238
1239	hdmi->i2c = i2c;
1240
1241	DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
1242
1243	return adap;
1244}
1245
1246static int inno_hdmi_bind(struct device *dev, struct device *master,
1247				 void *data)
1248{
1249	struct platform_device *pdev = to_platform_device(dev);
1250	struct drm_device *drm = data;
1251	struct inno_hdmi *hdmi;
1252	const struct inno_hdmi_variant *variant;
1253	int irq;
1254	int ret;
1255
1256	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1257	if (!hdmi)
1258		return -ENOMEM;
1259
1260	hdmi->dev = dev;
1261
1262	variant = of_device_get_match_data(hdmi->dev);
1263	if (!variant)
1264		return -EINVAL;
1265
1266	hdmi->variant = variant;
1267
1268	hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
1269	if (IS_ERR(hdmi->regs))
1270		return PTR_ERR(hdmi->regs);
1271
1272	hdmi->pclk = devm_clk_get_enabled(hdmi->dev, "pclk");
1273	if (IS_ERR(hdmi->pclk))
1274		return dev_err_probe(dev, PTR_ERR(hdmi->pclk), "Unable to get HDMI pclk\n");
1275
1276	hdmi->refclk = devm_clk_get_optional_enabled(hdmi->dev, "ref");
1277	if (IS_ERR(hdmi->refclk))
1278		return dev_err_probe(dev, PTR_ERR(hdmi->refclk), "Unable to get HDMI refclk\n");
1279
1280	if (hdmi->variant->dev_type == RK3036_HDMI) {
1281		hdmi->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
1282		if (IS_ERR(hdmi->grf))
1283			return dev_err_probe(dev,
1284					     PTR_ERR(hdmi->grf), "Unable to get rockchip,grf\n");
1285	}
1286
1287	irq = platform_get_irq(pdev, 0);
1288	if (irq < 0)
1289		return irq;
1290
1291	inno_hdmi_init_hw(hdmi);
1292
1293	hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
1294	if (IS_ERR(hdmi->ddc))
1295		return PTR_ERR(hdmi->ddc);
1296
1297	ret = inno_hdmi_register(drm, hdmi);
1298	if (ret)
1299		return ret;
1300
1301	dev_set_drvdata(dev, hdmi);
1302
1303	ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
1304					inno_hdmi_irq, IRQF_SHARED,
1305					dev_name(dev), hdmi);
1306	if (ret < 0)
1307		goto err_cleanup_hdmi;
1308
1309	return 0;
1310err_cleanup_hdmi:
1311	hdmi->connector.funcs->destroy(&hdmi->connector);
1312	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
1313	return ret;
1314}
1315
1316static void inno_hdmi_unbind(struct device *dev, struct device *master,
1317			     void *data)
1318{
1319	struct inno_hdmi *hdmi = dev_get_drvdata(dev);
1320
1321	hdmi->connector.funcs->destroy(&hdmi->connector);
1322	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
1323}
1324
1325static const struct component_ops inno_hdmi_ops = {
1326	.bind	= inno_hdmi_bind,
1327	.unbind	= inno_hdmi_unbind,
1328};
1329
1330static int inno_hdmi_probe(struct platform_device *pdev)
1331{
1332	return component_add(&pdev->dev, &inno_hdmi_ops);
1333}
1334
1335static void inno_hdmi_remove(struct platform_device *pdev)
1336{
1337	component_del(&pdev->dev, &inno_hdmi_ops);
1338}
1339
1340static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = {
1341	.dev_type = RK3036_HDMI,
1342	.phy_configs = rk3036_hdmi_phy_configs,
1343	.default_phy_config = &rk3036_hdmi_phy_configs[1],
1344};
1345
1346static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = {
1347	.dev_type = RK3128_HDMI,
1348	.phy_configs = rk3128_hdmi_phy_configs,
1349	.default_phy_config = &rk3128_hdmi_phy_configs[1],
1350};
1351
1352static const struct of_device_id inno_hdmi_dt_ids[] = {
1353	{ .compatible = "rockchip,rk3036-inno-hdmi",
1354	  .data = &rk3036_inno_hdmi_variant,
1355	},
1356	{ .compatible = "rockchip,rk3128-inno-hdmi",
1357	  .data = &rk3128_inno_hdmi_variant,
1358	},
1359	{},
1360};
1361MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
1362
1363struct platform_driver inno_hdmi_driver = {
1364	.probe  = inno_hdmi_probe,
1365	.remove = inno_hdmi_remove,
1366	.driver = {
1367		.name = "innohdmi-rockchip",
1368		.of_match_table = inno_hdmi_dt_ids,
1369	},
1370};