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dw-mipi-dsi-rockchip.c
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linux-6.19.14/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9#include <linux/clk.h> 10#include <linux/hw_bitfield.h> 11#include <linux/iopoll.h> 12#include <linux/math64.h> 13#include <linux/mfd/syscon.h> 14#include <linux/module.h> 15#include <linux/of_device.h> 16#include <linux/of_platform.h> 17#include <linux/phy/phy.h> 18#include <linux/platform_device.h> 19#include <linux/pm_runtime.h> 20#include <linux/regmap.h> 21 22#include <video/mipi_display.h> 23 24#include <drm/bridge/dw_mipi_dsi.h> 25#include <drm/drm_mipi_dsi.h> 26#include <drm/drm_of.h> 27#include <drm/drm_print.h> 28#include <drm/drm_simple_kms_helper.h> 29 30#include "rockchip_drm_drv.h" 31 32#define DSI_PHY_RSTZ 0xa0 33#define PHY_DISFORCEPLL 0 34#define PHY_ENFORCEPLL BIT(3) 35#define PHY_DISABLECLK 0 36#define PHY_ENABLECLK BIT(2) 37#define PHY_RSTZ 0 38#define PHY_UNRSTZ BIT(1) 39#define PHY_SHUTDOWNZ 0 40#define PHY_UNSHUTDOWNZ BIT(0) 41 42#define DSI_PHY_IF_CFG 0xa4 43#define N_LANES(n) ((((n) - 1) & 0x3) << 0) 44#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 45 46#define DSI_PHY_STATUS 0xb0 47#define LOCK BIT(0) 48#define STOP_STATE_CLK_LANE BIT(2) 49 50#define DSI_PHY_TST_CTRL0 0xb4 51#define PHY_TESTCLK BIT(1) 52#define PHY_UNTESTCLK 0 53#define PHY_TESTCLR BIT(0) 54#define PHY_UNTESTCLR 0 55 56#define DSI_PHY_TST_CTRL1 0xb8 57#define PHY_TESTEN BIT(16) 58#define PHY_UNTESTEN 0 59#define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 60#define PHY_TESTDIN(n) (((n) & 0xff) << 0) 61 62#define DSI_INT_ST0 0xbc 63#define DSI_INT_ST1 0xc0 64#define DSI_INT_MSK0 0xc4 65#define DSI_INT_MSK1 0xc8 66 67#define PHY_STATUS_TIMEOUT_US 10000 68#define CMD_PKT_STATUS_TIMEOUT_US 20000 69 70#define BYPASS_VCO_RANGE BIT(7) 71#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 72#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 73#define VCO_IN_CAP_CON_LOW (0x1 << 1) 74#define VCO_IN_CAP_CON_HIGH (0x2 << 1) 75#define REF_BIAS_CUR_SEL BIT(0) 76 77#define CP_CURRENT_3UA 0x1 78#define CP_CURRENT_4_5UA 0x2 79#define CP_CURRENT_7_5UA 0x6 80#define CP_CURRENT_6UA 0x9 81#define CP_CURRENT_12UA 0xb 82#define CP_CURRENT_SEL(val) ((val) & 0xf) 83#define CP_PROGRAM_EN BIT(7) 84 85#define LPF_RESISTORS_15_5KOHM 0x1 86#define LPF_RESISTORS_13KOHM 0x2 87#define LPF_RESISTORS_11_5KOHM 0x4 88#define LPF_RESISTORS_10_5KOHM 0x8 89#define LPF_RESISTORS_8KOHM 0x10 90#define LPF_PROGRAM_EN BIT(6) 91#define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 92 93#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 94 95#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 96#define LOW_PROGRAM_EN 0 97#define HIGH_PROGRAM_EN BIT(7) 98#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 99#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 100#define PLL_LOOP_DIV_EN BIT(5) 101#define PLL_INPUT_DIV_EN BIT(4) 102 103#define POWER_CONTROL BIT(6) 104#define INTERNAL_REG_CURRENT BIT(3) 105#define BIAS_BLOCK_ON BIT(2) 106#define BANDGAP_ON BIT(0) 107 108#define TER_RESISTOR_HIGH BIT(7) 109#define TER_RESISTOR_LOW 0 110#define LEVEL_SHIFTERS_ON BIT(6) 111#define TER_CAL_DONE BIT(5) 112#define SETRD_MAX (0x7 << 2) 113#define POWER_MANAGE BIT(1) 114#define TER_RESISTORS_ON BIT(0) 115 116#define BIASEXTR_SEL(val) ((val) & 0x7) 117#define BANDGAP_SEL(val) ((val) & 0x7) 118#define TLP_PROGRAM_EN BIT(7) 119#define THS_PRE_PROGRAM_EN BIT(7) 120#define THS_ZERO_PROGRAM_EN BIT(6) 121 122#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 123#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 124#define PLL_LPF_AND_CP_CONTROL 0x12 125#define PLL_INPUT_DIVIDER_RATIO 0x17 126#define PLL_LOOP_DIVIDER_RATIO 0x18 127#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 128#define BANDGAP_AND_BIAS_CONTROL 0x20 129#define TERMINATION_RESISTER_CONTROL 0x21 130#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 131#define HS_RX_CONTROL_OF_LANE_CLK 0x34 132#define HS_RX_CONTROL_OF_LANE_0 0x44 133#define HS_RX_CONTROL_OF_LANE_1 0x54 134#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 135#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 136#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 137#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 138#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 139#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 140#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 141#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 142#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 143#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 144#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 145#define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 146#define HS_RX_CONTROL_OF_LANE_2 0x84 147#define HS_RX_CONTROL_OF_LANE_3 0x94 148 149#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 150#define DW_MIPI_NEEDS_GRF_CLK BIT(1) 151 152#define PX30_GRF_PD_VO_CON1 0x0438 153#define PX30_DSI_FORCETXSTOPMODE (0xfUL << 7) 154#define PX30_DSI_FORCERXMODE BIT(6) 155#define PX30_DSI_TURNDISABLE BIT(5) 156#define PX30_DSI_LCDC_SEL BIT(0) 157 158#define RK3128_GRF_LVDS_CON0 0x0150 159#define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10) 160#define RK3128_DSI_FORCERXMODE BIT(9) 161#define RK3128_DSI_TURNDISABLE BIT(8) 162 163#define RK3288_GRF_SOC_CON6 0x025c 164#define RK3288_DSI0_LCDC_SEL BIT(6) 165#define RK3288_DSI1_LCDC_SEL BIT(9) 166 167#define RK3368_GRF_SOC_CON7 0x41c 168#define RK3368_DSI_FORCETXSTOPMODE (0xf << 7) 169#define RK3368_DSI_FORCERXMODE BIT(6) 170#define RK3368_DSI_TURNDISABLE BIT(5) 171 172#define RK3399_GRF_SOC_CON20 0x6250 173#define RK3399_DSI0_LCDC_SEL BIT(0) 174#define RK3399_DSI1_LCDC_SEL BIT(4) 175 176#define RK3399_GRF_SOC_CON22 0x6258 177#define RK3399_DSI0_TURNREQUEST (0xfUL << 12) 178#define RK3399_DSI0_TURNDISABLE (0xfUL << 8) 179#define RK3399_DSI0_FORCETXSTOPMODE (0xfUL << 4) 180#define RK3399_DSI0_FORCERXMODE (0xfUL << 0) 181 182#define RK3399_GRF_SOC_CON23 0x625c 183#define RK3399_DSI1_TURNDISABLE (0xfUL << 12) 184#define RK3399_DSI1_FORCETXSTOPMODE (0xfUL << 8) 185#define RK3399_DSI1_FORCERXMODE (0xfUL << 4) 186#define RK3399_DSI1_ENABLE (0xfUL << 0) 187 188#define RK3399_GRF_SOC_CON24 0x6260 189#define RK3399_TXRX_MASTERSLAVEZ BIT(7) 190#define RK3399_TXRX_ENABLECLK BIT(6) 191#define RK3399_TXRX_BASEDIR BIT(5) 192#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 193#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 194 195#define RK3568_GRF_VO_CON2 0x0368 196#define RK3568_DSI0_SKEWCALHS (0x1fUL << 11) 197#define RK3568_DSI0_FORCETXSTOPMODE (0xfUL << 4) 198#define RK3568_DSI0_TURNDISABLE BIT(2) 199#define RK3568_DSI0_FORCERXMODE BIT(0) 200 201/* 202 * Note these registers do not appear in the datasheet, they are 203 * however present in the BSP driver which is where these values 204 * come from. Name GRF_VO_CON3 is assumed. 205 */ 206#define RK3568_GRF_VO_CON3 0x36c 207#define RK3568_DSI1_SKEWCALHS (0x1fUL << 11) 208#define RK3568_DSI1_FORCETXSTOPMODE (0xfUL << 4) 209#define RK3568_DSI1_TURNDISABLE BIT(2) 210#define RK3568_DSI1_FORCERXMODE BIT(0) 211 212#define RV1126_GRF_DSIPHY_CON 0x10220 213#define RV1126_DSI_FORCETXSTOPMODE (0xfUL << 4) 214#define RV1126_DSI_TURNDISABLE BIT(2) 215#define RV1126_DSI_FORCERXMODE BIT(0) 216 217enum { 218 DW_DSI_USAGE_IDLE, 219 DW_DSI_USAGE_DSI, 220 DW_DSI_USAGE_PHY, 221}; 222 223enum { 224 BANDGAP_97_07, 225 BANDGAP_98_05, 226 BANDGAP_99_02, 227 BANDGAP_100_00, 228 BANDGAP_93_17, 229 BANDGAP_94_15, 230 BANDGAP_95_12, 231 BANDGAP_96_10, 232}; 233 234enum { 235 BIASEXTR_87_1, 236 BIASEXTR_91_5, 237 BIASEXTR_95_9, 238 BIASEXTR_100, 239 BIASEXTR_105_94, 240 BIASEXTR_111_88, 241 BIASEXTR_118_8, 242 BIASEXTR_127_7, 243}; 244 245struct rockchip_dw_dsi_chip_data { 246 u32 reg; 247 248 u32 lcdsel_grf_reg; 249 u32 lcdsel_big; 250 u32 lcdsel_lit; 251 252 u32 enable_grf_reg; 253 u32 enable; 254 255 u32 lanecfg1_grf_reg; 256 u32 lanecfg1; 257 u32 lanecfg2_grf_reg; 258 u32 lanecfg2; 259 260 int (*dphy_rx_init)(struct phy *phy); 261 int (*dphy_rx_power_on)(struct phy *phy); 262 int (*dphy_rx_power_off)(struct phy *phy); 263 264 unsigned int flags; 265 unsigned int max_data_lanes; 266}; 267 268struct dw_mipi_dsi_rockchip { 269 struct device *dev; 270 struct rockchip_encoder encoder; 271 void __iomem *base; 272 273 struct regmap *grf_regmap; 274 struct clk *pclk; 275 struct clk *pllref_clk; 276 struct clk *grf_clk; 277 struct clk *phy_cfg_clk; 278 279 /* dual-channel */ 280 bool is_slave; 281 struct dw_mipi_dsi_rockchip *slave; 282 283 /* optional external dphy */ 284 struct phy *phy; 285 union phy_configure_opts phy_opts; 286 287 /* being a phy for other mipi hosts */ 288 unsigned int usage_mode; 289 struct mutex usage_mutex; 290 struct phy *dphy; 291 struct phy_configure_opts_mipi_dphy dphy_config; 292 293 unsigned int lane_mbps; /* per lane */ 294 u16 input_div; 295 u16 feedback_div; 296 u32 format; 297 298 struct dw_mipi_dsi *dmd; 299 const struct rockchip_dw_dsi_chip_data *cdata; 300 struct dw_mipi_dsi_plat_data pdata; 301 302 bool dsi_bound; 303}; 304 305static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) 306{ 307 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 308 309 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); 310} 311 312struct dphy_pll_parameter_map { 313 unsigned int max_mbps; 314 u8 hsfreqrange; 315 u8 icpctrl; 316 u8 lpfctrl; 317}; 318 319/* The table is based on 27MHz DPHY pll reference clock. */ 320static const struct dphy_pll_parameter_map dppa_map[] = { 321 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 322 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 323 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 324 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 325 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 326 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 327 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 328 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 329 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 330 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 331 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 332 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 333 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 334 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 335 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 336 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 337 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 338 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 339 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 340 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 341 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 342 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 343 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 344 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 345 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 346 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 347 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 348 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 349 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 350 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 351 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 352 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 353 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 354 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 355 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 356 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 357 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 358 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 359 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 360}; 361 362static int max_mbps_to_parameter(unsigned int max_mbps) 363{ 364 int i; 365 366 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 367 if (dppa_map[i].max_mbps >= max_mbps) 368 return i; 369 370 return -EINVAL; 371} 372 373static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 374{ 375 writel(val, dsi->base + reg); 376} 377 378static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 379 u8 test_code, 380 u8 test_data) 381{ 382 /* 383 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 384 * is latched internally as the current test code. Test data is 385 * programmed internally by rising edge on TESTCLK. 386 */ 387 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 388 389 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 390 PHY_TESTDIN(test_code)); 391 392 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 393 394 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 395 PHY_TESTDIN(test_data)); 396 397 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 398} 399 400/* 401 * ns2bc - Nanoseconds to byte clock cycles 402 */ 403static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 404{ 405 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 406} 407 408/* 409 * ns2ui - Nanoseconds to UI time periods 410 */ 411static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 412{ 413 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 414} 415 416static int dw_mipi_dsi_phy_init(void *priv_data) 417{ 418 struct dw_mipi_dsi_rockchip *dsi = priv_data; 419 int ret, i, vco; 420 421 if (dsi->phy) 422 return 0; 423 424 /* 425 * Get vco from frequency(lane_mbps) 426 * vco frequency table 427 * 000 - between 80 and 200 MHz 428 * 001 - between 200 and 300 MHz 429 * 010 - between 300 and 500 MHz 430 * 011 - between 500 and 700 MHz 431 * 100 - between 700 and 900 MHz 432 * 101 - between 900 and 1100 MHz 433 * 110 - between 1100 and 1300 MHz 434 * 111 - between 1300 and 1500 MHz 435 */ 436 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 437 438 i = max_mbps_to_parameter(dsi->lane_mbps); 439 if (i < 0) { 440 DRM_DEV_ERROR(dsi->dev, 441 "failed to get parameter for %dmbps clock\n", 442 dsi->lane_mbps); 443 return i; 444 } 445 446 ret = clk_prepare_enable(dsi->phy_cfg_clk); 447 if (ret) { 448 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 449 return ret; 450 } 451 452 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 453 BYPASS_VCO_RANGE | 454 VCO_RANGE_CON_SEL(vco) | 455 VCO_IN_CAP_CON_LOW | 456 REF_BIAS_CUR_SEL); 457 458 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 459 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 460 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 461 CP_PROGRAM_EN | LPF_PROGRAM_EN | 462 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 463 464 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 465 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 466 467 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 468 INPUT_DIVIDER(dsi->input_div)); 469 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 470 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 471 LOW_PROGRAM_EN); 472 /* 473 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 474 * to make the configured LSB effective according to IP simulation 475 * and lab test results. 476 * Only in this way can we get correct mipi phy pll frequency. 477 */ 478 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 479 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 480 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 481 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 482 HIGH_PROGRAM_EN); 483 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 484 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 485 486 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 487 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 488 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 489 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 490 491 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 492 POWER_CONTROL | INTERNAL_REG_CURRENT | 493 BIAS_BLOCK_ON | BANDGAP_ON); 494 495 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 496 TER_RESISTOR_LOW | TER_CAL_DONE | 497 SETRD_MAX | TER_RESISTORS_ON); 498 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 499 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 500 SETRD_MAX | POWER_MANAGE | 501 TER_RESISTORS_ON); 502 503 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 504 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 505 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 506 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 507 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 508 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 509 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 510 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 511 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 512 BIT(5) | ns2bc(dsi, 100)); 513 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 514 BIT(5) | (ns2bc(dsi, 60) + 7)); 515 516 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 517 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 518 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 519 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 520 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 521 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 522 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 523 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 524 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 525 BIT(5) | ns2bc(dsi, 100)); 526 527 clk_disable_unprepare(dsi->phy_cfg_clk); 528 529 return ret; 530} 531 532static void dw_mipi_dsi_phy_power_on(void *priv_data) 533{ 534 struct dw_mipi_dsi_rockchip *dsi = priv_data; 535 int ret; 536 537 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 538 if (ret) { 539 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 540 return; 541 } 542 543 phy_configure(dsi->phy, &dsi->phy_opts); 544 phy_power_on(dsi->phy); 545} 546 547static void dw_mipi_dsi_phy_power_off(void *priv_data) 548{ 549 struct dw_mipi_dsi_rockchip *dsi = priv_data; 550 551 phy_power_off(dsi->phy); 552} 553 554static int 555dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 556 unsigned long mode_flags, u32 lanes, u32 format, 557 unsigned int *lane_mbps) 558{ 559 struct dw_mipi_dsi_rockchip *dsi = priv_data; 560 int bpp; 561 unsigned long mpclk, tmp; 562 unsigned int target_mbps = 1000; 563 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 564 unsigned long best_freq = 0; 565 unsigned long fvco_min, fvco_max, fin, fout; 566 unsigned int min_prediv, max_prediv; 567 unsigned int _prediv, best_prediv; 568 unsigned long _fbdiv, best_fbdiv; 569 unsigned long min_delta = ULONG_MAX; 570 571 dsi->format = format; 572 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 573 if (bpp < 0) { 574 DRM_DEV_ERROR(dsi->dev, 575 "failed to get bpp for pixel format %d\n", 576 dsi->format); 577 return bpp; 578 } 579 580 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 581 if (mpclk) { 582 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 583 tmp = mpclk * (bpp / lanes) * 10 / 8; 584 if (tmp < max_mbps) 585 target_mbps = tmp; 586 else 587 DRM_DEV_ERROR(dsi->dev, 588 "DPHY clock frequency is out of range\n"); 589 } 590 591 /* for external phy only a the mipi_dphy_config is necessary */ 592 if (dsi->phy) { 593 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 594 bpp, lanes, 595 &dsi->phy_opts.mipi_dphy); 596 dsi->lane_mbps = target_mbps; 597 *lane_mbps = dsi->lane_mbps; 598 599 return 0; 600 } 601 602 fin = clk_get_rate(dsi->pllref_clk); 603 fout = target_mbps * USEC_PER_SEC; 604 605 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 606 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 607 max_prediv = fin / (5 * USEC_PER_SEC); 608 609 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 610 fvco_min = 80 * USEC_PER_SEC; 611 fvco_max = 1500 * USEC_PER_SEC; 612 613 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 614 u64 tmp; 615 u32 delta; 616 /* Fvco = Fref * M / N */ 617 tmp = (u64)fout * _prediv; 618 do_div(tmp, fin); 619 _fbdiv = tmp; 620 /* 621 * Due to the use of a "by 2 pre-scaler," the range of the 622 * feedback multiplication value M is limited to even division 623 * numbers, and m must be greater than 6, not bigger than 512. 624 */ 625 if (_fbdiv < 6 || _fbdiv > 512) 626 continue; 627 628 _fbdiv += _fbdiv % 2; 629 630 tmp = (u64)_fbdiv * fin; 631 do_div(tmp, _prediv); 632 if (tmp < fvco_min || tmp > fvco_max) 633 continue; 634 635 delta = abs(fout - tmp); 636 if (delta < min_delta) { 637 best_prediv = _prediv; 638 best_fbdiv = _fbdiv; 639 min_delta = delta; 640 best_freq = tmp; 641 } 642 } 643 644 if (best_freq) { 645 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 646 *lane_mbps = dsi->lane_mbps; 647 dsi->input_div = best_prediv; 648 dsi->feedback_div = best_fbdiv; 649 } else { 650 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 651 return -EINVAL; 652 } 653 654 return 0; 655} 656 657struct hstt { 658 unsigned int maxfreq; 659 struct dw_mipi_dsi_dphy_timing timing; 660}; 661 662#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 663{ \ 664 .maxfreq = _maxfreq, \ 665 .timing = { \ 666 .clk_lp2hs = _c_lp2hs, \ 667 .clk_hs2lp = _c_hs2lp, \ 668 .data_lp2hs = _d_lp2hs, \ 669 .data_hs2lp = _d_hs2lp, \ 670 } \ 671} 672 673/* Table A-3 High-Speed Transition Times */ 674static struct hstt hstt_table[] = { 675 HSTT( 90, 32, 20, 26, 13), 676 HSTT( 100, 35, 23, 28, 14), 677 HSTT( 110, 32, 22, 26, 13), 678 HSTT( 130, 31, 20, 27, 13), 679 HSTT( 140, 33, 22, 26, 14), 680 HSTT( 150, 33, 21, 26, 14), 681 HSTT( 170, 32, 20, 27, 13), 682 HSTT( 180, 36, 23, 30, 15), 683 HSTT( 200, 40, 22, 33, 15), 684 HSTT( 220, 40, 22, 33, 15), 685 HSTT( 240, 44, 24, 36, 16), 686 HSTT( 250, 48, 24, 38, 17), 687 HSTT( 270, 48, 24, 38, 17), 688 HSTT( 300, 50, 27, 41, 18), 689 HSTT( 330, 56, 28, 45, 18), 690 HSTT( 360, 59, 28, 48, 19), 691 HSTT( 400, 61, 30, 50, 20), 692 HSTT( 450, 67, 31, 55, 21), 693 HSTT( 500, 73, 31, 59, 22), 694 HSTT( 550, 79, 36, 63, 24), 695 HSTT( 600, 83, 37, 68, 25), 696 HSTT( 650, 90, 38, 73, 27), 697 HSTT( 700, 95, 40, 77, 28), 698 HSTT( 750, 102, 40, 84, 28), 699 HSTT( 800, 106, 42, 87, 30), 700 HSTT( 850, 113, 44, 93, 31), 701 HSTT( 900, 118, 47, 98, 32), 702 HSTT( 950, 124, 47, 102, 34), 703 HSTT(1000, 130, 49, 107, 35), 704 HSTT(1050, 135, 51, 111, 37), 705 HSTT(1100, 139, 51, 114, 38), 706 HSTT(1150, 146, 54, 120, 40), 707 HSTT(1200, 153, 57, 125, 41), 708 HSTT(1250, 158, 58, 130, 42), 709 HSTT(1300, 163, 58, 135, 44), 710 HSTT(1350, 168, 60, 140, 45), 711 HSTT(1400, 172, 64, 144, 47), 712 HSTT(1450, 176, 65, 148, 48), 713 HSTT(1500, 181, 66, 153, 50) 714}; 715 716static int 717dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 718 struct dw_mipi_dsi_dphy_timing *timing) 719{ 720 int i; 721 722 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 723 if (lane_mbps < hstt_table[i].maxfreq) 724 break; 725 726 if (i == ARRAY_SIZE(hstt_table)) 727 i--; 728 729 *timing = hstt_table[i].timing; 730 731 return 0; 732} 733 734static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 735 .init = dw_mipi_dsi_phy_init, 736 .power_on = dw_mipi_dsi_phy_power_on, 737 .power_off = dw_mipi_dsi_phy_power_off, 738 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 739 .get_timing = dw_mipi_dsi_phy_get_timing, 740}; 741 742static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 743{ 744 if (dsi->cdata->lanecfg1_grf_reg) 745 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 746 dsi->cdata->lanecfg1); 747 748 if (dsi->cdata->lanecfg2_grf_reg) 749 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 750 dsi->cdata->lanecfg2); 751 752 if (dsi->cdata->enable_grf_reg) 753 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 754 dsi->cdata->enable); 755} 756 757static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 758 int mux) 759{ 760 if (dsi->cdata->lcdsel_grf_reg) 761 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 762 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 763} 764 765static int 766dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 767 struct drm_crtc_state *crtc_state, 768 struct drm_connector_state *conn_state) 769{ 770 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 771 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 772 773 switch (dsi->format) { 774 case MIPI_DSI_FMT_RGB888: 775 s->output_mode = ROCKCHIP_OUT_MODE_P888; 776 break; 777 case MIPI_DSI_FMT_RGB666: 778 s->output_mode = ROCKCHIP_OUT_MODE_P666; 779 break; 780 case MIPI_DSI_FMT_RGB565: 781 s->output_mode = ROCKCHIP_OUT_MODE_P565; 782 break; 783 default: 784 WARN_ON(1); 785 return -EINVAL; 786 } 787 788 s->output_type = DRM_MODE_CONNECTOR_DSI; 789 if (dsi->slave) 790 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 791 792 return 0; 793} 794 795static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 796{ 797 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 798 int ret, mux; 799 800 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 801 &dsi->encoder.encoder); 802 if (mux < 0) 803 return; 804 805 /* 806 * For the RK3399, the clk of grf must be enabled before writing grf 807 * register. And for RK3288 or other soc, this grf_clk must be NULL, 808 * the clk_prepare_enable return true directly. 809 */ 810 ret = clk_prepare_enable(dsi->grf_clk); 811 if (ret) { 812 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 813 return; 814 } 815 816 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 817 if (dsi->slave) 818 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 819 820 clk_disable_unprepare(dsi->grf_clk); 821} 822 823static const struct drm_encoder_helper_funcs 824dw_mipi_dsi_encoder_helper_funcs = { 825 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 826 .enable = dw_mipi_dsi_encoder_enable, 827}; 828 829static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 830 struct drm_device *drm_dev) 831{ 832 struct drm_encoder *encoder = &dsi->encoder.encoder; 833 int ret; 834 835 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 836 dsi->dev->of_node); 837 838 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 839 if (ret) { 840 DRM_ERROR("Failed to initialize encoder with drm\n"); 841 return ret; 842 } 843 844 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 845 846 return 0; 847} 848 849static struct device 850*dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 851{ 852 const struct of_device_id *match; 853 struct device_node *node = NULL, *local; 854 855 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 856 857 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 858 if (!local) 859 return NULL; 860 861 while ((node = of_find_compatible_node(node, NULL, 862 match->compatible))) { 863 struct device_node *remote; 864 865 /* found ourself */ 866 if (node == dsi->dev->of_node) 867 continue; 868 869 remote = of_graph_get_remote_node(node, 1, 0); 870 if (!remote) 871 continue; 872 873 /* same display device in port1-ep0 for both */ 874 if (remote == local) { 875 struct dw_mipi_dsi_rockchip *dsi2; 876 struct platform_device *pdev; 877 878 pdev = of_find_device_by_node(node); 879 880 /* 881 * we have found the second, so will either return it 882 * or return with an error. In any case won't need the 883 * nodes anymore nor continue the loop. 884 */ 885 of_node_put(remote); 886 of_node_put(node); 887 of_node_put(local); 888 889 if (!pdev) 890 return ERR_PTR(-EPROBE_DEFER); 891 892 dsi2 = platform_get_drvdata(pdev); 893 if (!dsi2) { 894 platform_device_put(pdev); 895 return ERR_PTR(-EPROBE_DEFER); 896 } 897 898 return &pdev->dev; 899 } 900 901 of_node_put(remote); 902 } 903 904 of_node_put(local); 905 906 return NULL; 907} 908 909static int dw_mipi_dsi_rockchip_bind(struct device *dev, 910 struct device *master, 911 void *data) 912{ 913 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 914 struct drm_device *drm_dev = data; 915 struct device *second; 916 bool master1, master2; 917 int ret; 918 919 second = dw_mipi_dsi_rockchip_find_second(dsi); 920 if (IS_ERR(second)) 921 return PTR_ERR(second); 922 923 if (second) { 924 master1 = of_property_read_bool(dsi->dev->of_node, 925 "clock-master"); 926 master2 = of_property_read_bool(second->of_node, 927 "clock-master"); 928 929 if (master1 && master2) { 930 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 931 return -EINVAL; 932 } 933 934 if (!master1 && !master2) { 935 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 936 return -EINVAL; 937 } 938 939 /* we are the slave in dual-DSI */ 940 if (!master1) { 941 dsi->is_slave = true; 942 return 0; 943 } 944 945 dsi->slave = dev_get_drvdata(second); 946 if (!dsi->slave) { 947 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 948 return -ENODEV; 949 } 950 951 dsi->slave->is_slave = true; 952 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 953 put_device(second); 954 } 955 956 pm_runtime_get_sync(dsi->dev); 957 if (dsi->slave) 958 pm_runtime_get_sync(dsi->slave->dev); 959 960 ret = clk_prepare_enable(dsi->pllref_clk); 961 if (ret) { 962 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 963 goto out_pm_runtime; 964 } 965 966 /* 967 * With the GRF clock running, write lane and dual-mode configurations 968 * that won't change immediately. If we waited until enable() to do 969 * this, things like panel preparation would not be able to send 970 * commands over DSI. 971 */ 972 ret = clk_prepare_enable(dsi->grf_clk); 973 if (ret) { 974 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 975 goto out_pll_clk; 976 } 977 978 dw_mipi_dsi_rockchip_config(dsi); 979 if (dsi->slave) 980 dw_mipi_dsi_rockchip_config(dsi->slave); 981 982 clk_disable_unprepare(dsi->grf_clk); 983 984 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 985 if (ret) { 986 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 987 goto out_pll_clk; 988 } 989 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, 990 dev->of_node, 0, 0); 991 992 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); 993 if (ret) { 994 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 995 goto out_pll_clk; 996 } 997 998 dsi->dsi_bound = true; 999 1000 return 0; 1001 1002out_pll_clk: 1003 clk_disable_unprepare(dsi->pllref_clk); 1004out_pm_runtime: 1005 pm_runtime_put(dsi->dev); 1006 if (dsi->slave) 1007 pm_runtime_put(dsi->slave->dev); 1008 1009 return ret; 1010} 1011 1012static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 1013 struct device *master, 1014 void *data) 1015{ 1016 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1017 1018 if (dsi->is_slave) 1019 return; 1020 1021 dsi->dsi_bound = false; 1022 1023 dw_mipi_dsi_unbind(dsi->dmd); 1024 1025 clk_disable_unprepare(dsi->pllref_clk); 1026 1027 pm_runtime_put(dsi->dev); 1028 if (dsi->slave) 1029 pm_runtime_put(dsi->slave->dev); 1030} 1031 1032static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1033 .bind = dw_mipi_dsi_rockchip_bind, 1034 .unbind = dw_mipi_dsi_rockchip_unbind, 1035}; 1036 1037static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1038 struct mipi_dsi_device *device) 1039{ 1040 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1041 struct device *second; 1042 int ret; 1043 1044 mutex_lock(&dsi->usage_mutex); 1045 1046 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1047 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1048 mutex_unlock(&dsi->usage_mutex); 1049 return -EBUSY; 1050 } 1051 1052 dsi->usage_mode = DW_DSI_USAGE_DSI; 1053 mutex_unlock(&dsi->usage_mutex); 1054 1055 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1056 if (ret) { 1057 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1058 ret); 1059 goto out; 1060 } 1061 1062 second = dw_mipi_dsi_rockchip_find_second(dsi); 1063 if (IS_ERR(second)) { 1064 ret = PTR_ERR(second); 1065 goto out; 1066 } 1067 if (second) { 1068 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1069 if (ret) { 1070 DRM_DEV_ERROR(second, 1071 "Failed to register component: %d\n", 1072 ret); 1073 goto out; 1074 } 1075 } 1076 1077 return 0; 1078 1079out: 1080 mutex_lock(&dsi->usage_mutex); 1081 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1082 mutex_unlock(&dsi->usage_mutex); 1083 return ret; 1084} 1085 1086static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1087 struct mipi_dsi_device *device) 1088{ 1089 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1090 struct device *second; 1091 1092 second = dw_mipi_dsi_rockchip_find_second(dsi); 1093 if (second && !IS_ERR(second)) 1094 component_del(second, &dw_mipi_dsi_rockchip_ops); 1095 1096 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1097 1098 mutex_lock(&dsi->usage_mutex); 1099 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1100 mutex_unlock(&dsi->usage_mutex); 1101 1102 return 0; 1103} 1104 1105static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1106 .attach = dw_mipi_dsi_rockchip_host_attach, 1107 .detach = dw_mipi_dsi_rockchip_host_detach, 1108}; 1109 1110static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1111 struct device *master, 1112 void *data) 1113{ 1114 /* 1115 * Nothing to do when used as a dphy. 1116 * Just make the rest of Rockchip-DRM happy 1117 * by being here. 1118 */ 1119 1120 return 0; 1121} 1122 1123static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1124 struct device *master, 1125 void *data) 1126{ 1127 /* Nothing to do when used as a dphy. */ 1128} 1129 1130static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1131 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1132 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1133}; 1134 1135static int dw_mipi_dsi_dphy_init(struct phy *phy) 1136{ 1137 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1138 int ret; 1139 1140 mutex_lock(&dsi->usage_mutex); 1141 1142 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1143 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1144 mutex_unlock(&dsi->usage_mutex); 1145 return -EBUSY; 1146 } 1147 1148 dsi->usage_mode = DW_DSI_USAGE_PHY; 1149 mutex_unlock(&dsi->usage_mutex); 1150 1151 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1152 if (ret < 0) 1153 goto err_graph; 1154 1155 if (dsi->cdata->dphy_rx_init) { 1156 ret = clk_prepare_enable(dsi->pclk); 1157 if (ret < 0) 1158 goto err_init; 1159 1160 ret = clk_prepare_enable(dsi->grf_clk); 1161 if (ret) { 1162 clk_disable_unprepare(dsi->pclk); 1163 goto err_init; 1164 } 1165 1166 ret = dsi->cdata->dphy_rx_init(phy); 1167 clk_disable_unprepare(dsi->grf_clk); 1168 clk_disable_unprepare(dsi->pclk); 1169 if (ret < 0) 1170 goto err_init; 1171 } 1172 1173 return 0; 1174 1175err_init: 1176 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1177err_graph: 1178 mutex_lock(&dsi->usage_mutex); 1179 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1180 mutex_unlock(&dsi->usage_mutex); 1181 1182 return ret; 1183} 1184 1185static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1186{ 1187 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1188 1189 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1190 1191 mutex_lock(&dsi->usage_mutex); 1192 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1193 mutex_unlock(&dsi->usage_mutex); 1194 1195 return 0; 1196} 1197 1198static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1199{ 1200 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1201 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1202 int ret; 1203 1204 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1205 if (ret) 1206 return ret; 1207 1208 dsi->dphy_config = *config; 1209 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1210 1211 return 0; 1212} 1213 1214static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1215{ 1216 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1217 int i, ret; 1218 1219 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1220 dsi->dphy_config.lanes, dsi->lane_mbps); 1221 1222 i = max_mbps_to_parameter(dsi->lane_mbps); 1223 if (i < 0) { 1224 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1225 dsi->lane_mbps); 1226 return i; 1227 } 1228 1229 ret = pm_runtime_resume_and_get(dsi->dev); 1230 if (ret < 0) { 1231 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1232 return ret; 1233 } 1234 1235 ret = clk_prepare_enable(dsi->pclk); 1236 if (ret) { 1237 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1238 goto err_pclk; 1239 } 1240 1241 ret = clk_prepare_enable(dsi->grf_clk); 1242 if (ret) { 1243 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1244 goto err_grf_clk; 1245 } 1246 1247 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1248 if (ret) { 1249 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1250 goto err_phy_cfg_clk; 1251 } 1252 1253 /* do soc-variant specific init */ 1254 if (dsi->cdata->dphy_rx_power_on) { 1255 ret = dsi->cdata->dphy_rx_power_on(phy); 1256 if (ret < 0) { 1257 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1258 goto err_pwr_on; 1259 } 1260 } 1261 1262 /* 1263 * Configure hsfreqrange according to frequency values 1264 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1265 */ 1266 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1267 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1268 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1269 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1270 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1271 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1272 1273 /* Normal operation */ 1274 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1275 1276 clk_disable_unprepare(dsi->phy_cfg_clk); 1277 clk_disable_unprepare(dsi->grf_clk); 1278 1279 return ret; 1280 1281err_pwr_on: 1282 clk_disable_unprepare(dsi->phy_cfg_clk); 1283err_phy_cfg_clk: 1284 clk_disable_unprepare(dsi->grf_clk); 1285err_grf_clk: 1286 clk_disable_unprepare(dsi->pclk); 1287err_pclk: 1288 pm_runtime_put(dsi->dev); 1289 return ret; 1290} 1291 1292static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1293{ 1294 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1295 int ret; 1296 1297 ret = clk_prepare_enable(dsi->grf_clk); 1298 if (ret) { 1299 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1300 return ret; 1301 } 1302 1303 if (dsi->cdata->dphy_rx_power_off) { 1304 ret = dsi->cdata->dphy_rx_power_off(phy); 1305 if (ret < 0) 1306 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1307 } 1308 1309 clk_disable_unprepare(dsi->grf_clk); 1310 clk_disable_unprepare(dsi->pclk); 1311 1312 pm_runtime_put(dsi->dev); 1313 1314 return ret; 1315} 1316 1317static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1318 .configure = dw_mipi_dsi_dphy_configure, 1319 .power_on = dw_mipi_dsi_dphy_power_on, 1320 .power_off = dw_mipi_dsi_dphy_power_off, 1321 .init = dw_mipi_dsi_dphy_init, 1322 .exit = dw_mipi_dsi_dphy_exit, 1323}; 1324 1325static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1326{ 1327 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1328 int ret; 1329 1330 /* 1331 * Re-configure DSI state, if we were previously initialized. We need 1332 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1333 */ 1334 if (dsi->dsi_bound) { 1335 ret = clk_prepare_enable(dsi->grf_clk); 1336 if (ret) { 1337 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1338 return ret; 1339 } 1340 1341 dw_mipi_dsi_rockchip_config(dsi); 1342 if (dsi->slave) 1343 dw_mipi_dsi_rockchip_config(dsi->slave); 1344 1345 clk_disable_unprepare(dsi->grf_clk); 1346 } 1347 1348 return 0; 1349} 1350 1351static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1352 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1353}; 1354 1355static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1356{ 1357 struct device *dev = &pdev->dev; 1358 struct device_node *np = dev->of_node; 1359 struct dw_mipi_dsi_rockchip *dsi; 1360 struct phy_provider *phy_provider; 1361 struct resource *res; 1362 const struct rockchip_dw_dsi_chip_data *cdata = 1363 of_device_get_match_data(dev); 1364 int ret, i; 1365 1366 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1367 if (!dsi) 1368 return -ENOMEM; 1369 1370 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1371 if (IS_ERR(dsi->base)) { 1372 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1373 return PTR_ERR(dsi->base); 1374 } 1375 1376 i = 0; 1377 while (cdata[i].reg) { 1378 if (cdata[i].reg == res->start) { 1379 dsi->cdata = &cdata[i]; 1380 break; 1381 } 1382 1383 i++; 1384 } 1385 1386 if (!dsi->cdata) { 1387 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1388 return -EINVAL; 1389 } 1390 1391 /* try to get a possible external dphy */ 1392 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1393 if (IS_ERR(dsi->phy)) { 1394 ret = PTR_ERR(dsi->phy); 1395 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1396 return ret; 1397 } 1398 1399 dsi->pclk = devm_clk_get(dev, "pclk"); 1400 if (IS_ERR(dsi->pclk)) { 1401 ret = PTR_ERR(dsi->pclk); 1402 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1403 return ret; 1404 } 1405 1406 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1407 if (IS_ERR(dsi->pllref_clk)) { 1408 if (dsi->phy) { 1409 /* 1410 * if external phy is present, pll will be 1411 * generated there. 1412 */ 1413 dsi->pllref_clk = NULL; 1414 } else { 1415 ret = PTR_ERR(dsi->pllref_clk); 1416 DRM_DEV_ERROR(dev, 1417 "Unable to get pll reference clock: %d\n", 1418 ret); 1419 return ret; 1420 } 1421 } 1422 1423 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1424 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1425 if (IS_ERR(dsi->phy_cfg_clk)) { 1426 ret = PTR_ERR(dsi->phy_cfg_clk); 1427 DRM_DEV_ERROR(dev, 1428 "Unable to get phy_cfg_clk: %d\n", ret); 1429 return ret; 1430 } 1431 } 1432 1433 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1434 dsi->grf_clk = devm_clk_get(dev, "grf"); 1435 if (IS_ERR(dsi->grf_clk)) { 1436 ret = PTR_ERR(dsi->grf_clk); 1437 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1438 return ret; 1439 } 1440 } 1441 1442 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1443 if (IS_ERR(dsi->grf_regmap)) { 1444 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1445 return PTR_ERR(dsi->grf_regmap); 1446 } 1447 1448 dsi->dev = dev; 1449 dsi->pdata.base = dsi->base; 1450 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1451 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1452 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1453 dsi->pdata.priv_data = dsi; 1454 platform_set_drvdata(pdev, dsi); 1455 1456 mutex_init(&dsi->usage_mutex); 1457 1458 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1459 if (IS_ERR(dsi->dphy)) { 1460 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1461 return PTR_ERR(dsi->dphy); 1462 } 1463 1464 phy_set_drvdata(dsi->dphy, dsi); 1465 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1466 if (IS_ERR(phy_provider)) 1467 return PTR_ERR(phy_provider); 1468 1469 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1470 if (IS_ERR(dsi->dmd)) { 1471 ret = PTR_ERR(dsi->dmd); 1472 if (ret != -EPROBE_DEFER) 1473 DRM_DEV_ERROR(dev, 1474 "Failed to probe dw_mipi_dsi: %d\n", ret); 1475 return ret; 1476 } 1477 1478 return 0; 1479} 1480 1481static void dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1482{ 1483 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1484 1485 dw_mipi_dsi_remove(dsi->dmd); 1486} 1487 1488static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1489 { 1490 .reg = 0xff450000, 1491 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1492 .lcdsel_big = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 0), 1493 .lcdsel_lit = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 1), 1494 1495 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1496 .lanecfg1 = FIELD_PREP_WM16_CONST((PX30_DSI_TURNDISABLE | 1497 PX30_DSI_FORCERXMODE | 1498 PX30_DSI_FORCETXSTOPMODE), 0), 1499 1500 .max_data_lanes = 4, 1501 }, 1502 { /* sentinel */ } 1503}; 1504 1505static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = { 1506 { 1507 .reg = 0x10110000, 1508 .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0, 1509 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3128_DSI_TURNDISABLE | 1510 RK3128_DSI_FORCERXMODE | 1511 RK3128_DSI_FORCETXSTOPMODE), 0), 1512 .max_data_lanes = 4, 1513 }, 1514 { /* sentinel */ } 1515}; 1516 1517static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1518 { 1519 .reg = 0xff960000, 1520 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1521 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 0), 1522 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1), 1523 1524 .max_data_lanes = 4, 1525 }, 1526 { 1527 .reg = 0xff964000, 1528 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1529 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 0), 1530 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1), 1531 1532 .max_data_lanes = 4, 1533 }, 1534 { /* sentinel */ } 1535}; 1536 1537static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = { 1538 { 1539 .reg = 0xff960000, 1540 .lanecfg1_grf_reg = RK3368_GRF_SOC_CON7, 1541 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3368_DSI_TURNDISABLE | 1542 RK3368_DSI_FORCETXSTOPMODE | 1543 RK3368_DSI_FORCERXMODE), 0), 1544 .max_data_lanes = 4, 1545 }, 1546 { /* sentinel */ } 1547}; 1548 1549static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1550{ 1551 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1552 1553 /* 1554 * Set TX1RX1 source to isp1. 1555 * Assume ISP0 is supplied by the RX0 dphy. 1556 */ 1557 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1558 FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0)); 1559 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1560 FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0)); 1561 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1562 FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0)); 1563 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1564 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0)); 1565 1566 return 0; 1567} 1568 1569static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1570{ 1571 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1572 1573 /* tester reset pulse */ 1574 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1575 usleep_range(100, 150); 1576 1577 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1578 FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0)); 1579 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1580 FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1)); 1581 1582 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1583 FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0)); 1584 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1585 FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0)); 1586 1587 /* Disable lane turn around, which is ignored in receive mode */ 1588 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1589 FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0)); 1590 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1591 FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf)); 1592 usleep_range(100, 150); 1593 1594 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1595 usleep_range(100, 150); 1596 1597 /* Enable dphy lanes */ 1598 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1599 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 1600 GENMASK(dsi->dphy_config.lanes - 1, 0))); 1601 1602 usleep_range(100, 150); 1603 1604 return 0; 1605} 1606 1607static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1608{ 1609 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1610 1611 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1612 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0)); 1613 1614 return 0; 1615} 1616 1617static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1618 { 1619 .reg = 0xff960000, 1620 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1621 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 0), 1622 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 1), 1623 1624 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1625 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI0_TURNREQUEST | 1626 RK3399_DSI0_TURNDISABLE | 1627 RK3399_DSI0_FORCETXSTOPMODE | 1628 RK3399_DSI0_FORCERXMODE), 0), 1629 1630 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1631 .max_data_lanes = 4, 1632 }, 1633 { 1634 .reg = 0xff968000, 1635 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1636 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 0), 1637 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 1), 1638 1639 1640 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1641 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI1_TURNDISABLE | 1642 RK3399_DSI1_FORCETXSTOPMODE | 1643 RK3399_DSI1_FORCERXMODE | 1644 RK3399_DSI1_ENABLE), 0), 1645 1646 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1647 .lanecfg2 = (FIELD_PREP_WM16_CONST(RK3399_TXRX_MASTERSLAVEZ, 1) | 1648 FIELD_PREP_WM16_CONST(RK3399_TXRX_ENABLECLK, 1) | 1649 FIELD_PREP_WM16_CONST(RK3399_TXRX_BASEDIR, 0)), 1650 1651 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1652 .enable = FIELD_PREP_WM16_CONST(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1653 1654 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1655 .max_data_lanes = 4, 1656 1657 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1658 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1659 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1660 }, 1661 { /* sentinel */ } 1662}; 1663 1664static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { 1665 { 1666 .reg = 0xfe060000, 1667 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, 1668 .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI0_SKEWCALHS, 0) | 1669 FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCETXSTOPMODE, 0) | 1670 FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) | 1671 FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), 1672 .max_data_lanes = 4, 1673 }, 1674 { 1675 .reg = 0xfe070000, 1676 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, 1677 .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI1_SKEWCALHS, 0) | 1678 FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCETXSTOPMODE, 0) | 1679 FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) | 1680 FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), 1681 .max_data_lanes = 4, 1682 }, 1683 { /* sentinel */ } 1684}; 1685 1686static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = { 1687 { 1688 .reg = 0xffb30000, 1689 .lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON, 1690 .lanecfg1 = (FIELD_PREP_WM16_CONST(RV1126_DSI_TURNDISABLE, 0) | 1691 FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) | 1692 FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), 1693 .max_data_lanes = 4, 1694 }, 1695 { /* sentinel */ } 1696}; 1697 1698static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1699 { 1700 .compatible = "rockchip,px30-mipi-dsi", 1701 .data = &px30_chip_data, 1702 }, { 1703 .compatible = "rockchip,rk3128-mipi-dsi", 1704 .data = &rk3128_chip_data, 1705 }, { 1706 .compatible = "rockchip,rk3288-mipi-dsi", 1707 .data = &rk3288_chip_data, 1708 }, { 1709 .compatible = "rockchip,rk3368-mipi-dsi", 1710 .data = &rk3368_chip_data, 1711 }, { 1712 .compatible = "rockchip,rk3399-mipi-dsi", 1713 .data = &rk3399_chip_data, 1714 }, { 1715 .compatible = "rockchip,rk3568-mipi-dsi", 1716 .data = &rk3568_chip_data, 1717 }, { 1718 .compatible = "rockchip,rv1126-mipi-dsi", 1719 .data = &rv1126_chip_data, 1720 }, 1721 { /* sentinel */ } 1722}; 1723MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1724 1725struct platform_driver dw_mipi_dsi_rockchip_driver = { 1726 .probe = dw_mipi_dsi_rockchip_probe, 1727 .remove = dw_mipi_dsi_rockchip_remove, 1728 .driver = { 1729 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1730 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1731 .name = "dw-mipi-dsi-rockchip", 1732 /* 1733 * For dual-DSI display, one DSI pokes at the other DSI's 1734 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1735 * safe for asynchronous probe. 1736 */ 1737 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1738 }, 1739};
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