cdn-dp-core.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
  4 * Copyright (C) Rockchip Electronics Co., Ltd.
  5 */
  6
  7#ifndef _CDN_DP_CORE_H
  8#define _CDN_DP_CORE_H
  9
 10#include <drm/display/drm_dp_helper.h>
 11#include <drm/drm_bridge.h>
 12#include <drm/drm_panel.h>
 13#include <drm/drm_probe_helper.h>
 14#include <sound/hdmi-codec.h>
 15
 16#include "rockchip_drm_drv.h"
 17
 18#define MAX_PHY		2
 19
 20enum audio_format {
 21	AFMT_I2S = 0,
 22	AFMT_SPDIF = 1,
 23	AFMT_UNUSED,
 24};
 25
 26struct audio_info {
 27	enum audio_format format;
 28	int sample_rate;
 29	int channels;
 30	int sample_width;
 31};
 32
 33enum vic_pxl_encoding_format {
 34	PXL_RGB = 0x1,
 35	YCBCR_4_4_4 = 0x2,
 36	YCBCR_4_2_2 = 0x4,
 37	YCBCR_4_2_0 = 0x8,
 38	Y_ONLY = 0x10,
 39};
 40
 41struct video_info {
 42	bool h_sync_polarity;
 43	bool v_sync_polarity;
 44	bool interlaced;
 45	int color_depth;
 46	enum vic_pxl_encoding_format color_fmt;
 47};
 48
 49struct cdn_firmware_header {
 50	u32 size_bytes; /* size of the entire header+image(s) in bytes */
 51	u32 header_size; /* size of just the header in bytes */
 52	u32 iram_size; /* size of iram */
 53	u32 dram_size; /* size of dram */
 54};
 55
 56struct cdn_dp_port {
 57	struct cdn_dp_device *dp;
 58	struct notifier_block event_nb;
 59	struct extcon_dev *extcon;
 60	struct phy *phy;
 61	u8 lanes;
 62	bool phy_enabled;
 63	u8 id;
 64};
 65
 66struct cdn_dp_device {
 67	struct device *dev;
 68	struct drm_device *drm_dev;
 69	struct drm_bridge bridge;
 70	struct rockchip_encoder encoder;
 71	struct drm_display_mode mode;
 72	struct platform_device *audio_pdev;
 73	struct work_struct event_work;
 74
 75	struct mutex lock;
 76	bool connected;
 77	bool active;
 78	bool suspended;
 79
 80	const struct firmware *fw;	/* cdn dp firmware */
 81	unsigned int fw_version;	/* cdn fw version */
 82	bool fw_loaded;
 83
 84	void __iomem *regs;
 85	struct regmap *grf;
 86	struct clk *core_clk;
 87	struct clk *pclk;
 88	struct clk *spdif_clk;
 89	struct clk *grf_clk;
 90	struct reset_control *spdif_rst;
 91	struct reset_control *dptx_rst;
 92	struct reset_control *apb_rst;
 93	struct reset_control *core_rst;
 94	struct audio_info audio_info;
 95	struct video_info video_info;
 96	struct cdn_dp_port *port[MAX_PHY];
 97	u8 ports;
 98	u8 max_lanes;
 99	unsigned int max_rate;
100	u8 lanes;
101	int active_port;
102
103	u8 dpcd[DP_RECEIVER_CAP_SIZE];
104};
105#endif  /* _CDN_DP_CORE_H */