rzg2l_mipi_dsi_regs.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * RZ/G2L MIPI DSI Interface Registers Definitions
  4 *
  5 * Copyright (C) 2022 Renesas Electronics Corporation
  6 */
  7
  8#ifndef __RZG2L_MIPI_DSI_REGS_H__
  9#define __RZG2L_MIPI_DSI_REGS_H__
 10
 11#include <linux/bits.h>
 12
 13/* DPHY Registers */
 14#define DSIDPHYCTRL0			0x00
 15#define DSIDPHYCTRL0_CAL_EN_HSRX_OFS	BIT(16)
 16#define DSIDPHYCTRL0_CMN_MASTER_EN	BIT(8)
 17#define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18	BIT(2)
 18#define DSIDPHYCTRL0_EN_LDO1200		BIT(1)
 19#define DSIDPHYCTRL0_EN_BGR		BIT(0)
 20
 21#define DSIDPHYTIM0			0x04
 22#define DSIDPHYTIM0_TCLK_MISS(x)	((x) << 24)
 23#define DSIDPHYTIM0_T_INIT(x)		((x) << 0)
 24
 25#define DSIDPHYTIM1			0x08
 26#define DSIDPHYTIM1_THS_PREPARE(x)	((x) << 24)
 27#define DSIDPHYTIM1_TCLK_PREPARE(x)	((x) << 16)
 28#define DSIDPHYTIM1_THS_SETTLE(x)	((x) << 8)
 29#define DSIDPHYTIM1_TCLK_SETTLE(x)	((x) << 0)
 30
 31#define DSIDPHYTIM2			0x0c
 32#define DSIDPHYTIM2_TCLK_TRAIL(x)	((x) << 24)
 33#define DSIDPHYTIM2_TCLK_POST(x)	((x) << 16)
 34#define DSIDPHYTIM2_TCLK_PRE(x)		((x) << 8)
 35#define DSIDPHYTIM2_TCLK_ZERO(x)	((x) << 0)
 36
 37#define DSIDPHYTIM3			0x10
 38#define DSIDPHYTIM3_TLPX(x)		((x) << 24)
 39#define DSIDPHYTIM3_THS_EXIT(x)		((x) << 16)
 40#define DSIDPHYTIM3_THS_TRAIL(x)	((x) << 8)
 41#define DSIDPHYTIM3_THS_ZERO(x)		((x) << 0)
 42
 43/* --------------------------------------------------------*/
 44
 45/* Link Status Register */
 46#define LINKSR				0x10
 47#define LINKSR_LPBUSY			BIT(13)
 48#define LINKSR_HSBUSY			BIT(12)
 49#define LINKSR_VICHRUN1			BIT(8)
 50#define LINKSR_SQCHRUN1			BIT(4)
 51#define LINKSR_SQCHRUN0			BIT(0)
 52
 53/* Tx Set Register */
 54#define TXSETR				0x100
 55#define TXSETR_NUMLANECAP		(0x3 << 16)
 56#define TXSETR_DLEN			(1 << 9)
 57#define TXSETR_CLEN			(1 << 8)
 58#define TXSETR_NUMLANEUSE(x)		(((x) & 0x3) << 0)
 59
 60/* HS Clock Set Register */
 61#define HSCLKSETR			0x104
 62#define HSCLKSETR_HSCLKMODE_CONT	(1 << 1)
 63#define HSCLKSETR_HSCLKMODE_NON_CONT	(0 << 1)
 64#define HSCLKSETR_HSCLKRUN_HS		(1 << 0)
 65#define HSCLKSETR_HSCLKRUN_LP		(0 << 0)
 66
 67/* Reset Control Register */
 68#define RSTCR				0x110
 69#define RSTCR_SWRST			BIT(0)
 70#define RSTCR_FCETXSTP			BIT(16)
 71
 72/* Reset Status Register */
 73#define RSTSR				0x114
 74#define RSTSR_DL0DIR			(1 << 15)
 75#define RSTSR_DLSTPST			(0xf << 8)
 76#define RSTSR_SWRSTV1			(1 << 4)
 77#define RSTSR_SWRSTIB			(1 << 3)
 78#define RSTSR_SWRSTAPB			(1 << 2)
 79#define RSTSR_SWRSTLP			(1 << 1)
 80#define RSTSR_SWRSTHS			(1 << 0)
 81
 82/* DSI Set Register */
 83#define DSISETR				0x120
 84#define DSISETR_MRPSZ			GENMASK(15, 0)
 85
 86/* Rx Result Save Slot 0 Register */
 87#define RXRSS0R				0x240
 88#define RXRSS0R_RXPKTDFAIL		BIT(28)
 89#define RXRSS0R_RXFAIL			BIT(27)
 90#define RXRSS0R_RXSUC			BIT(25)
 91#define RXRSS0R_DT			GENMASK(21, 16)
 92#define RXRSS0R_DATA1			GENMASK(15, 8)
 93#define RXRSS0R_DATA0			GENMASK(7, 0)
 94#define RXRSS0R_WC			GENMASK(15, 0) /* Word count for long packet. */
 95
 96/* Clock Lane Stop Time Set Register */
 97#define CLSTPTSETR			0x314
 98#define CLSTPTSETR_CLKKPT(x)		((x) << 24)
 99#define CLSTPTSETR_CLKBFHT(x)		((x) << 16)
100#define CLSTPTSETR_CLKSTPT(x)		((x) << 2)
101
102/* LP Transition Time Set Register */
103#define LPTRNSTSETR			0x318
104#define LPTRNSTSETR_GOLPBKT(x)		((x) << 0)
105
106/* Physical Lane Status Register */
107#define PLSR				0x320
108#define PLSR_CLHS2LP			BIT(27)
109#define PLSR_CLLP2HS			BIT(26)
110
111/* Video-Input Channel 1 Set 0 Register */
112#define VICH1SET0R			0x400
113#define VICH1SET0R_VSEN			BIT(12)
114#define VICH1SET0R_HFPNOLP		BIT(10)
115#define VICH1SET0R_HBPNOLP		BIT(9)
116#define VICH1SET0R_HSANOLP		BIT(8)
117#define VICH1SET0R_VSTPAFT		BIT(1)
118#define VICH1SET0R_VSTART		BIT(0)
119
120/* Video-Input Channel 1 Set 1 Register */
121#define VICH1SET1R			0x404
122#define VICH1SET1R_DLY(x)		(((x) & 0xfff) << 2)
123
124/* Video-Input Channel 1 Status Register */
125#define VICH1SR				0x410
126#define VICH1SR_VIRDY			BIT(3)
127#define VICH1SR_RUNNING			BIT(2)
128#define VICH1SR_STOP			BIT(1)
129#define VICH1SR_START			BIT(0)
130
131/* Video-Input Channel 1 Pixel Packet Set Register */
132#define VICH1PPSETR			0x420
133#define VICH1PPSETR_DT_RGB18		(0x1e << 16)
134#define VICH1PPSETR_DT_RGB18_LS		(0x2e << 16)
135#define VICH1PPSETR_DT_RGB24		(0x3e << 16)
136#define VICH1PPSETR_TXESYNC_PULSE	(1 << 15)
137#define VICH1PPSETR_VC(x)		((x) << 22)
138
139/* Video-Input Channel 1 Vertical Size Set Register */
140#define VICH1VSSETR			0x428
141#define VICH1VSSETR_VACTIVE(x)		(((x) & 0x7fff) << 16)
142#define VICH1VSSETR_VSPOL_LOW		(1 << 15)
143#define VICH1VSSETR_VSPOL_HIGH		(0 << 15)
144#define VICH1VSSETR_VSA(x)		(((x) & 0xfff) << 0)
145
146/* Video-Input Channel 1 Vertical Porch Set Register */
147#define VICH1VPSETR			0x42c
148#define VICH1VPSETR_VFP(x)		(((x) & 0x1fff) << 16)
149#define VICH1VPSETR_VBP(x)		(((x) & 0x1fff) << 0)
150
151/* Video-Input Channel 1 Horizontal Size Set Register */
152#define VICH1HSSETR			0x430
153#define VICH1HSSETR_HACTIVE(x)		(((x) & 0x7fff) << 16)
154#define VICH1HSSETR_HSPOL_LOW		(1 << 15)
155#define VICH1HSSETR_HSPOL_HIGH		(0 << 15)
156#define VICH1HSSETR_HSA(x)		(((x) & 0xfff) << 0)
157
158/* Video-Input Channel 1 Horizontal Porch Set Register */
159#define VICH1HPSETR			0x434
160#define VICH1HPSETR_HFP(x)		(((x) & 0x1fff) << 16)
161#define VICH1HPSETR_HBP(x)		(((x) & 0x1fff) << 0)
162
163/* Sequence Channel 0 Set 0 Register */
164#define SQCH0SET0R			0x5c0
165#define SQCH0SET0R_START		BIT(0)
166
167/* Sequence Channel 0 Status Register */
168#define SQCH0SR				0x5d0
169#define SQCH0SR_ADESFIN			BIT(8)
170
171/* Sequence Channel 0 Status Clear Register */
172#define SQCH0SCR			0x5d4
173#define SQCH0SCR_ADESFIN		BIT(8)
174
175/* Sequence Channel 0 Descriptor 0-A Register */
176#define SQCH0DSC0AR			0x780
177#define SQCH0DSC0AR_NXACT_TERM		0	/* Bit 28 */
178#define SQCH0DSC0AR_BTA			GENMASK(27, 26)
179#define SQCH0DSC0AR_BTA_NONE		0
180#define SQCH0DSC0AR_BTA_NON_READ	1
181#define SQCH0DSC0AR_BTA_READ		2
182#define SQCH0DSC0AR_BTA_ONLY		3
183#define SQCH0DSC0AR_SPD_HIGH		0
184#define SQCH0DSC0AR_SPD_LOW		BIT(25)
185#define SQCH0DSC0AR_FMT_SHORT		0
186#define SQCH0DSC0AR_FMT_LONG		BIT(24)
187#define SQCH0DSC0AR_DT			GENMASK(21, 16)
188#define SQCH0DSC0AR_DATA1		GENMASK(15, 8)
189#define SQCH0DSC0AR_DATA0		GENMASK(7, 0)
190
191/* Sequence Channel 0 Descriptor 0-B Register */
192#define SQCH0DSC0BR			0x784
193#define SQCH0DSC0BR_DTSEL_MEM_SPACE	BIT(24)	/* Use external memory */
194
195/* Sequence Channel 0 Descriptor 0-C Register */
196#define SQCH0DSC0CR			0x788
197#define SQCH0DSC0CR_FINACT		BIT(0)
198#define SQCH0DSC0CR_AUXOP		BIT(22)
199
200/* Sequence Channel 0 Descriptor 0-D Register */
201#define SQCH0DSC0DR			0x78c
202
203#endif /* __RZG2L_MIPI_DSI_REGS_H__ */