rzg2l_du_kms.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * RZ/G2L Display Unit Mode Setting
  4 *
  5 * Copyright (C) 2023 Renesas Electronics Corporation
  6 *
  7 * Based on rcar_du_kms.c
  8 */
  9
 10#include <drm/drm_atomic.h>
 11#include <drm/drm_atomic_helper.h>
 12#include <drm/drm_crtc.h>
 13#include <drm/drm_device.h>
 14#include <drm/drm_framebuffer.h>
 15#include <drm/drm_gem_dma_helper.h>
 16#include <drm/drm_gem_framebuffer_helper.h>
 17#include <drm/drm_managed.h>
 18#include <drm/drm_probe_helper.h>
 19#include <drm/drm_vblank.h>
 20
 21#include <linux/device.h>
 22#include <linux/of.h>
 23#include <linux/of_graph.h>
 24#include <linux/of_platform.h>
 25#include <linux/platform_device.h>
 26
 27#include "rzg2l_du_crtc.h"
 28#include "rzg2l_du_drv.h"
 29#include "rzg2l_du_encoder.h"
 30#include "rzg2l_du_kms.h"
 31#include "rzg2l_du_vsp.h"
 32
 33/* -----------------------------------------------------------------------------
 34 * Format helpers
 35 */
 36
 37static const struct rzg2l_du_format_info rzg2l_du_format_infos[] = {
 38	{
 39		.fourcc = DRM_FORMAT_RGB332,
 40		.v4l2 = V4L2_PIX_FMT_RGB332,
 41		.planes = 1,
 42		.hsub = 1,
 43	}, {
 44		.fourcc = DRM_FORMAT_ARGB4444,
 45		.v4l2 = V4L2_PIX_FMT_ARGB444,
 46		.planes = 1,
 47		.hsub = 1,
 48	}, {
 49		.fourcc = DRM_FORMAT_XRGB4444,
 50		.v4l2 = V4L2_PIX_FMT_XRGB444,
 51		.planes = 1,
 52		.hsub = 1,
 53	}, {
 54		.fourcc = DRM_FORMAT_ARGB1555,
 55		.v4l2 = V4L2_PIX_FMT_ARGB555,
 56		.planes = 1,
 57		.hsub = 1,
 58	}, {
 59		.fourcc = DRM_FORMAT_XRGB1555,
 60		.v4l2 = V4L2_PIX_FMT_XRGB555,
 61		.planes = 1,
 62	}, {
 63		.fourcc = DRM_FORMAT_RGB565,
 64		.v4l2 = V4L2_PIX_FMT_RGB565,
 65		.planes = 1,
 66		.hsub = 1,
 67	}, {
 68		.fourcc = DRM_FORMAT_BGR888,
 69		.v4l2 = V4L2_PIX_FMT_RGB24,
 70		.planes = 1,
 71		.hsub = 1,
 72	}, {
 73		.fourcc = DRM_FORMAT_RGB888,
 74		.v4l2 = V4L2_PIX_FMT_BGR24,
 75		.planes = 1,
 76		.hsub = 1,
 77	}, {
 78		.fourcc = DRM_FORMAT_BGRA8888,
 79		.v4l2 = V4L2_PIX_FMT_ARGB32,
 80		.planes = 1,
 81		.hsub = 1,
 82	}, {
 83		.fourcc = DRM_FORMAT_BGRX8888,
 84		.v4l2 = V4L2_PIX_FMT_XRGB32,
 85		.planes = 1,
 86		.hsub = 1,
 87	}, {
 88		.fourcc = DRM_FORMAT_ARGB8888,
 89		.v4l2 = V4L2_PIX_FMT_ABGR32,
 90		.planes = 1,
 91		.hsub = 1,
 92	}, {
 93		.fourcc = DRM_FORMAT_XRGB8888,
 94		.v4l2 = V4L2_PIX_FMT_XBGR32,
 95		.planes = 1,
 96		.hsub = 1,
 97	}, {
 98		.fourcc = DRM_FORMAT_UYVY,
 99		.v4l2 = V4L2_PIX_FMT_UYVY,
100		.planes = 1,
101		.hsub = 2,
102	}, {
103		.fourcc = DRM_FORMAT_YUYV,
104		.v4l2 = V4L2_PIX_FMT_YUYV,
105		.planes = 1,
106		.hsub = 2,
107	}, {
108		.fourcc = DRM_FORMAT_YVYU,
109		.v4l2 = V4L2_PIX_FMT_YVYU,
110		.planes = 1,
111		.hsub = 2,
112	}, {
113		.fourcc = DRM_FORMAT_NV12,
114		.v4l2 = V4L2_PIX_FMT_NV12M,
115		.planes = 2,
116		.hsub = 2,
117	}, {
118		.fourcc = DRM_FORMAT_NV21,
119		.v4l2 = V4L2_PIX_FMT_NV21M,
120		.planes = 2,
121		.hsub = 2,
122	}, {
123		.fourcc = DRM_FORMAT_NV16,
124		.v4l2 = V4L2_PIX_FMT_NV16M,
125		.planes = 2,
126		.hsub = 2,
127	}, {
128		.fourcc = DRM_FORMAT_NV61,
129		.v4l2 = V4L2_PIX_FMT_NV61M,
130		.planes = 2,
131		.hsub = 2,
132	}, {
133		.fourcc = DRM_FORMAT_YUV420,
134		.v4l2 = V4L2_PIX_FMT_YUV420M,
135		.planes = 3,
136		.hsub = 2,
137	}, {
138		.fourcc = DRM_FORMAT_YVU420,
139		.v4l2 = V4L2_PIX_FMT_YVU420M,
140		.planes = 3,
141		.hsub = 2,
142	}, {
143		.fourcc = DRM_FORMAT_YUV422,
144		.v4l2 = V4L2_PIX_FMT_YUV422M,
145		.planes = 3,
146		.hsub = 2,
147	}, {
148		.fourcc = DRM_FORMAT_YVU422,
149		.v4l2 = V4L2_PIX_FMT_YVU422M,
150		.planes = 3,
151		.hsub = 2,
152	}, {
153		.fourcc = DRM_FORMAT_YUV444,
154		.v4l2 = V4L2_PIX_FMT_YUV444M,
155		.planes = 3,
156		.hsub = 1,
157	}, {
158		.fourcc = DRM_FORMAT_YVU444,
159		.v4l2 = V4L2_PIX_FMT_YVU444M,
160		.planes = 3,
161		.hsub = 1,
162	}
163};
164
165const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc)
166{
167	unsigned int i;
168
169	for (i = 0; i < ARRAY_SIZE(rzg2l_du_format_infos); ++i) {
170		if (rzg2l_du_format_infos[i].fourcc == fourcc)
171			return &rzg2l_du_format_infos[i];
172	}
173
174	return NULL;
175}
176
177/* -----------------------------------------------------------------------------
178 * Frame buffer
179 */
180
181int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev,
182			 struct drm_mode_create_dumb *args)
183{
184	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
185	unsigned int align = 16 * args->bpp / 8;
186
187	args->pitch = roundup(min_pitch, align);
188
189	return drm_gem_dma_dumb_create_internal(file, dev, args);
190}
191
192static struct drm_framebuffer *
193rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
194		   const struct drm_format_info *info,
195		   const struct drm_mode_fb_cmd2 *mode_cmd)
196{
197	const struct rzg2l_du_format_info *format;
198	unsigned int max_pitch;
199
200	format = rzg2l_du_format_info(mode_cmd->pixel_format);
201	if (!format) {
202		dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
203			&mode_cmd->pixel_format);
204		return ERR_PTR(-EINVAL);
205	}
206
207	/*
208	 * On RZ/G2L the memory interface is handled by the VSP that limits the
209	 * pitch to 65535 bytes.
210	 */
211	max_pitch = 65535;
212	if (mode_cmd->pitches[0] > max_pitch) {
213		dev_dbg(dev->dev, "invalid pitch value %u\n",
214			mode_cmd->pitches[0]);
215		return ERR_PTR(-EINVAL);
216	}
217
218	return drm_gem_fb_create(dev, file_priv, info, mode_cmd);
219}
220
221/* -----------------------------------------------------------------------------
222 * Initialization
223 */
224
225static const struct drm_mode_config_helper_funcs rzg2l_du_mode_config_helper = {
226	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
227};
228
229static const struct drm_mode_config_funcs rzg2l_du_mode_config_funcs = {
230	.fb_create = rzg2l_du_fb_create,
231	.atomic_check = drm_atomic_helper_check,
232	.atomic_commit = drm_atomic_helper_commit,
233};
234
235static int rzg2l_du_encoders_init_one(struct rzg2l_du_device *rcdu,
236				      enum rzg2l_du_output output,
237				      struct of_endpoint *ep)
238{
239	struct device_node *entity;
240	int ret;
241
242	/* Locate the connected entity and initialize the encoder. */
243	entity = of_graph_get_remote_port_parent(ep->local_node);
244	if (!entity) {
245		dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
246			ep->local_node);
247		return -ENODEV;
248	}
249
250	if (!of_device_is_available(entity)) {
251		dev_dbg(rcdu->dev,
252			"connected entity %pOF is disabled, skipping\n",
253			entity);
254		of_node_put(entity);
255		return -ENODEV;
256	}
257
258	ret = rzg2l_du_encoder_init(rcdu, output, entity);
259	if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
260		dev_warn(rcdu->dev,
261			 "failed to initialize encoder %pOF on output %s (%d), skipping\n",
262			 entity, rzg2l_du_output_name(output), ret);
263
264	of_node_put(entity);
265
266	return ret;
267}
268
269static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu)
270{
271	struct device_node *np = rcdu->dev->of_node;
272	struct device_node *ep_node;
273	unsigned int num_encoders = 0;
274
275	/*
276	 * Iterate over the endpoints and create one encoder for each output
277	 * pipeline.
278	 */
279	for_each_endpoint_of_node(np, ep_node) {
280		enum rzg2l_du_output output;
281		struct of_endpoint ep;
282		unsigned int i;
283		int ret;
284
285		ret = of_graph_parse_endpoint(ep_node, &ep);
286		if (ret < 0) {
287			of_node_put(ep_node);
288			return ret;
289		}
290
291		/* Find the output route corresponding to the port number. */
292		for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) {
293			if (rcdu->info->routes[i].possible_outputs &&
294			    rcdu->info->routes[i].port == ep.port) {
295				output = i;
296				break;
297			}
298		}
299
300		if (i == RZG2L_DU_OUTPUT_MAX) {
301			dev_warn(rcdu->dev,
302				 "port %u references unexisting output, skipping\n",
303				 ep.port);
304			continue;
305		}
306
307		/* Process the output pipeline. */
308		ret = rzg2l_du_encoders_init_one(rcdu, output, &ep);
309		if (ret < 0) {
310			if (ret == -EPROBE_DEFER) {
311				of_node_put(ep_node);
312				return ret;
313			}
314
315			continue;
316		}
317
318		num_encoders++;
319	}
320
321	return num_encoders;
322}
323
324static int rzg2l_du_vsps_init(struct rzg2l_du_device *rcdu)
325{
326	const struct device_node *np = rcdu->dev->of_node;
327	const char *vsps_prop_name = "renesas,vsps";
328	struct of_phandle_args args;
329	struct {
330		struct device_node *np;
331		unsigned int crtcs_mask;
332	} vsps[RZG2L_DU_MAX_VSPS] = { { NULL, }, };
333	unsigned int vsps_count = 0;
334	unsigned int cells;
335	unsigned int i;
336	int ret;
337
338	/*
339	 * First parse the DT vsps property to populate the list of VSPs. Each
340	 * entry contains a pointer to the VSP DT node and a bitmask of the
341	 * connected DU CRTCs.
342	 */
343	ret = of_property_count_u32_elems(np, vsps_prop_name);
344	cells = ret / rcdu->num_crtcs - 1;
345	if (cells != 1)
346		return -EINVAL;
347
348	for (i = 0; i < rcdu->num_crtcs; ++i) {
349		unsigned int j;
350
351		ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
352						       cells, i, &args);
353		if (ret < 0)
354			goto done;
355
356		/*
357		 * Add the VSP to the list or update the corresponding existing
358		 * entry if the VSP has already been added.
359		 */
360		for (j = 0; j < vsps_count; ++j) {
361			if (vsps[j].np == args.np)
362				break;
363		}
364
365		if (j < vsps_count)
366			of_node_put(args.np);
367		else
368			vsps[vsps_count++].np = args.np;
369
370		vsps[j].crtcs_mask |= BIT(i);
371
372		/*
373		 * Store the VSP pointer and pipe index in the CRTC. If the
374		 * second cell of the 'renesas,vsps' specifier isn't present,
375		 * default to 0.
376		 */
377		rcdu->crtcs[i].vsp = &rcdu->vsps[j];
378		rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
379	}
380
381	/*
382	 * Then initialize all the VSPs from the node pointers and CRTCs bitmask
383	 * computed previously.
384	 */
385	for (i = 0; i < vsps_count; ++i) {
386		struct rzg2l_du_vsp *vsp = &rcdu->vsps[i];
387
388		vsp->index = i;
389		vsp->dev = rcdu;
390
391		ret = rzg2l_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
392		if (ret)
393			goto done;
394	}
395
396done:
397	for (i = 0; i < ARRAY_SIZE(vsps); ++i)
398		of_node_put(vsps[i].np);
399
400	return ret;
401}
402
403int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)
404{
405	struct drm_device *dev = &rcdu->ddev;
406	struct drm_encoder *encoder;
407	unsigned int num_encoders;
408	int ret;
409
410	ret = drmm_mode_config_init(dev);
411	if (ret)
412		return ret;
413
414	dev->mode_config.min_width = 0;
415	dev->mode_config.min_height = 0;
416	dev->mode_config.normalize_zpos = true;
417	dev->mode_config.funcs = &rzg2l_du_mode_config_funcs;
418	dev->mode_config.helper_private = &rzg2l_du_mode_config_helper;
419
420	/*
421	 * The RZ DU was designed to support a frame size of 1920x1200 (landscape)
422	 * or 1200x1920 (portrait).
423	 */
424	dev->mode_config.max_width = 1920;
425	dev->mode_config.max_height = 1920;
426
427	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
428
429	/*
430	 * Initialize vertical blanking interrupts handling. Start with vblank
431	 * disabled for all CRTCs.
432	 */
433	ret = drm_vblank_init(dev, rcdu->num_crtcs);
434	if (ret < 0)
435		return ret;
436
437	/* Initialize the compositors. */
438	ret = rzg2l_du_vsps_init(rcdu);
439	if (ret < 0)
440		return ret;
441
442	/* Create the CRTCs. */
443	ret = rzg2l_du_crtc_create(rcdu);
444	if (ret < 0)
445		return ret;
446
447	/* Initialize the encoders. */
448	ret = rzg2l_du_encoders_init(rcdu);
449	if (ret < 0)
450		return dev_err_probe(rcdu->dev, ret,
451				     "failed to initialize encoders\n");
452
453	if (ret == 0) {
454		dev_err(rcdu->dev, "error: no encoder could be initialized\n");
455		return -EINVAL;
456	}
457
458	num_encoders = ret;
459
460	/*
461	 * Set the possible CRTCs and possible clones. There's always at least
462	 * one way for all encoders to clone each other, set all bits in the
463	 * possible clones field.
464	 */
465	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
466		struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
467		const struct rzg2l_du_output_routing *route =
468			&rcdu->info->routes[renc->output];
469
470		encoder->possible_crtcs = route->possible_outputs;
471		encoder->possible_clones = (1 << num_encoders) - 1;
472	}
473
474	drm_mode_config_reset(dev);
475
476	drm_kms_helper_poll_init(dev);
477
478	return 0;
479}