rcar_mipi_dsi_regs.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * R-Car MIPI DSI Interface Registers Definitions
  4 *
  5 * Copyright (C) 2020 Renesas Electronics Corporation
  6 */
  7
  8#ifndef __RCAR_MIPI_DSI_REGS_H__
  9#define __RCAR_MIPI_DSI_REGS_H__
 10
 11#define LINKSR				0x010
 12#define LINKSR_LPBUSY			BIT_U32(1)
 13#define LINKSR_HSBUSY			BIT_U32(0)
 14
 15#define TXSETR				0x100
 16#define TXSETR_LANECNT_MASK		GENMASK_U32(1, 0)
 17
 18/*
 19 * DSI Command Transfer Registers
 20 */
 21#define TXCMSETR			0x110
 22#define TXCMSETR_SPDTYP			BIT_U32(8)	/* 0:HS 1:LP */
 23#define TXCMSETR_LPPDACC		BIT_U32(0)
 24#define TXCMCR				0x120
 25#define TXCMCR_BTATYP			BIT_U32(2)
 26#define TXCMCR_BTAREQ			BIT_U32(1)
 27#define TXCMCR_TXREQ			BIT_U32(0)
 28#define TXCMSR				0x130
 29#define TXCMSR_CLSNERR			BIT_U32(18)
 30#define TXCMSR_AXIERR			BIT_U32(16)
 31#define TXCMSR_TXREQEND			BIT_U32(0)
 32#define TXCMSCR				0x134
 33#define TXCMSCR_CLSNERR			BIT_U32(18)
 34#define TXCMSCR_AXIERR			BIT_U32(16)
 35#define TXCMSCR_TXREQEND		BIT_U32(0)
 36#define TXCMIER				0x138
 37#define TXCMIER_CLSNERR			BIT_U32(18)
 38#define TXCMIER_AXIERR			BIT_U32(16)
 39#define TXCMIER_TXREQEND		BIT_U32(0)
 40#define TXCMADDRSET0R			0x140
 41#define TXCMPHDR			0x150
 42#define TXCMPHDR_FMT			BIT_U32(24)	/* 0:SP 1:LP */
 43#define TXCMPHDR_VC_MASK		GENMASK_U32(23, 22)
 44#define TXCMPHDR_VC(n)			FIELD_PREP(TXCMPHDR_VC_MASK, (n))
 45#define TXCMPHDR_DT_MASK		GENMASK_U32(21, 16)
 46#define TXCMPHDR_DT(n)			FIELD_PREP(TXCMPHDR_DT_MASK, (n))
 47#define TXCMPHDR_DATA1_MASK		GENMASK_U32(15, 8)
 48#define TXCMPHDR_DATA1(n)		FIELD_PREP(TXCMPHDR_DATA1_MASK, (n))
 49#define TXCMPHDR_DATA0_MASK		GENMASK_U32(7, 0)
 50#define TXCMPHDR_DATA0(n)		FIELD_PREP(TXCMPHDR_DATA0_MASK, (n))
 51#define TXCMPPD0R			0x160
 52#define TXCMPPD1R			0x164
 53#define TXCMPPD2R			0x168
 54#define TXCMPPD3R			0x16c
 55
 56#define RXSETR				0x200
 57#define RXSETR_CRCEN_MASK		GENMASK_U32(27, 24)
 58#define RXSETR_ECCEN_MASK		GENMASK_U32(19, 16)
 59#define RXPSETR				0x210
 60#define RXPSETR_LPPDACC			BIT_U32(0)
 61#define RXPSR				0x220
 62#define RXPSR_ECCERR1B			BIT_U32(28)
 63#define RXPSR_UEXTRGERR			BIT_U32(25)
 64#define RXPSR_RESPTOERR			BIT_U32(24)
 65#define RXPSR_OVRERR			BIT_U32(23)
 66#define RXPSR_AXIERR			BIT_U32(22)
 67#define RXPSR_CRCERR			BIT_U32(21)
 68#define RXPSR_WCERR			BIT_U32(20)
 69#define RXPSR_UEXDTERR			BIT_U32(19)
 70#define RXPSR_UEXPKTERR			BIT_U32(18)
 71#define RXPSR_ECCERR			BIT_U32(17)
 72#define RXPSR_MLFERR			BIT_U32(16)
 73#define RXPSR_RCVACK			BIT_U32(14)
 74#define RXPSR_RCVEOT			BIT_U32(10)
 75#define RXPSR_RCVAKE			BIT_U32(9)
 76#define RXPSR_RCVRESP			BIT_U32(8)
 77#define RXPSR_BTAREQEND			BIT_U32(0)
 78#define RXPSCR				0x224
 79#define RXPSCR_ECCERR1B			BIT_U32(28)
 80#define RXPSCR_UEXTRGERR		BIT_U32(25)
 81#define RXPSCR_RESPTOERR		BIT_U32(24)
 82#define RXPSCR_OVRERR			BIT_U32(23)
 83#define RXPSCR_AXIERR			BIT_U32(22)
 84#define RXPSCR_CRCERR			BIT_U32(21)
 85#define RXPSCR_WCERR			BIT_U32(20)
 86#define RXPSCR_UEXDTERR			BIT_U32(19)
 87#define RXPSCR_UEXPKTERR		BIT_U32(18)
 88#define RXPSCR_ECCERR			BIT_U32(17)
 89#define RXPSCR_MLFERR			BIT_U32(16)
 90#define RXPSCR_RCVACK			BIT_U32(14)
 91#define RXPSCR_RCVEOT			BIT_U32(10)
 92#define RXPSCR_RCVAKE			BIT_U32(9)
 93#define RXPSCR_RCVRESP			BIT_U32(8)
 94#define RXPSCR_BTAREQEND		BIT_U32(0)
 95#define RXPIER				0x228
 96#define RXPIER_ECCERR1B			BIT_U32(28)
 97#define RXPIER_UEXTRGERR		BIT_U32(25)
 98#define RXPIER_RESPTOERR		BIT_U32(24)
 99#define RXPIER_OVRERR			BIT_U32(23)
100#define RXPIER_AXIERR			BIT_U32(22)
101#define RXPIER_CRCERR			BIT_U32(21)
102#define RXPIER_WCERR			BIT_U32(20)
103#define RXPIER_UEXDTERR			BIT_U32(19)
104#define RXPIER_UEXPKTERR		BIT_U32(18)
105#define RXPIER_ECCERR			BIT_U32(17)
106#define RXPIER_MLFERR			BIT_U32(16)
107#define RXPIER_RCVACK			BIT_U32(14)
108#define RXPIER_RCVEOT			BIT_U32(10)
109#define RXPIER_RCVAKE			BIT_U32(9)
110#define RXPIER_RCVRESP			BIT_U32(8)
111#define RXPIER_BTAREQEND		BIT_U32(0)
112#define RXPADDRSET0R			0x230
113#define RXPSIZESETR			0x238
114#define RXPSIZESETR_SIZE_MASK		GENMASK_U32(6, 3)
115#define RXPHDR				0x240
116#define RXPHDR_FMT			BIT_U32(24)	/* 0:SP 1:LP */
117#define RXPHDR_VC_MASK			GENMASK_U32(23, 22)
118#define RXPHDR_DT_MASK			GENMASK_U32(21, 16)
119#define RXPHDR_DATA1_MASK		GENMASK_U32(15, 8)
120#define RXPHDR_DATA0_MASK		GENMASK_U32(7, 0)
121#define RXPPD0R				0x250
122#define RXPPD1R				0x254
123#define RXPPD2R				0x258
124#define RXPPD3R				0x25c
125#define AKEPR				0x300
126#define AKEPR_VC_MASK			GENMASK_U32(23, 22)
127#define AKEPR_DT_MASK			GENMASK_U32(21, 16)
128#define AKEPR_ERRRPT_MASK		GENMASK_U32(15, 0)
129#define RXRESPTOSETR			0x400
130#define TACR				0x500
131#define TASR				0x510
132#define TASCR				0x514
133#define TAIER				0x518
134#define TOSR				0x610
135#define TOSR_TATO			BIT_U32(2)
136#define TOSR_LRXHTO			BIT_U32(1)
137#define TOSR_HRXTO			BIT_U32(0)
138#define TOSCR				0x614
139#define TOSCR_TATO			BIT_U32(2)
140#define TOSCR_LRXHTO			BIT_U32(1)
141#define TOSCR_HRXTO			BIT_U32(0)
142
143/*
144 * Video Mode Register
145 */
146#define TXVMSETR			0x180
147#define TXVMSETR_SYNSEQ_EVENTS		BIT_U32(16) /* 0:Pulses 1:Events */
148#define TXVMSETR_VSTPM			BIT_U32(15)
149#define TXVMSETR_PIXWDTH_MASK		GENMASK_U32(10, 8)
150#define TXVMSETR_PIXWDTH		BIT_U32(8) /* Only allowed value */
151#define TXVMSETR_VSEN			BIT_U32(4)
152#define TXVMSETR_HFPBPEN		BIT_U32(2)
153#define TXVMSETR_HBPBPEN		BIT_U32(1)
154#define TXVMSETR_HSABPEN		BIT_U32(0)
155
156#define TXVMCR				0x190
157#define TXVMCR_VFCLR			BIT_U32(12)
158#define TXVMCR_EN_VIDEO			BIT_U32(0)
159
160#define TXVMSR				0x1a0
161#define TXVMSR_STR			BIT_U32(16)
162#define TXVMSR_VFRDY			BIT_U32(12)
163#define TXVMSR_ACT			BIT_U32(8)
164#define TXVMSR_RDY			BIT_U32(0)
165
166#define TXVMSCR				0x1a4
167#define TXVMSCR_STR			BIT_U32(16)
168
169#define TXVMPSPHSETR			0x1c0
170#define TXVMPSPHSETR_DT_MASK		(0x3f << 16)
171#define TXVMPSPHSETR_DT_RGB16		FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x0e)
172#define TXVMPSPHSETR_DT_RGB18		FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x1e)
173#define TXVMPSPHSETR_DT_RGB18_LS	FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2e)
174#define TXVMPSPHSETR_DT_RGB24		FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x3e)
175#define TXVMPSPHSETR_DT_YCBCR16		FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c)
176
177#define TXVMVPRMSET0R			0x1d0
178#define TXVMVPRMSET0R_HSPOL_LOW		BIT_U32(17) /* 0:High 1:Low */
179#define TXVMVPRMSET0R_VSPOL_LOW		BIT_U32(16) /* 0:High 1:Low */
180#define TXVMVPRMSET0R_CSPC_YCbCr	BIT_U32(4) /* 0:RGB 1:YCbCr */
181#define TXVMVPRMSET0R_BPP_MASK		GENMASK_U32(2, 0)
182#define TXVMVPRMSET0R_BPP_16		FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0)
183#define TXVMVPRMSET0R_BPP_18		FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1)
184#define TXVMVPRMSET0R_BPP_24		FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2)
185
186#define TXVMVPRMSET1R			0x1d4
187#define TXVMVPRMSET1R_VACTIVE_MASK	GENMASK_U32(30, 16)
188#define TXVMVPRMSET1R_VACTIVE(n)	FIELD_PREP(TXVMVPRMSET1R_VACTIVE_MASK, (n))
189#define TXVMVPRMSET1R_VSA_MASK		GENMASK_U32(11, 0)
190#define TXVMVPRMSET1R_VSA(n)		FIELD_PREP(TXVMVPRMSET1R_VSA_MASK, (n))
191
192#define TXVMVPRMSET2R			0x1d8
193#define TXVMVPRMSET2R_VFP_MASK		GENMASK_U32(28, 16)
194#define TXVMVPRMSET2R_VFP(n)		FIELD_PREP(TXVMVPRMSET2R_VFP_MASK, (n))
195#define TXVMVPRMSET2R_VBP_MASK		GENMASK_U32(12, 0)
196#define TXVMVPRMSET2R_VBP(n)		FIELD_PREP(TXVMVPRMSET2R_VBP_MASK, (n))
197
198#define TXVMVPRMSET3R			0x1dc
199#define TXVMVPRMSET3R_HACTIVE_MASK	GENMASK_U32(30, 16)
200#define TXVMVPRMSET3R_HACTIVE(n)	FIELD_PREP(TXVMVPRMSET3R_HACTIVE_MASK, (n))
201#define TXVMVPRMSET3R_HSA_MASK		GENMASK_U32(11, 0)
202#define TXVMVPRMSET3R_HSA(n)		FIELD_PREP(TXVMVPRMSET3R_HSA_MASK, (n))
203
204#define TXVMVPRMSET4R			0x1e0
205#define TXVMVPRMSET4R_HFP_MASK		GENMASK_U32(28, 16)
206#define TXVMVPRMSET4R_HFP(n)		FIELD_PREP(TXVMVPRMSET4R_HFP_MASK, (n))
207#define TXVMVPRMSET4R_HBP_MASK		GENMASK_U32(12, 0)
208#define TXVMVPRMSET4R_HBP(n)		FIELD_PREP(TXVMVPRMSET4R_HBP_MASK, (n))
209
210/*
211 * PHY-Protocol Interface (PPI) Registers
212 */
213#define PPISETR				0x700
214#define PPISETR_DLEN_MASK		GENMASK_U32(3, 0)
215#define PPISETR_CLEN			BIT_U32(8)
216
217#define PPICLCR				0x710
218#define PPICLCR_TXREQHS			BIT_U32(8)
219#define PPICLCR_TXULPSEXT		BIT_U32(1)
220#define PPICLCR_TXULPSCLK		BIT_U32(0)
221
222#define PPICLSR				0x720
223#define PPICLSR_HSTOLP			BIT_U32(27)
224#define PPICLSR_TOHS			BIT_U32(26)
225#define PPICLSR_STPST			BIT_U32(0)
226
227#define PPICLSCR			0x724
228#define PPICLSCR_HSTOLP			BIT_U32(27)
229#define PPICLSCR_TOHS			BIT_U32(26)
230
231#define PPIDL0SR			0x740
232#define PPIDL0SR_DIR			BIT_U32(10)
233#define PPIDL0SR_STPST			BIT_U32(6)
234
235#define PPIDLSR				0x760
236#define PPIDLSR_STPST			GENMASK_U32(3, 0)
237
238/*
239 * Clocks registers
240 */
241#define LPCLKSET			0x1000
242#define LPCLKSET_CKEN			BIT_U32(8)
243#define LPCLKSET_LPCLKDIV_MASK		GENMASK_U32(5, 0)
244
245#define CFGCLKSET			0x1004
246#define CFGCLKSET_CKEN			BIT_U32(8)
247#define CFGCLKSET_CFGCLKDIV_MASK	GENMASK_U32(5, 0)
248
249#define DOTCLKDIV			0x1008
250#define DOTCLKDIV_CKEN			BIT_U32(8)
251#define DOTCLKDIV_DOTCLKDIV_MASK	GENMASK_U32(5, 0)
252
253#define VCLKSET				0x100c
254#define VCLKSET_CKEN			BIT_U32(16)
255#define VCLKSET_COLOR_YCC		BIT_U32(8) /* 0:RGB 1:YCbCr */
256#define VCLKSET_DIV_V3U_MASK		GENMASK_U32(5, 4)
257#define VCLKSET_DIV_V3U(n)		FIELD_PREP(VCLKSET_DIV_V3U_MASK, (n))
258#define VCLKSET_DIV_V4H_MASK		GENMASK_U32(6, 4)
259#define VCLKSET_DIV_V4H(n)		FIELD_PREP(VCLKSET_DIV_V4H_MASK, (n))
260#define VCLKSET_BPP_MASK		GENMASK_U32(3, 2)
261#define VCLKSET_BPP_16			FIELD_PREP(VCLKSET_BPP_MASK, 0)
262#define VCLKSET_BPP_18			FIELD_PREP(VCLKSET_BPP_MASK, 1)
263#define VCLKSET_BPP_18L			FIELD_PREP(VCLKSET_BPP_MASK, 2)
264#define VCLKSET_BPP_24			FIELD_PREP(VCLKSET_BPP_MASK, 3)
265#define VCLKSET_LANE_MASK		GENMASK_U32(1, 0)
266#define VCLKSET_LANE(n)			FIELD_PREP(VCLKSET_LANE_MASK, (n))
267
268#define VCLKEN				0x1010
269#define VCLKEN_CKEN			BIT_U32(0)
270
271#define PHYSETUP			0x1014
272#define PHYSETUP_HSFREQRANGE_MASK	GENMASK_U32(22, 16)
273#define PHYSETUP_HSFREQRANGE(n)		FIELD_PREP(PHYSETUP_HSFREQRANGE_MASK, (n))
274#define PHYSETUP_CFGCLKFREQRANGE_MASK	GENMASK_U32(13, 8)
275#define PHYSETUP_SHUTDOWNZ		BIT_U32(1)
276#define PHYSETUP_RSTZ			BIT_U32(0)
277
278#define CLOCKSET1			0x101c
279#define CLOCKSET1_LOCK_PHY		BIT_U32(17)
280#define CLOCKSET1_CLKSEL		BIT_U32(8)
281#define CLOCKSET1_CLKINSEL_MASK		GENMASK_U32(3, 2)
282#define CLOCKSET1_CLKINSEL_EXTAL	FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 0)
283#define CLOCKSET1_CLKINSEL_DIG		FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 1)
284#define CLOCKSET1_CLKINSEL_DU		FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 2)
285#define CLOCKSET1_SHADOW_CLEAR		BIT_U32(1)
286#define CLOCKSET1_UPDATEPLL		BIT_U32(0)
287
288#define CLOCKSET2			0x1020
289#define CLOCKSET2_M_MASK		GENMASK_U32(27, 16)
290#define CLOCKSET2_M(n)			FIELD_PREP(CLOCKSET2_M_MASK, (n))
291#define CLOCKSET2_VCO_CNTRL_MASK	GENMASK_U32(13, 8)
292#define CLOCKSET2_VCO_CNTRL(n)		FIELD_PREP(CLOCKSET2_VCO_CNTRL_MASK, (n))
293#define CLOCKSET2_N_MASK		GENMASK_U32(3, 0)
294#define CLOCKSET2_N(n)			FIELD_PREP(CLOCKSET2_N_MASK, (n))
295
296#define CLOCKSET3			0x1024
297#define CLOCKSET3_PROP_CNTRL_MASK	GENMASK_U32(29, 24)
298#define CLOCKSET3_PROP_CNTRL(n)	FIELD_PREP(CLOCKSET3_PROP_CNTRL_MASK, (n))
299#define CLOCKSET3_INT_CNTRL_MASK	GENMASK_U32(21, 16)
300#define CLOCKSET3_INT_CNTRL(n)		FIELD_PREP(CLOCKSET3_INT_CNTRL_MASK, (n))
301#define CLOCKSET3_CPBIAS_CNTRL_MASK	GENMASK_U32(14, 8)
302#define CLOCKSET3_CPBIAS_CNTRL(n)	FIELD_PREP(CLOCKSET3_CPBIAS_CNTRL_MASK, (n))
303#define CLOCKSET3_GMP_CNTRL_MASK	GENMASK_U32(1, 0)
304#define CLOCKSET3_GMP_CNTRL(n)		FIELD_PREP(CLOCKSET3_GMP_CNTRL_MASK, (n))
305
306#define PHTW				0x1034
307#define PHTW_DWEN			BIT_U32(24)
308#define PHTW_TESTDIN_DATA_MASK		GENMASK_U32(23, 16)
309#define PHTW_CWEN			BIT_U32(8)
310#define PHTW_TESTDIN_CODE_MASK		GENMASK_U32(7, 0)
311
312#define PHTR				0x1038
313#define PHTR_TESTDOUT			GENMASK_U32(23, 16)
314#define PHTR_TESTDOUT_TEST		BIT_U32(16)
315
316#define PHTC				0x103c
317#define PHTC_TESTCLR			BIT_U32(0)
318
319#endif /* __RCAR_MIPI_DSI_REGS_H__ */