rcar_du_group.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * R-Car Display Unit Channels Pair
  4 *
  5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
  6 *
  7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
  8 */
  9
 10/*
 11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
 12 * unit, timings generator, ...) and device-global resources (start/stop
 13 * control, planes, ...) shared between the two CRTCs.
 14 *
 15 * The R8A7790 introduced a third CRTC with its own set of global resources.
 16 * This would be modeled as two separate DU device instances if it wasn't for
 17 * a handful or resources that are shared between the three CRTCs (mostly
 18 * related to input and output routing). For this reason the R8A7790 DU must be
 19 * modeled as a single device with three CRTCs, two sets of "semi-global"
 20 * resources, and a few device-global resources.
 21 *
 22 * The rcar_du_group object is a driver specific object, without any real
 23 * counterpart in the DU documentation, that models those semi-global resources.
 24 */
 25
 26#include <linux/clk.h>
 27#include <linux/io.h>
 28
 29#include "rcar_du_drv.h"
 30#include "rcar_du_group.h"
 31#include "rcar_du_regs.h"
 32
 33u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
 34{
 35	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
 36}
 37
 38void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
 39{
 40	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
 41}
 42
 43static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
 44{
 45	u32 defr6 = DEFR6_CODE;
 46
 47	if (rgrp->channels_mask & BIT(0))
 48		defr6 |= DEFR6_ODPM02_DISP;
 49
 50	if (rgrp->channels_mask & BIT(1))
 51		defr6 |= DEFR6_ODPM12_DISP;
 52
 53	rcar_du_group_write(rgrp, DEFR6, defr6);
 54}
 55
 56static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
 57{
 58	struct rcar_du_device *rcdu = rgrp->dev;
 59	u32 defr8 = DEFR8_CODE;
 60
 61	if (rcdu->info->gen < 3) {
 62		defr8 |= DEFR8_DEFE8;
 63
 64		/*
 65		 * On Gen2 the DEFR8 register for the first group also controls
 66		 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
 67		 * DU instances that support it.
 68		 */
 69		if (rgrp->index == 0) {
 70			defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
 71			if (rgrp->dev->vspd1_sink == 2)
 72				defr8 |= DEFR8_VSCS;
 73		}
 74	} else {
 75		/*
 76		 * On Gen3 VSPD routing can't be configured, and DPAD routing
 77		 * is set in the group corresponding to the DPAD output (no Gen3
 78		 * SoC has multiple DPAD sources belonging to separate groups).
 79		 */
 80		if (rgrp->index == rcdu->dpad0_source / 2)
 81			defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
 82	}
 83
 84	rcar_du_group_write(rgrp, DEFR8, defr8);
 85}
 86
 87static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
 88{
 89	struct rcar_du_device *rcdu = rgrp->dev;
 90	struct rcar_du_crtc *rcrtc;
 91	unsigned int num_crtcs = 0;
 92	unsigned int i;
 93	u32 didsr;
 94
 95	/*
 96	 * Configure input dot clock routing with a hardcoded configuration. If
 97	 * the DU channel can use the LVDS encoder output clock as the dot
 98	 * clock, do so. Otherwise route DU_DOTCLKINn signal to DUn.
 99	 *
100	 * Each channel can then select between the dot clock configured here
101	 * and the clock provided by the CPG through the ESCR register.
102	 */
103	if (rcdu->info->gen < 3 && rgrp->index == 0) {
104		/*
105		 * On Gen2 a single register in the first group controls dot
106		 * clock selection for all channels.
107		 */
108		rcrtc = rcdu->crtcs;
109		num_crtcs = rcdu->num_crtcs;
110	} else if ((rcdu->info->gen == 3 && rgrp->num_crtcs > 1) ||
111		   rcdu->info->gen == 4) {
112		/*
113		 * On Gen3 dot clocks are setup through per-group registers,
114		 * only available when the group has two channels.
115		 * On Gen4 the registers are there for single channel too.
116		 */
117		rcrtc = &rcdu->crtcs[rgrp->index * 2];
118		num_crtcs = rgrp->num_crtcs;
119	}
120
121	if (!num_crtcs)
122		return;
123
124	didsr = DIDSR_CODE;
125	for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
126		if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
127			didsr |= DIDSR_LDCS_LVDS0(i)
128			      |  DIDSR_PDCS_CLK(i, 0);
129		else if (rcdu->info->dsi_clk_mask & BIT(rcrtc->index))
130			didsr |= DIDSR_LDCS_DSI(i);
131		else
132			didsr |= DIDSR_LDCS_DCLKIN(i)
133			      |  DIDSR_PDCS_CLK(i, 0);
134	}
135
136	rcar_du_group_write(rgrp, DIDSR, didsr);
137}
138
139static void rcar_du_group_setup(struct rcar_du_group *rgrp)
140{
141	struct rcar_du_device *rcdu = rgrp->dev;
142	u32 defr7 = DEFR7_CODE;
143	u32 dorcr;
144
145	/* Enable extended features */
146	rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
147	if (rcdu->info->gen < 3) {
148		rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
149		rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
150		rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
151	}
152	rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
153
154	if (rcdu->info->gen < 4)
155		rcar_du_group_setup_pins(rgrp);
156
157	if (rcdu->info->gen < 4) {
158		/*
159		 * TODO: Handle routing of the DU output to CMM dynamically, as
160		 * we should bypass CMM completely when no color management
161		 * feature is used.
162		 */
163		defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |
164			 (rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);
165		rcar_du_group_write(rgrp, DEFR7, defr7);
166	}
167
168	if (rcdu->info->gen >= 2) {
169		if (rcdu->info->gen < 4)
170			rcar_du_group_setup_defr8(rgrp);
171		rcar_du_group_setup_didsr(rgrp);
172	}
173
174	if (rcdu->info->gen >= 3)
175		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
176
177	/*
178	 * Use DS1PR and DS2PR to configure planes priorities and connects the
179	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
180	 *
181	 * Groups that have a single channel have a hardcoded configuration. On
182	 * Gen3 and newer, the documentation requires PG1T, DK1S and PG1D_DS1 to
183	 * always be set in this case.
184	 */
185	dorcr = DORCR_PG0D_DS0 | DORCR_DPRS;
186	if (rcdu->info->gen >= 3 && rgrp->num_crtcs == 1)
187		dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1;
188	rcar_du_group_write(rgrp, DORCR, dorcr);
189
190	/*
191	 * DPTSR is used to select the source for the planes of a group. The
192	 * first source is chosen by writing 0 to the respective bits, and this
193	 * is always the default value of the register. In other words, writing
194	 * DPTSR is only needed if the SoC supports choosing the second source.
195	 *
196	 * The SoCs documentations seems to confirm this, as the DPTSR register
197	 * is not documented if only the first source exists on that SoC.
198	 */
199	if (rgrp->channels_mask & BIT(1)) {
200		mutex_lock(&rgrp->lock);
201		rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
202				    rgrp->dptsr_planes);
203		mutex_unlock(&rgrp->lock);
204	}
205}
206
207/*
208 * rcar_du_group_get - Acquire a reference to the DU channels group
209 *
210 * Acquiring the first reference setups core registers. A reference must be held
211 * before accessing any hardware registers.
212 *
213 * This function must be called with the DRM mode_config lock held.
214 *
215 * Return 0 in case of success or a negative error code otherwise.
216 */
217int rcar_du_group_get(struct rcar_du_group *rgrp)
218{
219	if (rgrp->use_count)
220		goto done;
221
222	rcar_du_group_setup(rgrp);
223
224done:
225	rgrp->use_count++;
226	return 0;
227}
228
229/*
230 * rcar_du_group_put - Release a reference to the DU
231 *
232 * This function must be called with the DRM mode_config lock held.
233 */
234void rcar_du_group_put(struct rcar_du_group *rgrp)
235{
236	--rgrp->use_count;
237}
238
239static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
240{
241	struct rcar_du_device *rcdu = rgrp->dev;
242
243	/*
244	 * Group start/stop is controlled by the DRES and DEN bits of DSYSR0
245	 * for the first group and DSYSR2 for the second group. On most DU
246	 * instances, this maps to the first CRTC of the group, and we can just
247	 * use rcar_du_crtc_dsysr_clr_set() to access the correct DSYSR. On
248	 * M3-N, however, DU2 doesn't exist, but DSYSR2 does. We thus need to
249	 * access the register directly using group read/write.
250	 */
251	if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) {
252		struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2];
253
254		rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
255					   start ? DSYSR_DEN : DSYSR_DRES);
256	} else {
257		rcar_du_group_write(rgrp, DSYSR,
258				    start ? DSYSR_DEN : DSYSR_DRES);
259	}
260}
261
262void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
263{
264	/*
265	 * Many of the configuration bits are only updated when the display
266	 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
267	 * of those bits could be pre-configured, but others (especially the
268	 * bits related to plane assignment to display timing controllers) need
269	 * to be modified at runtime.
270	 *
271	 * Restart the display controller if a start is requested. Sorry for the
272	 * flicker. It should be possible to move most of the "DRES-update" bits
273	 * setup to driver initialization time and minimize the number of cases
274	 * when the display controller will have to be restarted.
275	 */
276	if (start) {
277		if (rgrp->used_crtcs++ != 0)
278			__rcar_du_group_start_stop(rgrp, false);
279		__rcar_du_group_start_stop(rgrp, true);
280	} else {
281		if (--rgrp->used_crtcs == 0)
282			__rcar_du_group_start_stop(rgrp, false);
283	}
284}
285
286void rcar_du_group_restart(struct rcar_du_group *rgrp)
287{
288	rgrp->need_restart = false;
289
290	__rcar_du_group_start_stop(rgrp, false);
291	__rcar_du_group_start_stop(rgrp, true);
292}
293
294int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
295{
296	struct rcar_du_group *rgrp;
297	struct rcar_du_crtc *crtc;
298	unsigned int index;
299	int ret;
300
301	if (rcdu->info->gen < 2)
302		return 0;
303
304	/*
305	 * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
306	 * configured in the DEFR8 register of the first group on Gen2 and the
307	 * last group on Gen3. As this function can be called with the DU
308	 * channels of the corresponding CRTCs disabled, we need to enable the
309	 * group clock before accessing the register.
310	 */
311	index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;
312	rgrp = &rcdu->groups[index];
313	crtc = &rcdu->crtcs[index * 2];
314
315	ret = clk_prepare_enable(crtc->clock);
316	if (ret < 0)
317		return ret;
318
319	rcar_du_group_setup_defr8(rgrp);
320
321	clk_disable_unprepare(crtc->clock);
322
323	return 0;
324}
325
326static void rcar_du_group_set_dpad_levels(struct rcar_du_group *rgrp)
327{
328	static const u32 doflr_values[2] = {
329		DOFLR_HSYCFL0 | DOFLR_VSYCFL0 | DOFLR_ODDFL0 |
330		DOFLR_DISPFL0 | DOFLR_CDEFL0  | DOFLR_RGBFL0,
331		DOFLR_HSYCFL1 | DOFLR_VSYCFL1 | DOFLR_ODDFL1 |
332		DOFLR_DISPFL1 | DOFLR_CDEFL1  | DOFLR_RGBFL1,
333	};
334	static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1)
335				   | BIT(RCAR_DU_OUTPUT_DPAD0);
336	struct rcar_du_device *rcdu = rgrp->dev;
337	u32 doflr = DOFLR_CODE;
338	unsigned int i;
339
340	if (rcdu->info->gen < 2)
341		return;
342
343	/*
344	 * The DPAD outputs can't be controlled directly. However, the parallel
345	 * output of the DU channels routed to DPAD can be set to fixed levels
346	 * through the DOFLR group register. Use this to turn the DPAD on or off
347	 * by driving fixed low-level signals at the output of any DU channel
348	 * not routed to a DPAD output. This doesn't affect the DU output
349	 * signals going to other outputs, such as the internal LVDS and HDMI
350	 * encoders.
351	 */
352
353	for (i = 0; i < rgrp->num_crtcs; ++i) {
354		struct rcar_du_crtc_state *rstate;
355		struct rcar_du_crtc *rcrtc;
356
357		rcrtc = &rcdu->crtcs[rgrp->index * 2 + i];
358		rstate = to_rcar_crtc_state(rcrtc->crtc.state);
359
360		if (!(rstate->outputs & dpad_mask))
361			doflr |= doflr_values[i];
362	}
363
364	rcar_du_group_write(rgrp, DOFLR, doflr);
365}
366
367int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
368{
369	struct rcar_du_device *rcdu = rgrp->dev;
370	u32 dorcr = rcar_du_group_read(rgrp, DORCR);
371
372	dorcr &= ~(DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_MASK);
373
374	/*
375	 * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
376	 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
377	 * by default.
378	 */
379	if (rcdu->dpad1_source == rgrp->index * 2)
380		dorcr |= DORCR_PG1D_DS0;
381	else
382		dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1;
383
384	rcar_du_group_write(rgrp, DORCR, dorcr);
385
386	rcar_du_group_set_dpad_levels(rgrp);
387
388	return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
389}