FILE
si_dpm.c
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/radeon/si_dpm.c
1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/math64.h> 25#include <linux/pci.h> 26#include <linux/seq_file.h> 27 28#include "atom.h" 29#include "evergreen.h" 30#include "r600_dpm.h" 31#include "rv770.h" 32#include "radeon.h" 33#include "radeon_asic.h" 34#include "ni_dpm.h" 35#include "si_dpm.h" 36#include "si.h" 37#include "sid.h" 38#include "vce.h" 39 40#define MC_CG_ARB_FREQ_F0 0x0a 41#define MC_CG_ARB_FREQ_F1 0x0b 42#define MC_CG_ARB_FREQ_F2 0x0c 43#define MC_CG_ARB_FREQ_F3 0x0d 44 45#define SMC_RAM_END 0x20000 46 47#define SCLK_MIN_DEEPSLEEP_FREQ 1350 48 49static const struct si_cac_config_reg cac_weights_tahiti[] = { 50 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 51 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 53 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 54 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 57 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 58 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 59 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 60 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 62 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 63 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 64 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 65 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 66 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 68 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 70 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 71 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 72 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 81 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 85 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 88 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 90 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 106 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 107 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 108 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 109 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 110 { 0xFFFFFFFF } 111}; 112 113static const struct si_cac_config_reg lcac_tahiti[] = { 114 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 119 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 121 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 135 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 137 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 159 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 161 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 171 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 173 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 183 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 185 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 187 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 197 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 198 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 199 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 200 { 0xFFFFFFFF } 201 202}; 203 204static const struct si_cac_config_reg cac_override_tahiti[] = { 205 { 0xFFFFFFFF } 206}; 207 208static const struct si_powertune_data powertune_data_tahiti = { 209 ((1 << 16) | 27027), 210 6, 211 0, 212 4, 213 95, 214 { 215 0UL, 216 0UL, 217 4521550UL, 218 309631529UL, 219 -1270850L, 220 4513710L, 221 40 222 }, 223 595000000UL, 224 12, 225 { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0 234 }, 235 true 236}; 237 238static const struct si_dte_data dte_data_tahiti = { 239 { 1159409, 0, 0, 0, 0 }, 240 { 777, 0, 0, 0, 0 }, 241 2, 242 54000, 243 127000, 244 25, 245 2, 246 10, 247 13, 248 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 249 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 250 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 251 85, 252 false 253}; 254 255static const struct si_dte_data dte_data_tahiti_pro = { 256 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 257 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 258 5, 259 45000, 260 100, 261 0xA, 262 1, 263 0, 264 0x10, 265 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 266 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 267 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 268 90, 269 true 270}; 271 272static const struct si_dte_data dte_data_new_zealand = { 273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 274 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 275 0x5, 276 0xAFC8, 277 0x69, 278 0x32, 279 1, 280 0, 281 0x10, 282 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 284 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 285 85, 286 true 287}; 288 289static const struct si_dte_data dte_data_aruba_pro = { 290 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 291 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 292 5, 293 45000, 294 100, 295 0xA, 296 1, 297 0, 298 0x10, 299 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 300 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 301 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 302 90, 303 true 304}; 305 306static const struct si_dte_data dte_data_malta = { 307 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 308 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 309 5, 310 45000, 311 100, 312 0xA, 313 1, 314 0, 315 0x10, 316 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 317 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 318 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 319 90, 320 true 321}; 322 323static struct si_cac_config_reg cac_weights_pitcairn[] = { 324 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 325 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 326 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 327 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 328 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 329 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 330 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 331 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 332 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 333 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 334 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 335 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 336 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 337 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 338 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 339 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 340 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 341 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 342 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 343 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 344 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 345 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 346 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 347 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 350 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 351 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 352 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 355 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 356 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 357 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 358 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 359 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 360 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 361 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 363 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 366 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 367 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 368 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 381 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 384 { 0xFFFFFFFF } 385}; 386 387static const struct si_cac_config_reg lcac_pitcairn[] = { 388 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 389 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 390 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 391 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 392 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 393 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 394 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 395 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 396 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 397 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 398 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 399 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 400 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 401 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 402 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 403 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 404 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 405 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 406 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 407 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 408 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 409 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 410 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 411 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 412 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 415 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 421 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 427 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 433 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 439 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 441 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 443 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 445 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 449 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 451 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 453 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 455 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 457 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 459 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 461 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 471 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 473 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0xFFFFFFFF } 475}; 476 477static const struct si_cac_config_reg cac_override_pitcairn[] = { 478 { 0xFFFFFFFF } 479}; 480 481static const struct si_powertune_data powertune_data_pitcairn = { 482 ((1 << 16) | 27027), 483 5, 484 0, 485 6, 486 100, 487 { 488 51600000UL, 489 1800000UL, 490 7194395UL, 491 309631529UL, 492 -1270850L, 493 4513710L, 494 100 495 }, 496 117830498UL, 497 12, 498 { 499 0, 500 0, 501 0, 502 0, 503 0, 504 0, 505 0, 506 0 507 }, 508 true 509}; 510 511static const struct si_dte_data dte_data_pitcairn = { 512 { 0, 0, 0, 0, 0 }, 513 { 0, 0, 0, 0, 0 }, 514 0, 515 0, 516 0, 517 0, 518 0, 519 0, 520 0, 521 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 522 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 523 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 524 0, 525 false 526}; 527 528static const struct si_dte_data dte_data_curacao_xt = { 529 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 530 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 531 5, 532 45000, 533 100, 534 0xA, 535 1, 536 0, 537 0x10, 538 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 539 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 540 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 541 90, 542 true 543}; 544 545static const struct si_dte_data dte_data_curacao_pro = { 546 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 547 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 548 5, 549 45000, 550 100, 551 0xA, 552 1, 553 0, 554 0x10, 555 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 556 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 557 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 558 90, 559 true 560}; 561 562static const struct si_dte_data dte_data_neptune_xt = { 563 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 564 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 565 5, 566 45000, 567 100, 568 0xA, 569 1, 570 0, 571 0x10, 572 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 573 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 574 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 575 90, 576 true 577}; 578 579static const struct si_cac_config_reg cac_weights_chelsea_pro[] = { 580 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 581 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 582 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 583 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 584 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 585 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 586 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 587 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 588 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 589 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 590 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 591 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 592 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 593 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 594 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 595 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 596 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 597 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 598 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 599 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 600 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 601 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 602 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 603 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 604 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 605 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 606 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 607 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 608 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 609 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 610 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 611 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 612 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 613 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 614 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 615 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 616 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 619 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 620 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 621 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 622 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 623 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 624 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 625 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 626 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 627 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 628 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 629 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 630 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 631 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 632 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 633 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 634 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 635 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 636 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 639 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 640 { 0xFFFFFFFF } 641}; 642 643static const struct si_cac_config_reg cac_weights_chelsea_xt[] = { 644 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 645 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 646 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 647 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 648 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 650 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 651 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 652 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 653 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 654 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 655 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 656 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 657 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 658 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 659 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 660 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 661 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 662 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 663 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 664 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 665 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 666 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 667 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 668 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 669 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 670 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 671 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 672 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 673 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 674 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 675 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 676 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 677 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 678 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 679 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 680 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 681 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 683 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 684 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 685 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 686 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 687 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 688 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 689 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 690 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 691 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 692 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 693 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 694 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 695 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 696 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 697 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 698 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 699 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 700 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 701 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 704 { 0xFFFFFFFF } 705}; 706 707static const struct si_cac_config_reg cac_weights_heathrow[] = { 708 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 709 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 710 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 711 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 712 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 714 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 716 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 717 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 718 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 719 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 720 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 721 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 722 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 723 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 724 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 725 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 726 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 727 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 728 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 729 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 730 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 731 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 732 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 733 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 734 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 735 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 737 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 738 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 739 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 740 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 741 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 742 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 743 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 744 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 746 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 748 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 749 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 750 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 751 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 752 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 753 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 754 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 755 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 757 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 758 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 759 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 760 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 761 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 762 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 763 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 764 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 766 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 768 { 0xFFFFFFFF } 769}; 770 771static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = { 772 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 773 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 775 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 776 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 778 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 779 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 781 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 782 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 783 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 784 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 786 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 787 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 788 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 789 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 790 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 791 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 792 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 793 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 794 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 795 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 796 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 797 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 798 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 799 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 801 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 802 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 803 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 804 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 805 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 806 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 807 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 808 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 809 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 810 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 811 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 812 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 813 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 814 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 815 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 816 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 817 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 818 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 819 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 820 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 822 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 823 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 824 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 825 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 826 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 827 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 828 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 829 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 831 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 832 { 0xFFFFFFFF } 833}; 834 835static const struct si_cac_config_reg cac_weights_cape_verde[] = { 836 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 837 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 838 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 840 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 842 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 843 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 844 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 845 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 846 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 847 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 848 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 850 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 851 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 852 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 853 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 854 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 855 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 856 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 857 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 858 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 859 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 860 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 861 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 862 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 863 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 865 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 866 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 867 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 868 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 869 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 870 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 871 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 872 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 873 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 874 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 876 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 877 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 878 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 879 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 880 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 881 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 882 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 883 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 884 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 885 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 887 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 888 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 889 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 890 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 891 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 892 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 893 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 894 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 896 { 0xFFFFFFFF } 897}; 898 899static const struct si_cac_config_reg lcac_cape_verde[] = { 900 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 901 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 903 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 904 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 905 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 906 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 908 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 909 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 910 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 911 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 912 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 913 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 914 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 915 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 916 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 917 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 918 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 919 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 920 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 921 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 922 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 923 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 924 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 925 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 926 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 927 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 928 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 929 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 930 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 931 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 932 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 933 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 934 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 935 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 936 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 939 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 941 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 945 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0xFFFFFFFF } 955}; 956 957static const struct si_cac_config_reg cac_override_cape_verde[] = { 958 { 0xFFFFFFFF } 959}; 960 961static const struct si_powertune_data powertune_data_cape_verde = { 962 ((1 << 16) | 0x6993), 963 5, 964 0, 965 7, 966 105, 967 { 968 0UL, 969 0UL, 970 7194395UL, 971 309631529UL, 972 -1270850L, 973 4513710L, 974 100 975 }, 976 117830498UL, 977 12, 978 { 979 0, 980 0, 981 0, 982 0, 983 0, 984 0, 985 0, 986 0 987 }, 988 true 989}; 990 991static const struct si_dte_data dte_data_cape_verde = { 992 { 0, 0, 0, 0, 0 }, 993 { 0, 0, 0, 0, 0 }, 994 0, 995 0, 996 0, 997 0, 998 0, 999 0, 1000 0, 1001 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1002 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1003 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1004 0, 1005 false 1006}; 1007 1008static const struct si_dte_data dte_data_venus_xtx = { 1009 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1010 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1011 5, 1012 55000, 1013 0x69, 1014 0xA, 1015 1, 1016 0, 1017 0x3, 1018 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1019 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1020 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1021 90, 1022 true 1023}; 1024 1025static const struct si_dte_data dte_data_venus_xt = { 1026 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1027 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1028 5, 1029 55000, 1030 0x69, 1031 0xA, 1032 1, 1033 0, 1034 0x3, 1035 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1036 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1037 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1038 90, 1039 true 1040}; 1041 1042static const struct si_dte_data dte_data_venus_pro = { 1043 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1044 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1045 5, 1046 55000, 1047 0x69, 1048 0xA, 1049 1, 1050 0, 1051 0x3, 1052 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1053 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1054 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1055 90, 1056 true 1057}; 1058 1059static struct si_cac_config_reg cac_weights_oland[] = { 1060 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1061 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1062 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1063 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1064 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1065 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1066 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1067 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1068 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1069 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1070 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1071 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1072 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1073 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1074 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1075 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1076 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1077 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1078 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1079 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1080 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1081 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1082 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1083 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1084 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1085 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1086 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1087 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1088 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1089 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1090 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1096 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1097 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1098 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1099 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1100 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1101 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1120 { 0xFFFFFFFF } 1121}; 1122 1123static const struct si_cac_config_reg cac_weights_mars_pro[] = { 1124 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1125 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1126 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1127 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1128 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1143 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1144 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1145 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1146 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1147 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1148 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1149 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1150 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1151 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1164 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1165 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1166 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1184 { 0xFFFFFFFF } 1185}; 1186 1187static const struct si_cac_config_reg cac_weights_mars_xt[] = { 1188 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1189 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1190 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1191 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1192 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1193 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1208 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1209 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1210 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1211 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1212 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1213 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1214 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1215 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1229 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1230 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1231 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1248 { 0xFFFFFFFF } 1249}; 1250 1251static const struct si_cac_config_reg cac_weights_oland_pro[] = { 1252 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1271 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1272 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1273 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1274 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1275 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1276 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1277 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1278 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1279 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1294 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1295 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1296 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1312 { 0xFFFFFFFF } 1313}; 1314 1315static const struct si_cac_config_reg cac_weights_oland_xt[] = { 1316 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1335 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1336 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1337 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1338 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1339 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1340 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1341 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1342 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1343 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1359 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1360 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1361 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1376 { 0xFFFFFFFF } 1377}; 1378 1379static const struct si_cac_config_reg lcac_oland[] = { 1380 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1422 { 0xFFFFFFFF } 1423}; 1424 1425static const struct si_cac_config_reg lcac_mars_pro[] = { 1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0xFFFFFFFF } 1469}; 1470 1471static const struct si_cac_config_reg cac_override_oland[] = { 1472 { 0xFFFFFFFF } 1473}; 1474 1475static const struct si_powertune_data powertune_data_oland = { 1476 ((1 << 16) | 0x6993), 1477 5, 1478 0, 1479 7, 1480 105, 1481 { 1482 0UL, 1483 0UL, 1484 7194395UL, 1485 309631529UL, 1486 -1270850L, 1487 4513710L, 1488 100 1489 }, 1490 117830498UL, 1491 12, 1492 { 1493 0, 1494 0, 1495 0, 1496 0, 1497 0, 1498 0, 1499 0, 1500 0 1501 }, 1502 true 1503}; 1504 1505static const struct si_powertune_data powertune_data_mars_pro = { 1506 ((1 << 16) | 0x6993), 1507 5, 1508 0, 1509 7, 1510 105, 1511 { 1512 0UL, 1513 0UL, 1514 7194395UL, 1515 309631529UL, 1516 -1270850L, 1517 4513710L, 1518 100 1519 }, 1520 117830498UL, 1521 12, 1522 { 1523 0, 1524 0, 1525 0, 1526 0, 1527 0, 1528 0, 1529 0, 1530 0 1531 }, 1532 true 1533}; 1534 1535static const struct si_dte_data dte_data_oland = { 1536 { 0, 0, 0, 0, 0 }, 1537 { 0, 0, 0, 0, 0 }, 1538 0, 1539 0, 1540 0, 1541 0, 1542 0, 1543 0, 1544 0, 1545 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1548 0, 1549 false 1550}; 1551 1552static const struct si_dte_data dte_data_mars_pro = { 1553 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1554 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1555 5, 1556 55000, 1557 105, 1558 0xA, 1559 1, 1560 0, 1561 0x10, 1562 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1563 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1564 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1565 90, 1566 true 1567}; 1568 1569static const struct si_dte_data dte_data_sun_xt = { 1570 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1571 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1572 5, 1573 55000, 1574 105, 1575 0xA, 1576 1, 1577 0, 1578 0x10, 1579 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1580 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1581 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1582 90, 1583 true 1584}; 1585 1586 1587static const struct si_cac_config_reg cac_weights_hainan[] = { 1588 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1589 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1590 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1591 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1592 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1593 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1594 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1595 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1596 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1597 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1598 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1599 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1600 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1601 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1602 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1603 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1604 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1605 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1606 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1607 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1608 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1609 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1610 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1611 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1612 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1613 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1614 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1615 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1616 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1617 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1618 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1619 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1620 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1621 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1622 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1623 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1624 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1625 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1626 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1627 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1628 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1629 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1630 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1631 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1632 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1633 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1634 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1635 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1636 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1637 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1638 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1639 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1640 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1641 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1642 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1648 { 0xFFFFFFFF } 1649}; 1650 1651static const struct si_powertune_data powertune_data_hainan = { 1652 ((1 << 16) | 0x6993), 1653 5, 1654 0, 1655 9, 1656 105, 1657 { 1658 0UL, 1659 0UL, 1660 7194395UL, 1661 309631529UL, 1662 -1270850L, 1663 4513710L, 1664 100 1665 }, 1666 117830498UL, 1667 12, 1668 { 1669 0, 1670 0, 1671 0, 1672 0, 1673 0, 1674 0, 1675 0, 1676 0 1677 }, 1678 true 1679}; 1680 1681static int si_populate_voltage_value(struct radeon_device *rdev, 1682 const struct atom_voltage_table *table, 1683 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1684static int si_get_std_voltage_value(struct radeon_device *rdev, 1685 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1686 u16 *std_voltage); 1687static int si_write_smc_soft_register(struct radeon_device *rdev, 1688 u16 reg_offset, u32 value); 1689static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1690 struct rv7xx_pl *pl, 1691 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1692static int si_calculate_sclk_params(struct radeon_device *rdev, 1693 u32 engine_clock, 1694 SISLANDS_SMC_SCLK_VALUE *sclk); 1695 1696static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1697static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1698 1699static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1700{ 1701 struct si_power_info *pi = rdev->pm.dpm.priv; 1702 1703 return pi; 1704} 1705 1706static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1707 u16 v, s32 t, u32 ileakage, u32 *leakage) 1708{ 1709 s64 kt, kv, leakage_w, i_leakage, vddc; 1710 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1711 s64 tmp; 1712 1713 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1714 vddc = div64_s64(drm_int2fixp(v), 1000); 1715 temperature = div64_s64(drm_int2fixp(t), 1000); 1716 1717 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1718 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1719 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1720 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1721 t_ref = drm_int2fixp(coeff->t_ref); 1722 1723 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1724 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1725 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1726 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1727 1728 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1729 1730 *leakage = drm_fixp2int(leakage_w * 1000); 1731} 1732 1733static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1734 const struct ni_leakage_coeffients *coeff, 1735 u16 v, 1736 s32 t, 1737 u32 i_leakage, 1738 u32 *leakage) 1739{ 1740 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1741} 1742 1743static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1744 const u32 fixed_kt, u16 v, 1745 u32 ileakage, u32 *leakage) 1746{ 1747 s64 kt, kv, leakage_w, i_leakage, vddc; 1748 1749 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1750 vddc = div64_s64(drm_int2fixp(v), 1000); 1751 1752 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1753 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1754 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1755 1756 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1757 1758 *leakage = drm_fixp2int(leakage_w * 1000); 1759} 1760 1761static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1762 const struct ni_leakage_coeffients *coeff, 1763 const u32 fixed_kt, 1764 u16 v, 1765 u32 i_leakage, 1766 u32 *leakage) 1767{ 1768 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1769} 1770 1771 1772static void si_update_dte_from_pl2(struct radeon_device *rdev, 1773 struct si_dte_data *dte_data) 1774{ 1775 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1776 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1777 u32 k = dte_data->k; 1778 u32 t_max = dte_data->max_t; 1779 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1780 u32 t_0 = dte_data->t0; 1781 u32 i; 1782 1783 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1784 dte_data->tdep_count = 3; 1785 1786 for (i = 0; i < k; i++) { 1787 dte_data->r[i] = 1788 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1789 (p_limit2 * (u32)100); 1790 } 1791 1792 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1793 1794 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1795 dte_data->tdep_r[i] = dte_data->r[4]; 1796 } 1797 } else { 1798 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1799 } 1800} 1801 1802static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1803{ 1804 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1805 struct si_power_info *si_pi = si_get_pi(rdev); 1806 bool update_dte_from_pl2 = false; 1807 1808 if (rdev->family == CHIP_TAHITI) { 1809 si_pi->cac_weights = cac_weights_tahiti; 1810 si_pi->lcac_config = lcac_tahiti; 1811 si_pi->cac_override = cac_override_tahiti; 1812 si_pi->powertune_data = &powertune_data_tahiti; 1813 si_pi->dte_data = dte_data_tahiti; 1814 1815 switch (rdev->pdev->device) { 1816 case 0x6798: 1817 si_pi->dte_data.enable_dte_by_default = true; 1818 break; 1819 case 0x6799: 1820 si_pi->dte_data = dte_data_new_zealand; 1821 break; 1822 case 0x6790: 1823 case 0x6791: 1824 case 0x6792: 1825 case 0x679E: 1826 si_pi->dte_data = dte_data_aruba_pro; 1827 update_dte_from_pl2 = true; 1828 break; 1829 case 0x679B: 1830 si_pi->dte_data = dte_data_malta; 1831 update_dte_from_pl2 = true; 1832 break; 1833 case 0x679A: 1834 si_pi->dte_data = dte_data_tahiti_pro; 1835 update_dte_from_pl2 = true; 1836 break; 1837 default: 1838 if (si_pi->dte_data.enable_dte_by_default == true) 1839 DRM_ERROR("DTE is not enabled!\n"); 1840 break; 1841 } 1842 } else if (rdev->family == CHIP_PITCAIRN) { 1843 switch (rdev->pdev->device) { 1844 case 0x6810: 1845 case 0x6818: 1846 si_pi->cac_weights = cac_weights_pitcairn; 1847 si_pi->lcac_config = lcac_pitcairn; 1848 si_pi->cac_override = cac_override_pitcairn; 1849 si_pi->powertune_data = &powertune_data_pitcairn; 1850 si_pi->dte_data = dte_data_curacao_xt; 1851 update_dte_from_pl2 = true; 1852 break; 1853 case 0x6819: 1854 case 0x6811: 1855 si_pi->cac_weights = cac_weights_pitcairn; 1856 si_pi->lcac_config = lcac_pitcairn; 1857 si_pi->cac_override = cac_override_pitcairn; 1858 si_pi->powertune_data = &powertune_data_pitcairn; 1859 si_pi->dte_data = dte_data_curacao_pro; 1860 update_dte_from_pl2 = true; 1861 break; 1862 case 0x6800: 1863 case 0x6806: 1864 si_pi->cac_weights = cac_weights_pitcairn; 1865 si_pi->lcac_config = lcac_pitcairn; 1866 si_pi->cac_override = cac_override_pitcairn; 1867 si_pi->powertune_data = &powertune_data_pitcairn; 1868 si_pi->dte_data = dte_data_neptune_xt; 1869 update_dte_from_pl2 = true; 1870 break; 1871 default: 1872 si_pi->cac_weights = cac_weights_pitcairn; 1873 si_pi->lcac_config = lcac_pitcairn; 1874 si_pi->cac_override = cac_override_pitcairn; 1875 si_pi->powertune_data = &powertune_data_pitcairn; 1876 si_pi->dte_data = dte_data_pitcairn; 1877 break; 1878 } 1879 } else if (rdev->family == CHIP_VERDE) { 1880 si_pi->lcac_config = lcac_cape_verde; 1881 si_pi->cac_override = cac_override_cape_verde; 1882 si_pi->powertune_data = &powertune_data_cape_verde; 1883 1884 switch (rdev->pdev->device) { 1885 case 0x683B: 1886 case 0x683F: 1887 case 0x6829: 1888 case 0x6835: 1889 si_pi->cac_weights = cac_weights_cape_verde_pro; 1890 si_pi->dte_data = dte_data_cape_verde; 1891 break; 1892 case 0x682C: 1893 si_pi->cac_weights = cac_weights_cape_verde_pro; 1894 si_pi->dte_data = dte_data_sun_xt; 1895 update_dte_from_pl2 = true; 1896 break; 1897 case 0x6825: 1898 case 0x6827: 1899 si_pi->cac_weights = cac_weights_heathrow; 1900 si_pi->dte_data = dte_data_cape_verde; 1901 break; 1902 case 0x6824: 1903 case 0x682D: 1904 si_pi->cac_weights = cac_weights_chelsea_xt; 1905 si_pi->dte_data = dte_data_cape_verde; 1906 break; 1907 case 0x682F: 1908 si_pi->cac_weights = cac_weights_chelsea_pro; 1909 si_pi->dte_data = dte_data_cape_verde; 1910 break; 1911 case 0x6820: 1912 si_pi->cac_weights = cac_weights_heathrow; 1913 si_pi->dte_data = dte_data_venus_xtx; 1914 break; 1915 case 0x6821: 1916 si_pi->cac_weights = cac_weights_heathrow; 1917 si_pi->dte_data = dte_data_venus_xt; 1918 break; 1919 case 0x6823: 1920 case 0x682B: 1921 case 0x6822: 1922 case 0x682A: 1923 si_pi->cac_weights = cac_weights_chelsea_pro; 1924 si_pi->dte_data = dte_data_venus_pro; 1925 break; 1926 default: 1927 si_pi->cac_weights = cac_weights_cape_verde; 1928 si_pi->dte_data = dte_data_cape_verde; 1929 break; 1930 } 1931 } else if (rdev->family == CHIP_OLAND) { 1932 switch (rdev->pdev->device) { 1933 case 0x6601: 1934 case 0x6621: 1935 case 0x6603: 1936 case 0x6605: 1937 si_pi->cac_weights = cac_weights_mars_pro; 1938 si_pi->lcac_config = lcac_mars_pro; 1939 si_pi->cac_override = cac_override_oland; 1940 si_pi->powertune_data = &powertune_data_mars_pro; 1941 si_pi->dte_data = dte_data_mars_pro; 1942 update_dte_from_pl2 = true; 1943 break; 1944 case 0x6600: 1945 case 0x6606: 1946 case 0x6620: 1947 case 0x6604: 1948 si_pi->cac_weights = cac_weights_mars_xt; 1949 si_pi->lcac_config = lcac_mars_pro; 1950 si_pi->cac_override = cac_override_oland; 1951 si_pi->powertune_data = &powertune_data_mars_pro; 1952 si_pi->dte_data = dte_data_mars_pro; 1953 update_dte_from_pl2 = true; 1954 break; 1955 case 0x6611: 1956 case 0x6613: 1957 case 0x6608: 1958 si_pi->cac_weights = cac_weights_oland_pro; 1959 si_pi->lcac_config = lcac_mars_pro; 1960 si_pi->cac_override = cac_override_oland; 1961 si_pi->powertune_data = &powertune_data_mars_pro; 1962 si_pi->dte_data = dte_data_mars_pro; 1963 update_dte_from_pl2 = true; 1964 break; 1965 case 0x6610: 1966 si_pi->cac_weights = cac_weights_oland_xt; 1967 si_pi->lcac_config = lcac_mars_pro; 1968 si_pi->cac_override = cac_override_oland; 1969 si_pi->powertune_data = &powertune_data_mars_pro; 1970 si_pi->dte_data = dte_data_mars_pro; 1971 update_dte_from_pl2 = true; 1972 break; 1973 default: 1974 si_pi->cac_weights = cac_weights_oland; 1975 si_pi->lcac_config = lcac_oland; 1976 si_pi->cac_override = cac_override_oland; 1977 si_pi->powertune_data = &powertune_data_oland; 1978 si_pi->dte_data = dte_data_oland; 1979 break; 1980 } 1981 } else if (rdev->family == CHIP_HAINAN) { 1982 si_pi->cac_weights = cac_weights_hainan; 1983 si_pi->lcac_config = lcac_oland; 1984 si_pi->cac_override = cac_override_oland; 1985 si_pi->powertune_data = &powertune_data_hainan; 1986 si_pi->dte_data = dte_data_sun_xt; 1987 update_dte_from_pl2 = true; 1988 } else { 1989 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 1990 return; 1991 } 1992 1993 ni_pi->enable_power_containment = false; 1994 ni_pi->enable_cac = false; 1995 ni_pi->enable_sq_ramping = false; 1996 si_pi->enable_dte = false; 1997 1998 if (si_pi->powertune_data->enable_powertune_by_default) { 1999 ni_pi->enable_power_containment= true; 2000 ni_pi->enable_cac = true; 2001 if (si_pi->dte_data.enable_dte_by_default) { 2002 si_pi->enable_dte = true; 2003 if (update_dte_from_pl2) 2004 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2005 2006 } 2007 ni_pi->enable_sq_ramping = true; 2008 } 2009 2010 ni_pi->driver_calculate_cac_leakage = true; 2011 ni_pi->cac_configuration_required = true; 2012 2013 if (ni_pi->cac_configuration_required) { 2014 ni_pi->support_cac_long_term_average = true; 2015 si_pi->dyn_powertune_data.l2_lta_window_size = 2016 si_pi->powertune_data->l2_lta_window_size_default; 2017 si_pi->dyn_powertune_data.lts_truncate = 2018 si_pi->powertune_data->lts_truncate_default; 2019 } else { 2020 ni_pi->support_cac_long_term_average = false; 2021 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2022 si_pi->dyn_powertune_data.lts_truncate = 0; 2023 } 2024 2025 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2026} 2027 2028static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2029{ 2030 return 1; 2031} 2032 2033static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2034{ 2035 u32 xclk; 2036 u32 wintime; 2037 u32 cac_window; 2038 u32 cac_window_size; 2039 2040 xclk = radeon_get_xclk(rdev); 2041 2042 if (xclk == 0) 2043 return 0; 2044 2045 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2046 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2047 2048 wintime = (cac_window_size * 100) / xclk; 2049 2050 return wintime; 2051} 2052 2053static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2054{ 2055 return power_in_watts; 2056} 2057 2058static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2059 bool adjust_polarity, 2060 u32 tdp_adjustment, 2061 u32 *tdp_limit, 2062 u32 *near_tdp_limit) 2063{ 2064 u32 adjustment_delta, max_tdp_limit; 2065 2066 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2067 return -EINVAL; 2068 2069 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2070 2071 if (adjust_polarity) { 2072 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2073 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2074 } else { 2075 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2076 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2077 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2078 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2079 else 2080 *near_tdp_limit = 0; 2081 } 2082 2083 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2084 return -EINVAL; 2085 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2086 return -EINVAL; 2087 2088 return 0; 2089} 2090 2091static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2092 struct radeon_ps *radeon_state) 2093{ 2094 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2095 struct si_power_info *si_pi = si_get_pi(rdev); 2096 2097 if (ni_pi->enable_power_containment) { 2098 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2099 PP_SIslands_PAPMParameters *papm_parm; 2100 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2101 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2102 u32 tdp_limit; 2103 u32 near_tdp_limit; 2104 int ret; 2105 2106 if (scaling_factor == 0) 2107 return -EINVAL; 2108 2109 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2110 2111 ret = si_calculate_adjusted_tdp_limits(rdev, 2112 false, /* ??? */ 2113 rdev->pm.dpm.tdp_adjustment, 2114 &tdp_limit, 2115 &near_tdp_limit); 2116 if (ret) 2117 return ret; 2118 2119 smc_table->dpm2Params.TDPLimit = 2120 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2121 smc_table->dpm2Params.NearTDPLimit = 2122 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2123 smc_table->dpm2Params.SafePowerLimit = 2124 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2125 2126 ret = si_copy_bytes_to_smc(rdev, 2127 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2128 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2129 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2130 sizeof(u32) * 3, 2131 si_pi->sram_end); 2132 if (ret) 2133 return ret; 2134 2135 if (si_pi->enable_ppm) { 2136 papm_parm = &si_pi->papm_parm; 2137 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2138 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2139 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2140 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2141 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2142 papm_parm->PlatformPowerLimit = 0xffffffff; 2143 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2144 2145 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2146 (u8 *)papm_parm, 2147 sizeof(PP_SIslands_PAPMParameters), 2148 si_pi->sram_end); 2149 if (ret) 2150 return ret; 2151 } 2152 } 2153 return 0; 2154} 2155 2156static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2157 struct radeon_ps *radeon_state) 2158{ 2159 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2160 struct si_power_info *si_pi = si_get_pi(rdev); 2161 2162 if (ni_pi->enable_power_containment) { 2163 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2165 int ret; 2166 2167 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2168 2169 smc_table->dpm2Params.NearTDPLimit = 2170 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2171 smc_table->dpm2Params.SafePowerLimit = 2172 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2173 2174 ret = si_copy_bytes_to_smc(rdev, 2175 (si_pi->state_table_start + 2176 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2177 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2178 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2179 sizeof(u32) * 2, 2180 si_pi->sram_end); 2181 if (ret) 2182 return ret; 2183 } 2184 2185 return 0; 2186} 2187 2188static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2189 const u16 prev_std_vddc, 2190 const u16 curr_std_vddc) 2191{ 2192 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2193 u64 prev_vddc = (u64)prev_std_vddc; 2194 u64 curr_vddc = (u64)curr_std_vddc; 2195 u64 pwr_efficiency_ratio, n, d; 2196 2197 if ((prev_vddc == 0) || (curr_vddc == 0)) 2198 return 0; 2199 2200 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2201 d = prev_vddc * prev_vddc; 2202 pwr_efficiency_ratio = div64_u64(n, d); 2203 2204 if (pwr_efficiency_ratio > (u64)0xFFFF) 2205 return 0; 2206 2207 return (u16)pwr_efficiency_ratio; 2208} 2209 2210static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2211 struct radeon_ps *radeon_state) 2212{ 2213 struct si_power_info *si_pi = si_get_pi(rdev); 2214 2215 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2216 radeon_state->vclk && radeon_state->dclk) 2217 return true; 2218 2219 return false; 2220} 2221 2222static int si_populate_power_containment_values(struct radeon_device *rdev, 2223 struct radeon_ps *radeon_state, 2224 SISLANDS_SMC_SWSTATE *smc_state) 2225{ 2226 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2227 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2228 struct ni_ps *state = ni_get_ps(radeon_state); 2229 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2230 u32 prev_sclk; 2231 u32 max_sclk; 2232 u32 min_sclk; 2233 u16 prev_std_vddc; 2234 u16 curr_std_vddc; 2235 int i; 2236 u16 pwr_efficiency_ratio; 2237 u8 max_ps_percent; 2238 bool disable_uvd_power_tune; 2239 int ret; 2240 2241 if (ni_pi->enable_power_containment == false) 2242 return 0; 2243 2244 if (state->performance_level_count == 0) 2245 return -EINVAL; 2246 2247 if (smc_state->levelCount != state->performance_level_count) 2248 return -EINVAL; 2249 2250 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2251 2252 smc_state->levels[0].dpm2.MaxPS = 0; 2253 smc_state->levels[0].dpm2.NearTDPDec = 0; 2254 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2255 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2256 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2257 2258 for (i = 1; i < state->performance_level_count; i++) { 2259 prev_sclk = state->performance_levels[i-1].sclk; 2260 max_sclk = state->performance_levels[i].sclk; 2261 if (i == 1) 2262 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2263 else 2264 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2265 2266 if (prev_sclk > max_sclk) 2267 return -EINVAL; 2268 2269 if ((max_ps_percent == 0) || 2270 (prev_sclk == max_sclk) || 2271 disable_uvd_power_tune) { 2272 min_sclk = max_sclk; 2273 } else if (i == 1) { 2274 min_sclk = prev_sclk; 2275 } else { 2276 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2277 } 2278 2279 if (min_sclk < state->performance_levels[0].sclk) 2280 min_sclk = state->performance_levels[0].sclk; 2281 2282 if (min_sclk == 0) 2283 return -EINVAL; 2284 2285 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2286 state->performance_levels[i-1].vddc, &vddc); 2287 if (ret) 2288 return ret; 2289 2290 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2291 if (ret) 2292 return ret; 2293 2294 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2295 state->performance_levels[i].vddc, &vddc); 2296 if (ret) 2297 return ret; 2298 2299 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2300 if (ret) 2301 return ret; 2302 2303 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2304 prev_std_vddc, curr_std_vddc); 2305 2306 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2307 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2308 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2309 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2310 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2311 } 2312 2313 return 0; 2314} 2315 2316static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2317 struct radeon_ps *radeon_state, 2318 SISLANDS_SMC_SWSTATE *smc_state) 2319{ 2320 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2321 struct ni_ps *state = ni_get_ps(radeon_state); 2322 u32 sq_power_throttle, sq_power_throttle2; 2323 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2324 int i; 2325 2326 if (state->performance_level_count == 0) 2327 return -EINVAL; 2328 2329 if (smc_state->levelCount != state->performance_level_count) 2330 return -EINVAL; 2331 2332 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2333 return -EINVAL; 2334 2335 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2336 enable_sq_ramping = false; 2337 2338 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2339 enable_sq_ramping = false; 2340 2341 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2342 enable_sq_ramping = false; 2343 2344 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2345 enable_sq_ramping = false; 2346 2347 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2348 enable_sq_ramping = false; 2349 2350 for (i = 0; i < state->performance_level_count; i++) { 2351 sq_power_throttle = 0; 2352 sq_power_throttle2 = 0; 2353 2354 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2355 enable_sq_ramping) { 2356 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2357 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2358 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2359 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2360 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2361 } else { 2362 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2363 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2364 } 2365 2366 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2367 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2368 } 2369 2370 return 0; 2371} 2372 2373static int si_enable_power_containment(struct radeon_device *rdev, 2374 struct radeon_ps *radeon_new_state, 2375 bool enable) 2376{ 2377 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2378 PPSMC_Result smc_result; 2379 int ret = 0; 2380 2381 if (ni_pi->enable_power_containment) { 2382 if (enable) { 2383 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2384 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2385 if (smc_result != PPSMC_Result_OK) { 2386 ret = -EINVAL; 2387 ni_pi->pc_enabled = false; 2388 } else { 2389 ni_pi->pc_enabled = true; 2390 } 2391 } 2392 } else { 2393 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2394 if (smc_result != PPSMC_Result_OK) 2395 ret = -EINVAL; 2396 ni_pi->pc_enabled = false; 2397 } 2398 } 2399 2400 return ret; 2401} 2402 2403static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2404{ 2405 struct si_power_info *si_pi = si_get_pi(rdev); 2406 int ret = 0; 2407 struct si_dte_data *dte_data = &si_pi->dte_data; 2408 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2409 u32 table_size; 2410 u8 tdep_count; 2411 u32 i; 2412 2413 if (dte_data == NULL) 2414 si_pi->enable_dte = false; 2415 2416 if (si_pi->enable_dte == false) 2417 return 0; 2418 2419 if (dte_data->k <= 0) 2420 return -EINVAL; 2421 2422 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2423 if (dte_tables == NULL) { 2424 si_pi->enable_dte = false; 2425 return -ENOMEM; 2426 } 2427 2428 table_size = dte_data->k; 2429 2430 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2431 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2432 2433 tdep_count = dte_data->tdep_count; 2434 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2435 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2436 2437 dte_tables->K = cpu_to_be32(table_size); 2438 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2439 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2440 dte_tables->WindowSize = dte_data->window_size; 2441 dte_tables->temp_select = dte_data->temp_select; 2442 dte_tables->DTE_mode = dte_data->dte_mode; 2443 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2444 2445 if (tdep_count > 0) 2446 table_size--; 2447 2448 for (i = 0; i < table_size; i++) { 2449 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2450 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2451 } 2452 2453 dte_tables->Tdep_count = tdep_count; 2454 2455 for (i = 0; i < (u32)tdep_count; i++) { 2456 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2457 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2458 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2459 } 2460 2461 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2462 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2463 kfree(dte_tables); 2464 2465 return ret; 2466} 2467 2468static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2469 u16 *max, u16 *min) 2470{ 2471 struct si_power_info *si_pi = si_get_pi(rdev); 2472 struct radeon_cac_leakage_table *table = 2473 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2474 u32 i; 2475 u32 v0_loadline; 2476 2477 2478 if (table == NULL) 2479 return -EINVAL; 2480 2481 *max = 0; 2482 *min = 0xFFFF; 2483 2484 for (i = 0; i < table->count; i++) { 2485 if (table->entries[i].vddc > *max) 2486 *max = table->entries[i].vddc; 2487 if (table->entries[i].vddc < *min) 2488 *min = table->entries[i].vddc; 2489 } 2490 2491 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2492 return -EINVAL; 2493 2494 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2495 2496 if (v0_loadline > 0xFFFFUL) 2497 return -EINVAL; 2498 2499 *min = (u16)v0_loadline; 2500 2501 if ((*min > *max) || (*max == 0) || (*min == 0)) 2502 return -EINVAL; 2503 2504 return 0; 2505} 2506 2507static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2508{ 2509 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2510 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2511} 2512 2513static int si_init_dte_leakage_table(struct radeon_device *rdev, 2514 PP_SIslands_CacConfig *cac_tables, 2515 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2516 u16 t0, u16 t_step) 2517{ 2518 struct si_power_info *si_pi = si_get_pi(rdev); 2519 u32 leakage; 2520 unsigned int i, j; 2521 s32 t; 2522 u32 smc_leakage; 2523 u32 scaling_factor; 2524 u16 voltage; 2525 2526 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2527 2528 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2529 t = (1000 * (i * t_step + t0)); 2530 2531 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2532 voltage = vddc_max - (vddc_step * j); 2533 2534 si_calculate_leakage_for_v_and_t(rdev, 2535 &si_pi->powertune_data->leakage_coefficients, 2536 voltage, 2537 t, 2538 si_pi->dyn_powertune_data.cac_leakage, 2539 &leakage); 2540 2541 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2542 2543 if (smc_leakage > 0xFFFF) 2544 smc_leakage = 0xFFFF; 2545 2546 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2547 cpu_to_be16((u16)smc_leakage); 2548 } 2549 } 2550 return 0; 2551} 2552 2553static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2554 PP_SIslands_CacConfig *cac_tables, 2555 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2556{ 2557 struct si_power_info *si_pi = si_get_pi(rdev); 2558 u32 leakage; 2559 unsigned int i, j; 2560 u32 smc_leakage; 2561 u32 scaling_factor; 2562 u16 voltage; 2563 2564 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2565 2566 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2567 voltage = vddc_max - (vddc_step * j); 2568 2569 si_calculate_leakage_for_v(rdev, 2570 &si_pi->powertune_data->leakage_coefficients, 2571 si_pi->powertune_data->fixed_kt, 2572 voltage, 2573 si_pi->dyn_powertune_data.cac_leakage, 2574 &leakage); 2575 2576 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2577 2578 if (smc_leakage > 0xFFFF) 2579 smc_leakage = 0xFFFF; 2580 2581 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2582 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2583 cpu_to_be16((u16)smc_leakage); 2584 } 2585 return 0; 2586} 2587 2588static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2589{ 2590 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2591 struct si_power_info *si_pi = si_get_pi(rdev); 2592 PP_SIslands_CacConfig *cac_tables = NULL; 2593 u16 vddc_max, vddc_min, vddc_step; 2594 u16 t0, t_step; 2595 u32 load_line_slope, reg; 2596 int ret = 0; 2597 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2598 2599 if (ni_pi->enable_cac == false) 2600 return 0; 2601 2602 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2603 if (!cac_tables) 2604 return -ENOMEM; 2605 2606 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2607 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2608 WREG32(CG_CAC_CTRL, reg); 2609 2610 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2611 si_pi->dyn_powertune_data.dc_pwr_value = 2612 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2613 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2614 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2615 2616 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2617 2618 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2619 if (ret) 2620 goto done_free; 2621 2622 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2623 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2624 t_step = 4; 2625 t0 = 60; 2626 2627 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2628 ret = si_init_dte_leakage_table(rdev, cac_tables, 2629 vddc_max, vddc_min, vddc_step, 2630 t0, t_step); 2631 else 2632 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2633 vddc_max, vddc_min, vddc_step); 2634 if (ret) 2635 goto done_free; 2636 2637 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2638 2639 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2640 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2641 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2642 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2643 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2644 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2645 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2646 cac_tables->calculation_repeats = cpu_to_be32(2); 2647 cac_tables->dc_cac = cpu_to_be32(0); 2648 cac_tables->log2_PG_LKG_SCALE = 12; 2649 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2650 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2651 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2652 2653 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2654 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2655 2656 if (ret) 2657 goto done_free; 2658 2659 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2660 2661done_free: 2662 if (ret) { 2663 ni_pi->enable_cac = false; 2664 ni_pi->enable_power_containment = false; 2665 } 2666 2667 kfree(cac_tables); 2668 2669 return 0; 2670} 2671 2672static int si_program_cac_config_registers(struct radeon_device *rdev, 2673 const struct si_cac_config_reg *cac_config_regs) 2674{ 2675 const struct si_cac_config_reg *config_regs = cac_config_regs; 2676 u32 data = 0, offset; 2677 2678 if (!config_regs) 2679 return -EINVAL; 2680 2681 while (config_regs->offset != 0xFFFFFFFF) { 2682 switch (config_regs->type) { 2683 case SISLANDS_CACCONFIG_CGIND: 2684 offset = SMC_CG_IND_START + config_regs->offset; 2685 if (offset < SMC_CG_IND_END) 2686 data = RREG32_SMC(offset); 2687 break; 2688 default: 2689 data = RREG32(config_regs->offset << 2); 2690 break; 2691 } 2692 2693 data &= ~config_regs->mask; 2694 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2695 2696 switch (config_regs->type) { 2697 case SISLANDS_CACCONFIG_CGIND: 2698 offset = SMC_CG_IND_START + config_regs->offset; 2699 if (offset < SMC_CG_IND_END) 2700 WREG32_SMC(offset, data); 2701 break; 2702 default: 2703 WREG32(config_regs->offset << 2, data); 2704 break; 2705 } 2706 config_regs++; 2707 } 2708 return 0; 2709} 2710 2711static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2712{ 2713 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2714 struct si_power_info *si_pi = si_get_pi(rdev); 2715 int ret; 2716 2717 if ((ni_pi->enable_cac == false) || 2718 (ni_pi->cac_configuration_required == false)) 2719 return 0; 2720 2721 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2722 if (ret) 2723 return ret; 2724 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2725 if (ret) 2726 return ret; 2727 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2728 if (ret) 2729 return ret; 2730 2731 return 0; 2732} 2733 2734static int si_enable_smc_cac(struct radeon_device *rdev, 2735 struct radeon_ps *radeon_new_state, 2736 bool enable) 2737{ 2738 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2739 struct si_power_info *si_pi = si_get_pi(rdev); 2740 PPSMC_Result smc_result; 2741 int ret = 0; 2742 2743 if (ni_pi->enable_cac) { 2744 if (enable) { 2745 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2746 if (ni_pi->support_cac_long_term_average) { 2747 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2748 if (smc_result != PPSMC_Result_OK) 2749 ni_pi->support_cac_long_term_average = false; 2750 } 2751 2752 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2753 if (smc_result != PPSMC_Result_OK) { 2754 ret = -EINVAL; 2755 ni_pi->cac_enabled = false; 2756 } else { 2757 ni_pi->cac_enabled = true; 2758 } 2759 2760 if (si_pi->enable_dte) { 2761 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2762 if (smc_result != PPSMC_Result_OK) 2763 ret = -EINVAL; 2764 } 2765 } 2766 } else if (ni_pi->cac_enabled) { 2767 if (si_pi->enable_dte) 2768 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2769 2770 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2771 2772 ni_pi->cac_enabled = false; 2773 2774 if (ni_pi->support_cac_long_term_average) 2775 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2776 } 2777 } 2778 return ret; 2779} 2780 2781static int si_init_smc_spll_table(struct radeon_device *rdev) 2782{ 2783 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2784 struct si_power_info *si_pi = si_get_pi(rdev); 2785 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2786 SISLANDS_SMC_SCLK_VALUE sclk_params; 2787 u32 fb_div, p_div; 2788 u32 clk_s, clk_v; 2789 u32 sclk = 0; 2790 int ret = 0; 2791 u32 tmp; 2792 int i; 2793 2794 if (si_pi->spll_table_start == 0) 2795 return -EINVAL; 2796 2797 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2798 if (spll_table == NULL) 2799 return -ENOMEM; 2800 2801 for (i = 0; i < 256; i++) { 2802 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2803 if (ret) 2804 break; 2805 2806 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2807 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2808 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2809 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2810 2811 fb_div &= ~0x00001FFF; 2812 fb_div >>= 1; 2813 clk_v >>= 6; 2814 2815 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2816 ret = -EINVAL; 2817 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2818 ret = -EINVAL; 2819 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2820 ret = -EINVAL; 2821 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2822 ret = -EINVAL; 2823 2824 if (ret) 2825 break; 2826 2827 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2828 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2829 spll_table->freq[i] = cpu_to_be32(tmp); 2830 2831 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2832 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2833 spll_table->ss[i] = cpu_to_be32(tmp); 2834 2835 sclk += 512; 2836 } 2837 2838 2839 if (!ret) 2840 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2841 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2842 si_pi->sram_end); 2843 2844 if (ret) 2845 ni_pi->enable_power_containment = false; 2846 2847 kfree(spll_table); 2848 2849 return ret; 2850} 2851 2852static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2853 u16 vce_voltage) 2854{ 2855 u16 highest_leakage = 0; 2856 struct si_power_info *si_pi = si_get_pi(rdev); 2857 int i; 2858 2859 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2860 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2861 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2862 } 2863 2864 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2865 return highest_leakage; 2866 2867 return vce_voltage; 2868} 2869 2870static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2871 u32 evclk, u32 ecclk, u16 *voltage) 2872{ 2873 u32 i; 2874 int ret = -EINVAL; 2875 struct radeon_vce_clock_voltage_dependency_table *table = 2876 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2877 2878 if (((evclk == 0) && (ecclk == 0)) || 2879 (table && (table->count == 0))) { 2880 *voltage = 0; 2881 return 0; 2882 } 2883 2884 for (i = 0; i < table->count; i++) { 2885 if ((evclk <= table->entries[i].evclk) && 2886 (ecclk <= table->entries[i].ecclk)) { 2887 *voltage = table->entries[i].v; 2888 ret = 0; 2889 break; 2890 } 2891 } 2892 2893 /* if no match return the highest voltage */ 2894 if (ret) 2895 *voltage = table->entries[table->count - 1].v; 2896 2897 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2898 2899 return ret; 2900} 2901 2902static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2903 struct radeon_ps *rps) 2904{ 2905 struct ni_ps *ps = ni_get_ps(rps); 2906 struct radeon_clock_and_voltage_limits *max_limits; 2907 bool disable_mclk_switching = false; 2908 bool disable_sclk_switching = false; 2909 u32 mclk, sclk; 2910 u16 vddc, vddci, min_vce_voltage = 0; 2911 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2912 u32 max_sclk = 0, max_mclk = 0; 2913 int i; 2914 2915 if (rdev->family == CHIP_HAINAN) { 2916 if ((rdev->pdev->revision == 0x81) || 2917 (rdev->pdev->revision == 0xC3) || 2918 (rdev->pdev->device == 0x6660) || 2919 (rdev->pdev->device == 0x6664) || 2920 (rdev->pdev->device == 0x6665) || 2921 (rdev->pdev->device == 0x6667) || 2922 (rdev->pdev->device == 0x666F)) { 2923 max_sclk = 75000; 2924 } 2925 if ((rdev->pdev->revision == 0xC3) || 2926 (rdev->pdev->device == 0x6665)) { 2927 max_sclk = 60000; 2928 max_mclk = 80000; 2929 } 2930 if ((rdev->pdev->device == 0x666f) && 2931 (rdev->pdev->revision == 0x00)) { 2932 max_sclk = 80000; 2933 max_mclk = 95000; 2934 } 2935 } else if (rdev->family == CHIP_OLAND) { 2936 if ((rdev->pdev->revision == 0xC7) || 2937 (rdev->pdev->revision == 0x80) || 2938 (rdev->pdev->revision == 0x81) || 2939 (rdev->pdev->revision == 0x83) || 2940 (rdev->pdev->revision == 0x87) || 2941 (rdev->pdev->device == 0x6604) || 2942 (rdev->pdev->device == 0x6605)) { 2943 max_sclk = 75000; 2944 } 2945 2946 if (rdev->pm.dpm.high_pixelclock_count > 1) 2947 disable_sclk_switching = true; 2948 } 2949 2950 if (rps->vce_active) { 2951 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 2952 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 2953 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 2954 &min_vce_voltage); 2955 } else { 2956 rps->evclk = 0; 2957 rps->ecclk = 0; 2958 } 2959 2960 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2961 ni_dpm_vblank_too_short(rdev)) 2962 disable_mclk_switching = true; 2963 2964 if (rps->vclk || rps->dclk) { 2965 disable_mclk_switching = true; 2966 disable_sclk_switching = true; 2967 } 2968 2969 if (rdev->pm.dpm.ac_power) 2970 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2971 else 2972 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2973 2974 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2975 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2976 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2977 } 2978 if (rdev->pm.dpm.ac_power == false) { 2979 for (i = 0; i < ps->performance_level_count; i++) { 2980 if (ps->performance_levels[i].mclk > max_limits->mclk) 2981 ps->performance_levels[i].mclk = max_limits->mclk; 2982 if (ps->performance_levels[i].sclk > max_limits->sclk) 2983 ps->performance_levels[i].sclk = max_limits->sclk; 2984 if (ps->performance_levels[i].vddc > max_limits->vddc) 2985 ps->performance_levels[i].vddc = max_limits->vddc; 2986 if (ps->performance_levels[i].vddci > max_limits->vddci) 2987 ps->performance_levels[i].vddci = max_limits->vddci; 2988 } 2989 } 2990 2991 /* limit clocks to max supported clocks based on voltage dependency tables */ 2992 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2993 &max_sclk_vddc); 2994 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2995 &max_mclk_vddci); 2996 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2997 &max_mclk_vddc); 2998 2999 for (i = 0; i < ps->performance_level_count; i++) { 3000 if (max_sclk_vddc) { 3001 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3002 ps->performance_levels[i].sclk = max_sclk_vddc; 3003 } 3004 if (max_mclk_vddci) { 3005 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3006 ps->performance_levels[i].mclk = max_mclk_vddci; 3007 } 3008 if (max_mclk_vddc) { 3009 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3010 ps->performance_levels[i].mclk = max_mclk_vddc; 3011 } 3012 if (max_mclk) { 3013 if (ps->performance_levels[i].mclk > max_mclk) 3014 ps->performance_levels[i].mclk = max_mclk; 3015 } 3016 if (max_sclk) { 3017 if (ps->performance_levels[i].sclk > max_sclk) 3018 ps->performance_levels[i].sclk = max_sclk; 3019 } 3020 } 3021 3022 /* XXX validate the min clocks required for display */ 3023 3024 if (disable_mclk_switching) { 3025 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3026 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3027 } else { 3028 mclk = ps->performance_levels[0].mclk; 3029 vddci = ps->performance_levels[0].vddci; 3030 } 3031 3032 if (disable_sclk_switching) { 3033 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3034 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3035 } else { 3036 sclk = ps->performance_levels[0].sclk; 3037 vddc = ps->performance_levels[0].vddc; 3038 } 3039 3040 if (rps->vce_active) { 3041 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3042 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3043 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3044 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3045 } 3046 3047 /* adjusted low state */ 3048 ps->performance_levels[0].sclk = sclk; 3049 ps->performance_levels[0].mclk = mclk; 3050 ps->performance_levels[0].vddc = vddc; 3051 ps->performance_levels[0].vddci = vddci; 3052 3053 if (disable_sclk_switching) { 3054 sclk = ps->performance_levels[0].sclk; 3055 for (i = 1; i < ps->performance_level_count; i++) { 3056 if (sclk < ps->performance_levels[i].sclk) 3057 sclk = ps->performance_levels[i].sclk; 3058 } 3059 for (i = 0; i < ps->performance_level_count; i++) { 3060 ps->performance_levels[i].sclk = sclk; 3061 ps->performance_levels[i].vddc = vddc; 3062 } 3063 } else { 3064 for (i = 1; i < ps->performance_level_count; i++) { 3065 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3066 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3067 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3068 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3069 } 3070 } 3071 3072 if (disable_mclk_switching) { 3073 mclk = ps->performance_levels[0].mclk; 3074 for (i = 1; i < ps->performance_level_count; i++) { 3075 if (mclk < ps->performance_levels[i].mclk) 3076 mclk = ps->performance_levels[i].mclk; 3077 } 3078 for (i = 0; i < ps->performance_level_count; i++) { 3079 ps->performance_levels[i].mclk = mclk; 3080 ps->performance_levels[i].vddci = vddci; 3081 } 3082 } else { 3083 for (i = 1; i < ps->performance_level_count; i++) { 3084 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3085 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3086 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3087 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3088 } 3089 } 3090 3091 for (i = 0; i < ps->performance_level_count; i++) 3092 btc_adjust_clock_combinations(rdev, max_limits, 3093 &ps->performance_levels[i]); 3094 3095 for (i = 0; i < ps->performance_level_count; i++) { 3096 if (ps->performance_levels[i].vddc < min_vce_voltage) 3097 ps->performance_levels[i].vddc = min_vce_voltage; 3098 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3099 ps->performance_levels[i].sclk, 3100 max_limits->vddc, &ps->performance_levels[i].vddc); 3101 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3102 ps->performance_levels[i].mclk, 3103 max_limits->vddci, &ps->performance_levels[i].vddci); 3104 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3105 ps->performance_levels[i].mclk, 3106 max_limits->vddc, &ps->performance_levels[i].vddc); 3107 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3108 rdev->clock.current_dispclk, 3109 max_limits->vddc, &ps->performance_levels[i].vddc); 3110 } 3111 3112 for (i = 0; i < ps->performance_level_count; i++) { 3113 btc_apply_voltage_delta_rules(rdev, 3114 max_limits->vddc, max_limits->vddci, 3115 &ps->performance_levels[i].vddc, 3116 &ps->performance_levels[i].vddci); 3117 } 3118 3119 ps->dc_compatible = true; 3120 for (i = 0; i < ps->performance_level_count; i++) { 3121 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3122 ps->dc_compatible = false; 3123 } 3124} 3125 3126#if 0 3127static int si_read_smc_soft_register(struct radeon_device *rdev, 3128 u16 reg_offset, u32 *value) 3129{ 3130 struct si_power_info *si_pi = si_get_pi(rdev); 3131 3132 return si_read_smc_sram_dword(rdev, 3133 si_pi->soft_regs_start + reg_offset, value, 3134 si_pi->sram_end); 3135} 3136#endif 3137 3138static int si_write_smc_soft_register(struct radeon_device *rdev, 3139 u16 reg_offset, u32 value) 3140{ 3141 struct si_power_info *si_pi = si_get_pi(rdev); 3142 3143 return si_write_smc_sram_dword(rdev, 3144 si_pi->soft_regs_start + reg_offset, 3145 value, si_pi->sram_end); 3146} 3147 3148static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3149{ 3150 bool ret = false; 3151 u32 tmp, width, row, column, bank, density; 3152 bool is_memory_gddr5, is_special; 3153 3154 tmp = RREG32(MC_SEQ_MISC0); 3155 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3156 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3157 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3158 3159 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3160 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3161 3162 tmp = RREG32(MC_ARB_RAMCFG); 3163 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3164 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3165 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3166 3167 density = (1 << (row + column - 20 + bank)) * width; 3168 3169 if ((rdev->pdev->device == 0x6819) && 3170 is_memory_gddr5 && is_special && (density == 0x400)) 3171 ret = true; 3172 3173 return ret; 3174} 3175 3176static void si_get_leakage_vddc(struct radeon_device *rdev) 3177{ 3178 struct si_power_info *si_pi = si_get_pi(rdev); 3179 u16 vddc, count = 0; 3180 int i, ret; 3181 3182 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3183 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3184 3185 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3186 si_pi->leakage_voltage.entries[count].voltage = vddc; 3187 si_pi->leakage_voltage.entries[count].leakage_index = 3188 SISLANDS_LEAKAGE_INDEX0 + i; 3189 count++; 3190 } 3191 } 3192 si_pi->leakage_voltage.count = count; 3193} 3194 3195static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3196 u32 index, u16 *leakage_voltage) 3197{ 3198 struct si_power_info *si_pi = si_get_pi(rdev); 3199 int i; 3200 3201 if (leakage_voltage == NULL) 3202 return -EINVAL; 3203 3204 if ((index & 0xff00) != 0xff00) 3205 return -EINVAL; 3206 3207 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3208 return -EINVAL; 3209 3210 if (index < SISLANDS_LEAKAGE_INDEX0) 3211 return -EINVAL; 3212 3213 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3214 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3215 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3216 return 0; 3217 } 3218 } 3219 return -EAGAIN; 3220} 3221 3222static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3223{ 3224 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3225 bool want_thermal_protection; 3226 enum radeon_dpm_event_src dpm_event_src; 3227 3228 switch (sources) { 3229 case 0: 3230 default: 3231 want_thermal_protection = false; 3232 break; 3233 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3234 want_thermal_protection = true; 3235 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3236 break; 3237 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3238 want_thermal_protection = true; 3239 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3240 break; 3241 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3242 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3243 want_thermal_protection = true; 3244 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3245 break; 3246 } 3247 3248 if (want_thermal_protection) { 3249 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3250 if (pi->thermal_protection) 3251 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3252 } else { 3253 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3254 } 3255} 3256 3257static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3258 enum radeon_dpm_auto_throttle_src source, 3259 bool enable) 3260{ 3261 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3262 3263 if (enable) { 3264 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3265 pi->active_auto_throttle_sources |= 1 << source; 3266 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3267 } 3268 } else { 3269 if (pi->active_auto_throttle_sources & (1 << source)) { 3270 pi->active_auto_throttle_sources &= ~(1 << source); 3271 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3272 } 3273 } 3274} 3275 3276static void si_start_dpm(struct radeon_device *rdev) 3277{ 3278 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3279} 3280 3281static void si_stop_dpm(struct radeon_device *rdev) 3282{ 3283 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3284} 3285 3286static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3287{ 3288 if (enable) 3289 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3290 else 3291 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3292 3293} 3294 3295#if 0 3296static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3297 u32 thermal_level) 3298{ 3299 PPSMC_Result ret; 3300 3301 if (thermal_level == 0) { 3302 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3303 if (ret == PPSMC_Result_OK) 3304 return 0; 3305 else 3306 return -EINVAL; 3307 } 3308 return 0; 3309} 3310 3311static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3312{ 3313 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3314} 3315#endif 3316 3317#if 0 3318static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3319{ 3320 if (ac_power) 3321 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3322 0 : -EINVAL; 3323 3324 return 0; 3325} 3326#endif 3327 3328static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3329 PPSMC_Msg msg, u32 parameter) 3330{ 3331 WREG32(SMC_SCRATCH0, parameter); 3332 return si_send_msg_to_smc(rdev, msg); 3333} 3334 3335static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3336{ 3337 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3338 return -EINVAL; 3339 3340 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3341 0 : -EINVAL; 3342} 3343 3344int si_dpm_force_performance_level(struct radeon_device *rdev, 3345 enum radeon_dpm_forced_level level) 3346{ 3347 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3348 struct ni_ps *ps = ni_get_ps(rps); 3349 u32 levels = ps->performance_level_count; 3350 3351 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3352 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3353 return -EINVAL; 3354 3355 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3356 return -EINVAL; 3357 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3358 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3359 return -EINVAL; 3360 3361 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3362 return -EINVAL; 3363 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3364 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3365 return -EINVAL; 3366 3367 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3368 return -EINVAL; 3369 } 3370 3371 rdev->pm.dpm.forced_level = level; 3372 3373 return 0; 3374} 3375 3376#if 0 3377static int si_set_boot_state(struct radeon_device *rdev) 3378{ 3379 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3380 0 : -EINVAL; 3381} 3382#endif 3383 3384static int si_set_sw_state(struct radeon_device *rdev) 3385{ 3386 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3387 0 : -EINVAL; 3388} 3389 3390static int si_halt_smc(struct radeon_device *rdev) 3391{ 3392 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3393 return -EINVAL; 3394 3395 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3396 0 : -EINVAL; 3397} 3398 3399static int si_resume_smc(struct radeon_device *rdev) 3400{ 3401 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3402 return -EINVAL; 3403 3404 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3405 0 : -EINVAL; 3406} 3407 3408static void si_dpm_start_smc(struct radeon_device *rdev) 3409{ 3410 si_program_jump_on_start(rdev); 3411 si_start_smc(rdev); 3412 si_start_smc_clock(rdev); 3413} 3414 3415static void si_dpm_stop_smc(struct radeon_device *rdev) 3416{ 3417 si_reset_smc(rdev); 3418 si_stop_smc_clock(rdev); 3419} 3420 3421static int si_process_firmware_header(struct radeon_device *rdev) 3422{ 3423 struct si_power_info *si_pi = si_get_pi(rdev); 3424 u32 tmp; 3425 int ret; 3426 3427 ret = si_read_smc_sram_dword(rdev, 3428 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3429 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3430 &tmp, si_pi->sram_end); 3431 if (ret) 3432 return ret; 3433 3434 si_pi->state_table_start = tmp; 3435 3436 ret = si_read_smc_sram_dword(rdev, 3437 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3438 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3439 &tmp, si_pi->sram_end); 3440 if (ret) 3441 return ret; 3442 3443 si_pi->soft_regs_start = tmp; 3444 3445 ret = si_read_smc_sram_dword(rdev, 3446 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3447 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3448 &tmp, si_pi->sram_end); 3449 if (ret) 3450 return ret; 3451 3452 si_pi->mc_reg_table_start = tmp; 3453 3454 ret = si_read_smc_sram_dword(rdev, 3455 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3456 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3457 &tmp, si_pi->sram_end); 3458 if (ret) 3459 return ret; 3460 3461 si_pi->fan_table_start = tmp; 3462 3463 ret = si_read_smc_sram_dword(rdev, 3464 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3465 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3466 &tmp, si_pi->sram_end); 3467 if (ret) 3468 return ret; 3469 3470 si_pi->arb_table_start = tmp; 3471 3472 ret = si_read_smc_sram_dword(rdev, 3473 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3474 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3475 &tmp, si_pi->sram_end); 3476 if (ret) 3477 return ret; 3478 3479 si_pi->cac_table_start = tmp; 3480 3481 ret = si_read_smc_sram_dword(rdev, 3482 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3483 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3484 &tmp, si_pi->sram_end); 3485 if (ret) 3486 return ret; 3487 3488 si_pi->dte_table_start = tmp; 3489 3490 ret = si_read_smc_sram_dword(rdev, 3491 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3492 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3493 &tmp, si_pi->sram_end); 3494 if (ret) 3495 return ret; 3496 3497 si_pi->spll_table_start = tmp; 3498 3499 ret = si_read_smc_sram_dword(rdev, 3500 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3501 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3502 &tmp, si_pi->sram_end); 3503 if (ret) 3504 return ret; 3505 3506 si_pi->papm_cfg_table_start = tmp; 3507 3508 return ret; 3509} 3510 3511static void si_read_clock_registers(struct radeon_device *rdev) 3512{ 3513 struct si_power_info *si_pi = si_get_pi(rdev); 3514 3515 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3516 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3517 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3518 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3519 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3520 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3521 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3522 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3523 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3524 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3525 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3526 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3527 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3528 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3529 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3530} 3531 3532static void si_enable_thermal_protection(struct radeon_device *rdev, 3533 bool enable) 3534{ 3535 if (enable) 3536 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3537 else 3538 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3539} 3540 3541static void si_enable_acpi_power_management(struct radeon_device *rdev) 3542{ 3543 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3544} 3545 3546#if 0 3547static int si_enter_ulp_state(struct radeon_device *rdev) 3548{ 3549 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3550 3551 udelay(25000); 3552 3553 return 0; 3554} 3555 3556static int si_exit_ulp_state(struct radeon_device *rdev) 3557{ 3558 int i; 3559 3560 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3561 3562 udelay(7000); 3563 3564 for (i = 0; i < rdev->usec_timeout; i++) { 3565 if (RREG32(SMC_RESP_0) == 1) 3566 break; 3567 udelay(1000); 3568 } 3569 3570 return 0; 3571} 3572#endif 3573 3574static int si_notify_smc_display_change(struct radeon_device *rdev, 3575 bool has_display) 3576{ 3577 PPSMC_Msg msg = has_display ? 3578 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3579 3580 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3581 0 : -EINVAL; 3582} 3583 3584static void si_program_response_times(struct radeon_device *rdev) 3585{ 3586 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 3587 u32 vddc_dly, acpi_dly, vbi_dly; 3588 u32 reference_clock; 3589 3590 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3591 3592 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3593 3594 if (voltage_response_time == 0) 3595 voltage_response_time = 1000; 3596 3597 acpi_delay_time = 15000; 3598 vbi_time_out = 100000; 3599 3600 reference_clock = radeon_get_xclk(rdev); 3601 3602 vddc_dly = (voltage_response_time * reference_clock) / 100; 3603 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3604 vbi_dly = (vbi_time_out * reference_clock) / 100; 3605 3606 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3607 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3608 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3609 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3610} 3611 3612static void si_program_ds_registers(struct radeon_device *rdev) 3613{ 3614 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3615 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3616 3617 if (eg_pi->sclk_deep_sleep) { 3618 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3619 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3620 ~AUTOSCALE_ON_SS_CLEAR); 3621 } 3622} 3623 3624static void si_program_display_gap(struct radeon_device *rdev) 3625{ 3626 u32 tmp, pipe; 3627 int i; 3628 3629 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3630 if (rdev->pm.dpm.new_active_crtc_count > 0) 3631 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3632 else 3633 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3634 3635 if (rdev->pm.dpm.new_active_crtc_count > 1) 3636 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3637 else 3638 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3639 3640 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3641 3642 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3643 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3644 3645 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3646 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3647 /* find the first active crtc */ 3648 for (i = 0; i < rdev->num_crtc; i++) { 3649 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3650 break; 3651 } 3652 if (i == rdev->num_crtc) 3653 pipe = 0; 3654 else 3655 pipe = i; 3656 3657 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3658 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3659 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3660 } 3661 3662 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3663 * This can be a problem on PowerXpress systems or if you want to use the card 3664 * for offscreen rendering or compute if there are no crtcs enabled. 3665 */ 3666 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3667} 3668 3669static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3670{ 3671 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3672 3673 if (enable) { 3674 if (pi->sclk_ss) 3675 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3676 } else { 3677 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3678 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3679 } 3680} 3681 3682static void si_setup_bsp(struct radeon_device *rdev) 3683{ 3684 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3685 u32 xclk = radeon_get_xclk(rdev); 3686 3687 r600_calculate_u_and_p(pi->asi, 3688 xclk, 3689 16, 3690 &pi->bsp, 3691 &pi->bsu); 3692 3693 r600_calculate_u_and_p(pi->pasi, 3694 xclk, 3695 16, 3696 &pi->pbsp, 3697 &pi->pbsu); 3698 3699 3700 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3701 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3702 3703 WREG32(CG_BSP, pi->dsp); 3704} 3705 3706static void si_program_git(struct radeon_device *rdev) 3707{ 3708 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3709} 3710 3711static void si_program_tp(struct radeon_device *rdev) 3712{ 3713 int i; 3714 enum r600_td td = R600_TD_DFLT; 3715 3716 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3717 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3718 3719 if (td == R600_TD_AUTO) 3720 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3721 else 3722 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3723 3724 if (td == R600_TD_UP) 3725 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3726 3727 if (td == R600_TD_DOWN) 3728 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3729} 3730 3731static void si_program_tpp(struct radeon_device *rdev) 3732{ 3733 WREG32(CG_TPC, R600_TPC_DFLT); 3734} 3735 3736static void si_program_sstp(struct radeon_device *rdev) 3737{ 3738 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3739} 3740 3741static void si_enable_display_gap(struct radeon_device *rdev) 3742{ 3743 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3744 3745 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3746 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3747 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3748 3749 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3750 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3751 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3752 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3753} 3754 3755static void si_program_vc(struct radeon_device *rdev) 3756{ 3757 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3758 3759 WREG32(CG_FTV, pi->vrc); 3760} 3761 3762static void si_clear_vc(struct radeon_device *rdev) 3763{ 3764 WREG32(CG_FTV, 0); 3765} 3766 3767u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3768{ 3769 u8 mc_para_index; 3770 3771 if (memory_clock < 10000) 3772 mc_para_index = 0; 3773 else if (memory_clock >= 80000) 3774 mc_para_index = 0x0f; 3775 else 3776 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3777 return mc_para_index; 3778} 3779 3780u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3781{ 3782 u8 mc_para_index; 3783 3784 if (strobe_mode) { 3785 if (memory_clock < 12500) 3786 mc_para_index = 0x00; 3787 else if (memory_clock > 47500) 3788 mc_para_index = 0x0f; 3789 else 3790 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3791 } else { 3792 if (memory_clock < 65000) 3793 mc_para_index = 0x00; 3794 else if (memory_clock > 135000) 3795 mc_para_index = 0x0f; 3796 else 3797 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3798 } 3799 return mc_para_index; 3800} 3801 3802static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3803{ 3804 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3805 bool strobe_mode = false; 3806 u8 result = 0; 3807 3808 if (mclk <= pi->mclk_strobe_mode_threshold) 3809 strobe_mode = true; 3810 3811 if (pi->mem_gddr5) 3812 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3813 else 3814 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3815 3816 if (strobe_mode) 3817 result |= SISLANDS_SMC_STROBE_ENABLE; 3818 3819 return result; 3820} 3821 3822static int si_upload_firmware(struct radeon_device *rdev) 3823{ 3824 struct si_power_info *si_pi = si_get_pi(rdev); 3825 int ret; 3826 3827 si_reset_smc(rdev); 3828 si_stop_smc_clock(rdev); 3829 3830 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3831 3832 return ret; 3833} 3834 3835static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3836 const struct atom_voltage_table *table, 3837 const struct radeon_phase_shedding_limits_table *limits) 3838{ 3839 u32 data, num_bits, num_levels; 3840 3841 if ((table == NULL) || (limits == NULL)) 3842 return false; 3843 3844 data = table->mask_low; 3845 3846 num_bits = hweight32(data); 3847 3848 if (num_bits == 0) 3849 return false; 3850 3851 num_levels = (1 << num_bits); 3852 3853 if (table->count != num_levels) 3854 return false; 3855 3856 if (limits->count != (num_levels - 1)) 3857 return false; 3858 3859 return true; 3860} 3861 3862void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3863 u32 max_voltage_steps, 3864 struct atom_voltage_table *voltage_table) 3865{ 3866 unsigned int i, diff; 3867 3868 if (voltage_table->count <= max_voltage_steps) 3869 return; 3870 3871 diff = voltage_table->count - max_voltage_steps; 3872 3873 for (i= 0; i < max_voltage_steps; i++) 3874 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3875 3876 voltage_table->count = max_voltage_steps; 3877} 3878 3879static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3880 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3881 struct atom_voltage_table *voltage_table) 3882{ 3883 u32 i; 3884 3885 if (voltage_dependency_table == NULL) 3886 return -EINVAL; 3887 3888 voltage_table->mask_low = 0; 3889 voltage_table->phase_delay = 0; 3890 3891 voltage_table->count = voltage_dependency_table->count; 3892 for (i = 0; i < voltage_table->count; i++) { 3893 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3894 voltage_table->entries[i].smio_low = 0; 3895 } 3896 3897 return 0; 3898} 3899 3900static int si_construct_voltage_tables(struct radeon_device *rdev) 3901{ 3902 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3903 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3904 struct si_power_info *si_pi = si_get_pi(rdev); 3905 int ret; 3906 3907 if (pi->voltage_control) { 3908 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3909 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3910 if (ret) 3911 return ret; 3912 3913 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3914 si_trim_voltage_table_to_fit_state_table(rdev, 3915 SISLANDS_MAX_NO_VREG_STEPS, 3916 &eg_pi->vddc_voltage_table); 3917 } else if (si_pi->voltage_control_svi2) { 3918 ret = si_get_svi2_voltage_table(rdev, 3919 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3920 &eg_pi->vddc_voltage_table); 3921 if (ret) 3922 return ret; 3923 } else { 3924 return -EINVAL; 3925 } 3926 3927 if (eg_pi->vddci_control) { 3928 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3929 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3930 if (ret) 3931 return ret; 3932 3933 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3934 si_trim_voltage_table_to_fit_state_table(rdev, 3935 SISLANDS_MAX_NO_VREG_STEPS, 3936 &eg_pi->vddci_voltage_table); 3937 } 3938 if (si_pi->vddci_control_svi2) { 3939 ret = si_get_svi2_voltage_table(rdev, 3940 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3941 &eg_pi->vddci_voltage_table); 3942 if (ret) 3943 return ret; 3944 } 3945 3946 if (pi->mvdd_control) { 3947 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3948 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3949 3950 if (ret) { 3951 pi->mvdd_control = false; 3952 return ret; 3953 } 3954 3955 if (si_pi->mvdd_voltage_table.count == 0) { 3956 pi->mvdd_control = false; 3957 return -EINVAL; 3958 } 3959 3960 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3961 si_trim_voltage_table_to_fit_state_table(rdev, 3962 SISLANDS_MAX_NO_VREG_STEPS, 3963 &si_pi->mvdd_voltage_table); 3964 } 3965 3966 if (si_pi->vddc_phase_shed_control) { 3967 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3968 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3969 if (ret) 3970 si_pi->vddc_phase_shed_control = false; 3971 3972 if ((si_pi->vddc_phase_shed_table.count == 0) || 3973 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3974 si_pi->vddc_phase_shed_control = false; 3975 } 3976 3977 return 0; 3978} 3979 3980static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3981 const struct atom_voltage_table *voltage_table, 3982 SISLANDS_SMC_STATETABLE *table) 3983{ 3984 unsigned int i; 3985 3986 for (i = 0; i < voltage_table->count; i++) 3987 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3988} 3989 3990static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3991 SISLANDS_SMC_STATETABLE *table) 3992{ 3993 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3994 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3995 struct si_power_info *si_pi = si_get_pi(rdev); 3996 u8 i; 3997 3998 if (si_pi->voltage_control_svi2) { 3999 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4000 si_pi->svc_gpio_id); 4001 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4002 si_pi->svd_gpio_id); 4003 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4004 2); 4005 } else { 4006 if (eg_pi->vddc_voltage_table.count) { 4007 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4008 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4009 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4010 4011 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4012 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4013 table->maxVDDCIndexInPPTable = i; 4014 break; 4015 } 4016 } 4017 } 4018 4019 if (eg_pi->vddci_voltage_table.count) { 4020 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4021 4022 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4023 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4024 } 4025 4026 4027 if (si_pi->mvdd_voltage_table.count) { 4028 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4029 4030 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4031 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4032 } 4033 4034 if (si_pi->vddc_phase_shed_control) { 4035 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4036 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4037 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4038 4039 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4040 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4041 4042 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4043 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4044 } else { 4045 si_pi->vddc_phase_shed_control = false; 4046 } 4047 } 4048 } 4049 4050 return 0; 4051} 4052 4053static int si_populate_voltage_value(struct radeon_device *rdev, 4054 const struct atom_voltage_table *table, 4055 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4056{ 4057 unsigned int i; 4058 4059 for (i = 0; i < table->count; i++) { 4060 if (value <= table->entries[i].value) { 4061 voltage->index = (u8)i; 4062 voltage->value = cpu_to_be16(table->entries[i].value); 4063 break; 4064 } 4065 } 4066 4067 if (i >= table->count) 4068 return -EINVAL; 4069 4070 return 0; 4071} 4072 4073static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4074 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4075{ 4076 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4077 struct si_power_info *si_pi = si_get_pi(rdev); 4078 4079 if (pi->mvdd_control) { 4080 if (mclk <= pi->mvdd_split_frequency) 4081 voltage->index = 0; 4082 else 4083 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4084 4085 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4086 } 4087 return 0; 4088} 4089 4090static int si_get_std_voltage_value(struct radeon_device *rdev, 4091 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4092 u16 *std_voltage) 4093{ 4094 u16 v_index; 4095 bool voltage_found = false; 4096 *std_voltage = be16_to_cpu(voltage->value); 4097 4098 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4099 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4100 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4101 return -EINVAL; 4102 4103 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4104 if (be16_to_cpu(voltage->value) == 4105 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4106 voltage_found = true; 4107 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4108 *std_voltage = 4109 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4110 else 4111 *std_voltage = 4112 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4113 break; 4114 } 4115 } 4116 4117 if (!voltage_found) { 4118 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4119 if (be16_to_cpu(voltage->value) <= 4120 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4121 voltage_found = true; 4122 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4123 *std_voltage = 4124 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4125 else 4126 *std_voltage = 4127 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4128 break; 4129 } 4130 } 4131 } 4132 } else { 4133 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4134 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4135 } 4136 } 4137 4138 return 0; 4139} 4140 4141static int si_populate_std_voltage_value(struct radeon_device *rdev, 4142 u16 value, u8 index, 4143 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4144{ 4145 voltage->index = index; 4146 voltage->value = cpu_to_be16(value); 4147 4148 return 0; 4149} 4150 4151static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4152 const struct radeon_phase_shedding_limits_table *limits, 4153 u16 voltage, u32 sclk, u32 mclk, 4154 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4155{ 4156 unsigned int i; 4157 4158 for (i = 0; i < limits->count; i++) { 4159 if ((voltage <= limits->entries[i].voltage) && 4160 (sclk <= limits->entries[i].sclk) && 4161 (mclk <= limits->entries[i].mclk)) 4162 break; 4163 } 4164 4165 smc_voltage->phase_settings = (u8)i; 4166 4167 return 0; 4168} 4169 4170static int si_init_arb_table_index(struct radeon_device *rdev) 4171{ 4172 struct si_power_info *si_pi = si_get_pi(rdev); 4173 u32 tmp; 4174 int ret; 4175 4176 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4177 if (ret) 4178 return ret; 4179 4180 tmp &= 0x00FFFFFF; 4181 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4182 4183 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4184} 4185 4186static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4187{ 4188 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4189} 4190 4191static int si_reset_to_default(struct radeon_device *rdev) 4192{ 4193 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4194 0 : -EINVAL; 4195} 4196 4197static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4198{ 4199 struct si_power_info *si_pi = si_get_pi(rdev); 4200 u32 tmp; 4201 int ret; 4202 4203 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4204 &tmp, si_pi->sram_end); 4205 if (ret) 4206 return ret; 4207 4208 tmp = (tmp >> 24) & 0xff; 4209 4210 if (tmp == MC_CG_ARB_FREQ_F0) 4211 return 0; 4212 4213 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4214} 4215 4216static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4217 u32 engine_clock) 4218{ 4219 u32 dram_rows; 4220 u32 dram_refresh_rate; 4221 u32 mc_arb_rfsh_rate; 4222 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4223 4224 if (tmp >= 4) 4225 dram_rows = 16384; 4226 else 4227 dram_rows = 1 << (tmp + 10); 4228 4229 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4230 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4231 4232 return mc_arb_rfsh_rate; 4233} 4234 4235static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4236 struct rv7xx_pl *pl, 4237 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4238{ 4239 u32 dram_timing; 4240 u32 dram_timing2; 4241 u32 burst_time; 4242 4243 arb_regs->mc_arb_rfsh_rate = 4244 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4245 4246 radeon_atom_set_engine_dram_timings(rdev, 4247 pl->sclk, 4248 pl->mclk); 4249 4250 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4251 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4252 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4253 4254 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4255 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4256 arb_regs->mc_arb_burst_time = (u8)burst_time; 4257 4258 return 0; 4259} 4260 4261static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4262 struct radeon_ps *radeon_state, 4263 unsigned int first_arb_set) 4264{ 4265 struct si_power_info *si_pi = si_get_pi(rdev); 4266 struct ni_ps *state = ni_get_ps(radeon_state); 4267 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4268 int i, ret = 0; 4269 4270 for (i = 0; i < state->performance_level_count; i++) { 4271 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4272 if (ret) 4273 break; 4274 ret = si_copy_bytes_to_smc(rdev, 4275 si_pi->arb_table_start + 4276 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4277 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4278 (u8 *)&arb_regs, 4279 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4280 si_pi->sram_end); 4281 if (ret) 4282 break; 4283 } 4284 4285 return ret; 4286} 4287 4288static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4289 struct radeon_ps *radeon_new_state) 4290{ 4291 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4292 SISLANDS_DRIVER_STATE_ARB_INDEX); 4293} 4294 4295static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4296 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4297{ 4298 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4299 struct si_power_info *si_pi = si_get_pi(rdev); 4300 4301 if (pi->mvdd_control) 4302 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4303 si_pi->mvdd_bootup_value, voltage); 4304 4305 return 0; 4306} 4307 4308static int si_populate_smc_initial_state(struct radeon_device *rdev, 4309 struct radeon_ps *radeon_initial_state, 4310 SISLANDS_SMC_STATETABLE *table) 4311{ 4312 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4313 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4314 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4315 struct si_power_info *si_pi = si_get_pi(rdev); 4316 u32 reg; 4317 int ret; 4318 4319 table->initialState.level.mclk.vDLL_CNTL = 4320 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4321 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = 4322 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4323 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = 4324 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4325 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4326 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4327 table->initialState.level.mclk.vMPLL_FUNC_CNTL = 4328 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4329 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = 4330 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4331 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = 4332 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4333 table->initialState.level.mclk.vMPLL_SS = 4334 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4335 table->initialState.level.mclk.vMPLL_SS2 = 4336 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4337 4338 table->initialState.level.mclk.mclk_value = 4339 cpu_to_be32(initial_state->performance_levels[0].mclk); 4340 4341 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = 4342 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4343 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4344 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4345 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4346 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4347 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4348 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4349 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = 4350 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4351 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4352 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4353 4354 table->initialState.level.sclk.sclk_value = 4355 cpu_to_be32(initial_state->performance_levels[0].sclk); 4356 4357 table->initialState.level.arbRefreshState = 4358 SISLANDS_INITIAL_STATE_ARB_INDEX; 4359 4360 table->initialState.level.ACIndex = 0; 4361 4362 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4363 initial_state->performance_levels[0].vddc, 4364 &table->initialState.level.vddc); 4365 4366 if (!ret) { 4367 u16 std_vddc; 4368 4369 ret = si_get_std_voltage_value(rdev, 4370 &table->initialState.level.vddc, 4371 &std_vddc); 4372 if (!ret) 4373 si_populate_std_voltage_value(rdev, std_vddc, 4374 table->initialState.level.vddc.index, 4375 &table->initialState.level.std_vddc); 4376 } 4377 4378 if (eg_pi->vddci_control) 4379 si_populate_voltage_value(rdev, 4380 &eg_pi->vddci_voltage_table, 4381 initial_state->performance_levels[0].vddci, 4382 &table->initialState.level.vddci); 4383 4384 if (si_pi->vddc_phase_shed_control) 4385 si_populate_phase_shedding_value(rdev, 4386 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4387 initial_state->performance_levels[0].vddc, 4388 initial_state->performance_levels[0].sclk, 4389 initial_state->performance_levels[0].mclk, 4390 &table->initialState.level.vddc); 4391 4392 si_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd); 4393 4394 reg = CG_R(0xffff) | CG_L(0); 4395 table->initialState.level.aT = cpu_to_be32(reg); 4396 4397 table->initialState.level.bSP = cpu_to_be32(pi->dsp); 4398 4399 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; 4400 4401 if (pi->mem_gddr5) { 4402 table->initialState.level.strobeMode = 4403 si_get_strobe_mode_settings(rdev, 4404 initial_state->performance_levels[0].mclk); 4405 4406 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4407 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4408 else 4409 table->initialState.level.mcFlags = 0; 4410 } 4411 4412 table->initialState.levelCount = 1; 4413 4414 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4415 4416 table->initialState.level.dpm2.MaxPS = 0; 4417 table->initialState.level.dpm2.NearTDPDec = 0; 4418 table->initialState.level.dpm2.AboveSafeInc = 0; 4419 table->initialState.level.dpm2.BelowSafeInc = 0; 4420 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; 4421 4422 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4423 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); 4424 4425 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4426 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 4427 4428 return 0; 4429} 4430 4431static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4432 SISLANDS_SMC_STATETABLE *table) 4433{ 4434 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4435 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4436 struct si_power_info *si_pi = si_get_pi(rdev); 4437 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4438 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4439 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4440 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4441 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4442 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4443 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4444 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4445 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4446 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4447 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4448 u32 reg; 4449 int ret; 4450 4451 table->ACPIState = table->initialState; 4452 4453 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4454 4455 if (pi->acpi_vddc) { 4456 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4457 pi->acpi_vddc, &table->ACPIState.level.vddc); 4458 if (!ret) { 4459 u16 std_vddc; 4460 4461 ret = si_get_std_voltage_value(rdev, 4462 &table->ACPIState.level.vddc, &std_vddc); 4463 if (!ret) 4464 si_populate_std_voltage_value(rdev, std_vddc, 4465 table->ACPIState.level.vddc.index, 4466 &table->ACPIState.level.std_vddc); 4467 } 4468 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; 4469 4470 if (si_pi->vddc_phase_shed_control) { 4471 si_populate_phase_shedding_value(rdev, 4472 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4473 pi->acpi_vddc, 4474 0, 4475 0, 4476 &table->ACPIState.level.vddc); 4477 } 4478 } else { 4479 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4480 pi->min_vddc_in_table, &table->ACPIState.level.vddc); 4481 if (!ret) { 4482 u16 std_vddc; 4483 4484 ret = si_get_std_voltage_value(rdev, 4485 &table->ACPIState.level.vddc, &std_vddc); 4486 4487 if (!ret) 4488 si_populate_std_voltage_value(rdev, std_vddc, 4489 table->ACPIState.level.vddc.index, 4490 &table->ACPIState.level.std_vddc); 4491 } 4492 table->ACPIState.level.gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4493 si_pi->sys_pcie_mask, 4494 si_pi->boot_pcie_gen, 4495 RADEON_PCIE_GEN1); 4496 4497 if (si_pi->vddc_phase_shed_control) 4498 si_populate_phase_shedding_value(rdev, 4499 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4500 pi->min_vddc_in_table, 4501 0, 4502 0, 4503 &table->ACPIState.level.vddc); 4504 } 4505 4506 if (pi->acpi_vddc) { 4507 if (eg_pi->acpi_vddci) 4508 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4509 eg_pi->acpi_vddci, 4510 &table->ACPIState.level.vddci); 4511 } 4512 4513 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4514 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4515 4516 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4517 4518 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4519 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4520 4521 table->ACPIState.level.mclk.vDLL_CNTL = 4522 cpu_to_be32(dll_cntl); 4523 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = 4524 cpu_to_be32(mclk_pwrmgt_cntl); 4525 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = 4526 cpu_to_be32(mpll_ad_func_cntl); 4527 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4528 cpu_to_be32(mpll_dq_func_cntl); 4529 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = 4530 cpu_to_be32(mpll_func_cntl); 4531 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = 4532 cpu_to_be32(mpll_func_cntl_1); 4533 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = 4534 cpu_to_be32(mpll_func_cntl_2); 4535 table->ACPIState.level.mclk.vMPLL_SS = 4536 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4537 table->ACPIState.level.mclk.vMPLL_SS2 = 4538 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4539 4540 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = 4541 cpu_to_be32(spll_func_cntl); 4542 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4543 cpu_to_be32(spll_func_cntl_2); 4544 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4545 cpu_to_be32(spll_func_cntl_3); 4546 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4547 cpu_to_be32(spll_func_cntl_4); 4548 4549 table->ACPIState.level.mclk.mclk_value = 0; 4550 table->ACPIState.level.sclk.sclk_value = 0; 4551 4552 si_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd); 4553 4554 if (eg_pi->dynamic_ac_timing) 4555 table->ACPIState.level.ACIndex = 0; 4556 4557 table->ACPIState.level.dpm2.MaxPS = 0; 4558 table->ACPIState.level.dpm2.NearTDPDec = 0; 4559 table->ACPIState.level.dpm2.AboveSafeInc = 0; 4560 table->ACPIState.level.dpm2.BelowSafeInc = 0; 4561 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; 4562 4563 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4564 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); 4565 4566 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4567 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 4568 4569 return 0; 4570} 4571 4572static int si_populate_ulv_state(struct radeon_device *rdev, 4573 struct SISLANDS_SMC_SWSTATE_SINGLE *state) 4574{ 4575 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4576 struct si_power_info *si_pi = si_get_pi(rdev); 4577 struct si_ulv_param *ulv = &si_pi->ulv; 4578 u32 sclk_in_sr = 1350; /* ??? */ 4579 int ret; 4580 4581 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4582 &state->level); 4583 if (!ret) { 4584 if (eg_pi->sclk_deep_sleep) { 4585 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4586 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4587 else 4588 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4589 } 4590 if (ulv->one_pcie_lane_in_ulv) 4591 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4592 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4593 state->level.ACIndex = 1; 4594 state->level.std_vddc = state->level.vddc; 4595 state->levelCount = 1; 4596 4597 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4598 } 4599 4600 return ret; 4601} 4602 4603static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4604{ 4605 struct si_power_info *si_pi = si_get_pi(rdev); 4606 struct si_ulv_param *ulv = &si_pi->ulv; 4607 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4608 int ret; 4609 4610 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4611 &arb_regs); 4612 if (ret) 4613 return ret; 4614 4615 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4616 ulv->volt_change_delay); 4617 4618 ret = si_copy_bytes_to_smc(rdev, 4619 si_pi->arb_table_start + 4620 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4621 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4622 (u8 *)&arb_regs, 4623 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4624 si_pi->sram_end); 4625 4626 return ret; 4627} 4628 4629static void si_get_mvdd_configuration(struct radeon_device *rdev) 4630{ 4631 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4632 4633 pi->mvdd_split_frequency = 30000; 4634} 4635 4636static int si_init_smc_table(struct radeon_device *rdev) 4637{ 4638 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4639 struct si_power_info *si_pi = si_get_pi(rdev); 4640 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4641 const struct si_ulv_param *ulv = &si_pi->ulv; 4642 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4643 int ret; 4644 u32 lane_width; 4645 u32 vr_hot_gpio; 4646 4647 si_populate_smc_voltage_tables(rdev, table); 4648 4649 switch (rdev->pm.int_thermal_type) { 4650 case THERMAL_TYPE_SI: 4651 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4652 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4653 break; 4654 case THERMAL_TYPE_NONE: 4655 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4656 break; 4657 default: 4658 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4659 break; 4660 } 4661 4662 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4663 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4664 4665 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4666 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4667 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4668 } 4669 4670 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4671 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4672 4673 if (pi->mem_gddr5) 4674 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4675 4676 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4677 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4678 4679 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4680 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4681 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4682 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4683 vr_hot_gpio); 4684 } 4685 4686 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4687 if (ret) 4688 return ret; 4689 4690 ret = si_populate_smc_acpi_state(rdev, table); 4691 if (ret) 4692 return ret; 4693 4694 table->driverState.flags = table->initialState.flags; 4695 table->driverState.levelCount = table->initialState.levelCount; 4696 table->driverState.levels[0] = table->initialState.level; 4697 4698 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4699 SISLANDS_INITIAL_STATE_ARB_INDEX); 4700 if (ret) 4701 return ret; 4702 4703 if (ulv->supported && ulv->pl.vddc) { 4704 ret = si_populate_ulv_state(rdev, &table->ULVState); 4705 if (ret) 4706 return ret; 4707 4708 ret = si_program_ulv_memory_timing_parameters(rdev); 4709 if (ret) 4710 return ret; 4711 4712 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4713 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4714 4715 lane_width = radeon_get_pcie_lanes(rdev); 4716 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4717 } else { 4718 table->ULVState = table->initialState; 4719 } 4720 4721 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4722 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4723 si_pi->sram_end); 4724} 4725 4726static int si_calculate_sclk_params(struct radeon_device *rdev, 4727 u32 engine_clock, 4728 SISLANDS_SMC_SCLK_VALUE *sclk) 4729{ 4730 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4731 struct si_power_info *si_pi = si_get_pi(rdev); 4732 struct atom_clock_dividers dividers; 4733 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4734 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4735 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4736 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4737 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4738 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4739 u64 tmp; 4740 u32 reference_clock = rdev->clock.spll.reference_freq; 4741 u32 reference_divider; 4742 u32 fbdiv; 4743 int ret; 4744 4745 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4746 engine_clock, false, ÷rs); 4747 if (ret) 4748 return ret; 4749 4750 reference_divider = 1 + dividers.ref_div; 4751 4752 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4753 do_div(tmp, reference_clock); 4754 fbdiv = (u32) tmp; 4755 4756 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4757 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4758 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4759 4760 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4761 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4762 4763 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4764 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4765 spll_func_cntl_3 |= SPLL_DITHEN; 4766 4767 if (pi->sclk_ss) { 4768 struct radeon_atom_ss ss; 4769 u32 vco_freq = engine_clock * dividers.post_div; 4770 4771 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4772 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4773 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4774 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4775 4776 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4777 cg_spll_spread_spectrum |= CLK_S(clk_s); 4778 cg_spll_spread_spectrum |= SSEN; 4779 4780 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4781 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4782 } 4783 } 4784 4785 sclk->sclk_value = engine_clock; 4786 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4787 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4788 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4789 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4790 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4791 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4792 4793 return 0; 4794} 4795 4796static int si_populate_sclk_value(struct radeon_device *rdev, 4797 u32 engine_clock, 4798 SISLANDS_SMC_SCLK_VALUE *sclk) 4799{ 4800 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4801 int ret; 4802 4803 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4804 if (!ret) { 4805 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4806 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4807 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4808 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4809 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4810 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4811 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4812 } 4813 4814 return ret; 4815} 4816 4817static int si_populate_mclk_value(struct radeon_device *rdev, 4818 u32 engine_clock, 4819 u32 memory_clock, 4820 SISLANDS_SMC_MCLK_VALUE *mclk, 4821 bool strobe_mode, 4822 bool dll_state_on) 4823{ 4824 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4825 struct si_power_info *si_pi = si_get_pi(rdev); 4826 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4827 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4828 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4829 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4830 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4831 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4832 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4833 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4834 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4835 struct atom_mpll_param mpll_param; 4836 int ret; 4837 4838 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4839 if (ret) 4840 return ret; 4841 4842 mpll_func_cntl &= ~BWCTRL_MASK; 4843 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4844 4845 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4846 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4847 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4848 4849 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4850 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4851 4852 if (pi->mem_gddr5) { 4853 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4854 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4855 YCLK_POST_DIV(mpll_param.post_div); 4856 } 4857 4858 if (pi->mclk_ss) { 4859 struct radeon_atom_ss ss; 4860 u32 freq_nom; 4861 u32 tmp; 4862 u32 reference_clock = rdev->clock.mpll.reference_freq; 4863 4864 if (pi->mem_gddr5) 4865 freq_nom = memory_clock * 4; 4866 else 4867 freq_nom = memory_clock * 2; 4868 4869 tmp = freq_nom / reference_clock; 4870 tmp = tmp * tmp; 4871 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4872 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4873 u32 clks = reference_clock * 5 / ss.rate; 4874 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4875 4876 mpll_ss1 &= ~CLKV_MASK; 4877 mpll_ss1 |= CLKV(clkv); 4878 4879 mpll_ss2 &= ~CLKS_MASK; 4880 mpll_ss2 |= CLKS(clks); 4881 } 4882 } 4883 4884 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4885 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4886 4887 if (dll_state_on) 4888 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4889 else 4890 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4891 4892 mclk->mclk_value = cpu_to_be32(memory_clock); 4893 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4894 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4895 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4896 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4897 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4898 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4899 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4900 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4901 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4902 4903 return 0; 4904} 4905 4906static void si_populate_smc_sp(struct radeon_device *rdev, 4907 struct radeon_ps *radeon_state, 4908 SISLANDS_SMC_SWSTATE *smc_state) 4909{ 4910 struct ni_ps *ps = ni_get_ps(radeon_state); 4911 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4912 int i; 4913 4914 for (i = 0; i < ps->performance_level_count - 1; i++) 4915 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4916 4917 smc_state->levels[ps->performance_level_count - 1].bSP = 4918 cpu_to_be32(pi->psp); 4919} 4920 4921static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4922 struct rv7xx_pl *pl, 4923 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4924{ 4925 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4926 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4927 struct si_power_info *si_pi = si_get_pi(rdev); 4928 int ret; 4929 bool dll_state_on; 4930 u16 std_vddc; 4931 bool gmc_pg = false; 4932 4933 if (eg_pi->pcie_performance_request && 4934 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4935 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4936 else 4937 level->gen2PCIE = (u8)pl->pcie_gen; 4938 4939 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4940 if (ret) 4941 return ret; 4942 4943 level->mcFlags = 0; 4944 4945 if (pi->mclk_stutter_mode_threshold && 4946 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4947 !eg_pi->uvd_enabled && 4948 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4949 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4950 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4951 4952 if (gmc_pg) 4953 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4954 } 4955 4956 if (pi->mem_gddr5) { 4957 if (pl->mclk > pi->mclk_edc_enable_threshold) 4958 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4959 4960 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4961 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4962 4963 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4964 4965 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4966 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4967 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4968 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4969 else 4970 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4971 } else { 4972 dll_state_on = false; 4973 } 4974 } else { 4975 level->strobeMode = si_get_strobe_mode_settings(rdev, 4976 pl->mclk); 4977 4978 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4979 } 4980 4981 ret = si_populate_mclk_value(rdev, 4982 pl->sclk, 4983 pl->mclk, 4984 &level->mclk, 4985 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4986 if (ret) 4987 return ret; 4988 4989 ret = si_populate_voltage_value(rdev, 4990 &eg_pi->vddc_voltage_table, 4991 pl->vddc, &level->vddc); 4992 if (ret) 4993 return ret; 4994 4995 4996 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4997 if (ret) 4998 return ret; 4999 5000 ret = si_populate_std_voltage_value(rdev, std_vddc, 5001 level->vddc.index, &level->std_vddc); 5002 if (ret) 5003 return ret; 5004 5005 if (eg_pi->vddci_control) { 5006 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5007 pl->vddci, &level->vddci); 5008 if (ret) 5009 return ret; 5010 } 5011 5012 if (si_pi->vddc_phase_shed_control) { 5013 ret = si_populate_phase_shedding_value(rdev, 5014 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5015 pl->vddc, 5016 pl->sclk, 5017 pl->mclk, 5018 &level->vddc); 5019 if (ret) 5020 return ret; 5021 } 5022 5023 level->MaxPoweredUpCU = si_pi->max_cu; 5024 5025 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5026 5027 return ret; 5028} 5029 5030static int si_populate_smc_t(struct radeon_device *rdev, 5031 struct radeon_ps *radeon_state, 5032 SISLANDS_SMC_SWSTATE *smc_state) 5033{ 5034 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5035 struct ni_ps *state = ni_get_ps(radeon_state); 5036 u32 a_t; 5037 u32 t_l, t_h; 5038 u32 high_bsp; 5039 int i, ret; 5040 5041 if (state->performance_level_count >= 9) 5042 return -EINVAL; 5043 5044 if (state->performance_level_count < 2) { 5045 a_t = CG_R(0xffff) | CG_L(0); 5046 smc_state->levels[0].aT = cpu_to_be32(a_t); 5047 return 0; 5048 } 5049 5050 smc_state->levels[0].aT = cpu_to_be32(0); 5051 5052 for (i = 0; i <= state->performance_level_count - 2; i++) { 5053 ret = r600_calculate_at( 5054 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5055 100 * R600_AH_DFLT, 5056 state->performance_levels[i + 1].sclk, 5057 state->performance_levels[i].sclk, 5058 &t_l, 5059 &t_h); 5060 5061 if (ret) { 5062 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5063 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5064 } 5065 5066 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5067 a_t |= CG_R(t_l * pi->bsp / 20000); 5068 smc_state->levels[i].aT = cpu_to_be32(a_t); 5069 5070 high_bsp = (i == state->performance_level_count - 2) ? 5071 pi->pbsp : pi->bsp; 5072 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5073 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5074 } 5075 5076 return 0; 5077} 5078 5079static int si_disable_ulv(struct radeon_device *rdev) 5080{ 5081 struct si_power_info *si_pi = si_get_pi(rdev); 5082 struct si_ulv_param *ulv = &si_pi->ulv; 5083 5084 if (ulv->supported) 5085 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5086 0 : -EINVAL; 5087 5088 return 0; 5089} 5090 5091static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5092 struct radeon_ps *radeon_state) 5093{ 5094 const struct si_power_info *si_pi = si_get_pi(rdev); 5095 const struct si_ulv_param *ulv = &si_pi->ulv; 5096 const struct ni_ps *state = ni_get_ps(radeon_state); 5097 int i; 5098 5099 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5100 return false; 5101 5102 /* XXX validate against display requirements! */ 5103 5104 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5105 if (rdev->clock.current_dispclk <= 5106 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5107 if (ulv->pl.vddc < 5108 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5109 return false; 5110 } 5111 } 5112 5113 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5114 return false; 5115 5116 return true; 5117} 5118 5119static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5120 struct radeon_ps *radeon_new_state) 5121{ 5122 const struct si_power_info *si_pi = si_get_pi(rdev); 5123 const struct si_ulv_param *ulv = &si_pi->ulv; 5124 5125 if (ulv->supported) { 5126 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5127 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5128 0 : -EINVAL; 5129 } 5130 return 0; 5131} 5132 5133static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5134 struct radeon_ps *radeon_state, 5135 SISLANDS_SMC_SWSTATE *smc_state) 5136{ 5137 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5138 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5139 struct si_power_info *si_pi = si_get_pi(rdev); 5140 struct ni_ps *state = ni_get_ps(radeon_state); 5141 int i, ret; 5142 u32 threshold; 5143 u32 sclk_in_sr = 1350; /* ??? */ 5144 5145 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5146 return -EINVAL; 5147 5148 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5149 5150 if (radeon_state->vclk && radeon_state->dclk) { 5151 eg_pi->uvd_enabled = true; 5152 if (eg_pi->smu_uvd_hs) 5153 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5154 } else { 5155 eg_pi->uvd_enabled = false; 5156 } 5157 5158 if (state->dc_compatible) 5159 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5160 5161 smc_state->levelCount = 0; 5162 for (i = 0; i < state->performance_level_count; i++) { 5163 if (eg_pi->sclk_deep_sleep) { 5164 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5165 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5166 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5167 else 5168 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5169 } 5170 } 5171 5172 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5173 &smc_state->levels[i]); 5174 smc_state->levels[i].arbRefreshState = 5175 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5176 5177 if (ret) 5178 return ret; 5179 5180 if (ni_pi->enable_power_containment) 5181 smc_state->levels[i].displayWatermark = 5182 (state->performance_levels[i].sclk < threshold) ? 5183 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5184 else 5185 smc_state->levels[i].displayWatermark = (i < 2) ? 5186 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5187 5188 if (eg_pi->dynamic_ac_timing) 5189 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5190 else 5191 smc_state->levels[i].ACIndex = 0; 5192 5193 smc_state->levelCount++; 5194 } 5195 5196 si_write_smc_soft_register(rdev, 5197 SI_SMC_SOFT_REGISTER_watermark_threshold, 5198 threshold / 512); 5199 5200 si_populate_smc_sp(rdev, radeon_state, smc_state); 5201 5202 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5203 if (ret) 5204 ni_pi->enable_power_containment = false; 5205 5206 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5207 if (ret) 5208 ni_pi->enable_sq_ramping = false; 5209 5210 return si_populate_smc_t(rdev, radeon_state, smc_state); 5211} 5212 5213static int si_upload_sw_state(struct radeon_device *rdev, 5214 struct radeon_ps *radeon_new_state) 5215{ 5216 struct si_power_info *si_pi = si_get_pi(rdev); 5217 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5218 int ret; 5219 u32 address = si_pi->state_table_start + 5220 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5221 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5222 size_t state_size = struct_size(smc_state, levels, 5223 new_state->performance_level_count); 5224 5225 memset(smc_state, 0, state_size); 5226 5227 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5228 if (ret) 5229 return ret; 5230 5231 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5232 state_size, si_pi->sram_end); 5233 5234 return ret; 5235} 5236 5237static int si_upload_ulv_state(struct radeon_device *rdev) 5238{ 5239 struct si_power_info *si_pi = si_get_pi(rdev); 5240 struct si_ulv_param *ulv = &si_pi->ulv; 5241 int ret = 0; 5242 5243 if (ulv->supported && ulv->pl.vddc) { 5244 u32 address = si_pi->state_table_start + 5245 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5246 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; 5247 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE); 5248 5249 memset(smc_state, 0, state_size); 5250 5251 ret = si_populate_ulv_state(rdev, smc_state); 5252 if (!ret) 5253 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5254 state_size, si_pi->sram_end); 5255 } 5256 5257 return ret; 5258} 5259 5260static int si_upload_smc_data(struct radeon_device *rdev) 5261{ 5262 struct radeon_crtc *radeon_crtc = NULL; 5263 int i; 5264 5265 if (rdev->pm.dpm.new_active_crtc_count == 0) 5266 return 0; 5267 5268 for (i = 0; i < rdev->num_crtc; i++) { 5269 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5270 radeon_crtc = rdev->mode_info.crtcs[i]; 5271 break; 5272 } 5273 } 5274 5275 if (radeon_crtc == NULL) 5276 return 0; 5277 5278 if (radeon_crtc->line_time <= 0) 5279 return 0; 5280 5281 if (si_write_smc_soft_register(rdev, 5282 SI_SMC_SOFT_REGISTER_crtc_index, 5283 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5284 return 0; 5285 5286 if (si_write_smc_soft_register(rdev, 5287 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5288 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5289 return 0; 5290 5291 if (si_write_smc_soft_register(rdev, 5292 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5293 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5294 return 0; 5295 5296 return 0; 5297} 5298 5299static int si_set_mc_special_registers(struct radeon_device *rdev, 5300 struct si_mc_reg_table *table) 5301{ 5302 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5303 u8 i, j, k; 5304 u32 temp_reg; 5305 5306 for (i = 0, j = table->last; i < table->last; i++) { 5307 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5308 return -EINVAL; 5309 switch (table->mc_reg_address[i].s1 << 2) { 5310 case MC_SEQ_MISC1: 5311 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5312 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5313 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5314 for (k = 0; k < table->num_entries; k++) 5315 table->mc_reg_table_entry[k].mc_data[j] = 5316 ((temp_reg & 0xffff0000)) | 5317 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5318 j++; 5319 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5320 return -EINVAL; 5321 5322 temp_reg = RREG32(MC_PMG_CMD_MRS); 5323 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5324 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5325 for (k = 0; k < table->num_entries; k++) { 5326 table->mc_reg_table_entry[k].mc_data[j] = 5327 (temp_reg & 0xffff0000) | 5328 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5329 if (!pi->mem_gddr5) 5330 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5331 } 5332 j++; 5333 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5334 return -EINVAL; 5335 5336 if (!pi->mem_gddr5) { 5337 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5338 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5339 for (k = 0; k < table->num_entries; k++) 5340 table->mc_reg_table_entry[k].mc_data[j] = 5341 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5342 j++; 5343 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5344 return -EINVAL; 5345 } 5346 break; 5347 case MC_SEQ_RESERVE_M: 5348 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5349 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5350 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5351 for(k = 0; k < table->num_entries; k++) 5352 table->mc_reg_table_entry[k].mc_data[j] = 5353 (temp_reg & 0xffff0000) | 5354 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5355 j++; 5356 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5357 return -EINVAL; 5358 break; 5359 default: 5360 break; 5361 } 5362 } 5363 5364 table->last = j; 5365 5366 return 0; 5367} 5368 5369static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5370{ 5371 bool result = true; 5372 5373 switch (in_reg) { 5374 case MC_SEQ_RAS_TIMING >> 2: 5375 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5376 break; 5377 case MC_SEQ_CAS_TIMING >> 2: 5378 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5379 break; 5380 case MC_SEQ_MISC_TIMING >> 2: 5381 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5382 break; 5383 case MC_SEQ_MISC_TIMING2 >> 2: 5384 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5385 break; 5386 case MC_SEQ_RD_CTL_D0 >> 2: 5387 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5388 break; 5389 case MC_SEQ_RD_CTL_D1 >> 2: 5390 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5391 break; 5392 case MC_SEQ_WR_CTL_D0 >> 2: 5393 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5394 break; 5395 case MC_SEQ_WR_CTL_D1 >> 2: 5396 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5397 break; 5398 case MC_PMG_CMD_EMRS >> 2: 5399 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5400 break; 5401 case MC_PMG_CMD_MRS >> 2: 5402 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5403 break; 5404 case MC_PMG_CMD_MRS1 >> 2: 5405 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5406 break; 5407 case MC_SEQ_PMG_TIMING >> 2: 5408 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5409 break; 5410 case MC_PMG_CMD_MRS2 >> 2: 5411 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5412 break; 5413 case MC_SEQ_WR_CTL_2 >> 2: 5414 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5415 break; 5416 default: 5417 result = false; 5418 break; 5419 } 5420 5421 return result; 5422} 5423 5424static void si_set_valid_flag(struct si_mc_reg_table *table) 5425{ 5426 u8 i, j; 5427 5428 for (i = 0; i < table->last; i++) { 5429 for (j = 1; j < table->num_entries; j++) { 5430 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5431 table->valid_flag |= 1 << i; 5432 break; 5433 } 5434 } 5435 } 5436} 5437 5438static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5439{ 5440 u32 i; 5441 u16 address; 5442 5443 for (i = 0; i < table->last; i++) 5444 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5445 address : table->mc_reg_address[i].s1; 5446 5447} 5448 5449static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5450 struct si_mc_reg_table *si_table) 5451{ 5452 u8 i, j; 5453 5454 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5455 return -EINVAL; 5456 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5457 return -EINVAL; 5458 5459 for (i = 0; i < table->last; i++) 5460 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5461 si_table->last = table->last; 5462 5463 for (i = 0; i < table->num_entries; i++) { 5464 si_table->mc_reg_table_entry[i].mclk_max = 5465 table->mc_reg_table_entry[i].mclk_max; 5466 for (j = 0; j < table->last; j++) { 5467 si_table->mc_reg_table_entry[i].mc_data[j] = 5468 table->mc_reg_table_entry[i].mc_data[j]; 5469 } 5470 } 5471 si_table->num_entries = table->num_entries; 5472 5473 return 0; 5474} 5475 5476static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5477{ 5478 struct si_power_info *si_pi = si_get_pi(rdev); 5479 struct atom_mc_reg_table *table; 5480 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5481 u8 module_index = rv770_get_memory_module_index(rdev); 5482 int ret; 5483 5484 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5485 if (!table) 5486 return -ENOMEM; 5487 5488 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5489 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5490 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5491 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5492 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5493 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5494 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5495 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5496 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5497 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5498 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5499 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5500 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5501 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5502 5503 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5504 if (ret) 5505 goto init_mc_done; 5506 5507 ret = si_copy_vbios_mc_reg_table(table, si_table); 5508 if (ret) 5509 goto init_mc_done; 5510 5511 si_set_s0_mc_reg_index(si_table); 5512 5513 ret = si_set_mc_special_registers(rdev, si_table); 5514 if (ret) 5515 goto init_mc_done; 5516 5517 si_set_valid_flag(si_table); 5518 5519init_mc_done: 5520 kfree(table); 5521 5522 return ret; 5523 5524} 5525 5526static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5527 SMC_SIslands_MCRegisters *mc_reg_table) 5528{ 5529 struct si_power_info *si_pi = si_get_pi(rdev); 5530 u32 i, j; 5531 5532 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5533 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5534 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5535 break; 5536 mc_reg_table->address[i].s0 = 5537 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5538 mc_reg_table->address[i].s1 = 5539 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5540 i++; 5541 } 5542 } 5543 mc_reg_table->last = (u8)i; 5544} 5545 5546static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5547 SMC_SIslands_MCRegisterSet *data, 5548 u32 num_entries, u32 valid_flag) 5549{ 5550 u32 i, j; 5551 5552 for(i = 0, j = 0; j < num_entries; j++) { 5553 if (valid_flag & (1 << j)) { 5554 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5555 i++; 5556 } 5557 } 5558} 5559 5560static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5561 struct rv7xx_pl *pl, 5562 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5563{ 5564 struct si_power_info *si_pi = si_get_pi(rdev); 5565 u32 i = 0; 5566 5567 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5568 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5569 break; 5570 } 5571 5572 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5573 --i; 5574 5575 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5576 mc_reg_table_data, si_pi->mc_reg_table.last, 5577 si_pi->mc_reg_table.valid_flag); 5578} 5579 5580static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5581 struct radeon_ps *radeon_state, 5582 SMC_SIslands_MCRegisters *mc_reg_table) 5583{ 5584 struct ni_ps *state = ni_get_ps(radeon_state); 5585 int i; 5586 5587 for (i = 0; i < state->performance_level_count; i++) { 5588 si_convert_mc_reg_table_entry_to_smc(rdev, 5589 &state->performance_levels[i], 5590 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5591 } 5592} 5593 5594static int si_populate_mc_reg_table(struct radeon_device *rdev, 5595 struct radeon_ps *radeon_boot_state) 5596{ 5597 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5598 struct si_power_info *si_pi = si_get_pi(rdev); 5599 struct si_ulv_param *ulv = &si_pi->ulv; 5600 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5601 5602 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5603 5604 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5605 5606 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5607 5608 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5609 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5610 5611 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5612 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5613 si_pi->mc_reg_table.last, 5614 si_pi->mc_reg_table.valid_flag); 5615 5616 if (ulv->supported && ulv->pl.vddc != 0) 5617 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5618 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5619 else 5620 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5621 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5622 si_pi->mc_reg_table.last, 5623 si_pi->mc_reg_table.valid_flag); 5624 5625 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5626 5627 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5628 (u8 *)smc_mc_reg_table, 5629 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5630} 5631 5632static int si_upload_mc_reg_table(struct radeon_device *rdev, 5633 struct radeon_ps *radeon_new_state) 5634{ 5635 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5636 struct si_power_info *si_pi = si_get_pi(rdev); 5637 u32 address = si_pi->mc_reg_table_start + 5638 offsetof(SMC_SIslands_MCRegisters, 5639 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5640 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5641 5642 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5643 5644 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5645 5646 5647 return si_copy_bytes_to_smc(rdev, address, 5648 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5649 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5650 si_pi->sram_end); 5651 5652} 5653 5654static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5655{ 5656 if (enable) 5657 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5658 else 5659 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5660} 5661 5662static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5663 struct radeon_ps *radeon_state) 5664{ 5665 struct ni_ps *state = ni_get_ps(radeon_state); 5666 int i; 5667 u16 pcie_speed, max_speed = 0; 5668 5669 for (i = 0; i < state->performance_level_count; i++) { 5670 pcie_speed = state->performance_levels[i].pcie_gen; 5671 if (max_speed < pcie_speed) 5672 max_speed = pcie_speed; 5673 } 5674 return max_speed; 5675} 5676 5677static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5678{ 5679 u32 speed_cntl; 5680 5681 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5682 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5683 5684 return (u16)speed_cntl; 5685} 5686 5687static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5688 struct radeon_ps *radeon_new_state, 5689 struct radeon_ps *radeon_current_state) 5690{ 5691 struct si_power_info *si_pi = si_get_pi(rdev); 5692 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5693 enum radeon_pcie_gen current_link_speed; 5694 5695 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5696 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5697 else 5698 current_link_speed = si_pi->force_pcie_gen; 5699 5700 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5701 si_pi->pspp_notify_required = false; 5702 if (target_link_speed > current_link_speed) { 5703 switch (target_link_speed) { 5704#if defined(CONFIG_ACPI) 5705 case RADEON_PCIE_GEN3: 5706 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5707 break; 5708 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5709 if (current_link_speed == RADEON_PCIE_GEN2) 5710 break; 5711 fallthrough; 5712 case RADEON_PCIE_GEN2: 5713 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5714 break; 5715 fallthrough; 5716#endif 5717 default: 5718 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5719 break; 5720 } 5721 } else { 5722 if (target_link_speed < current_link_speed) 5723 si_pi->pspp_notify_required = true; 5724 } 5725} 5726 5727static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5728 struct radeon_ps *radeon_new_state, 5729 struct radeon_ps *radeon_current_state) 5730{ 5731 struct si_power_info *si_pi = si_get_pi(rdev); 5732 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5733 u8 request; 5734 5735 if (si_pi->pspp_notify_required) { 5736 if (target_link_speed == RADEON_PCIE_GEN3) 5737 request = PCIE_PERF_REQ_PECI_GEN3; 5738 else if (target_link_speed == RADEON_PCIE_GEN2) 5739 request = PCIE_PERF_REQ_PECI_GEN2; 5740 else 5741 request = PCIE_PERF_REQ_PECI_GEN1; 5742 5743 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5744 (si_get_current_pcie_speed(rdev) > 0)) 5745 return; 5746 5747#if defined(CONFIG_ACPI) 5748 radeon_acpi_pcie_performance_request(rdev, request, false); 5749#endif 5750 } 5751} 5752 5753#if 0 5754static int si_ds_request(struct radeon_device *rdev, 5755 bool ds_status_on, u32 count_write) 5756{ 5757 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5758 5759 if (eg_pi->sclk_deep_sleep) { 5760 if (ds_status_on) 5761 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5762 PPSMC_Result_OK) ? 5763 0 : -EINVAL; 5764 else 5765 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5766 PPSMC_Result_OK) ? 0 : -EINVAL; 5767 } 5768 return 0; 5769} 5770#endif 5771 5772static void si_set_max_cu_value(struct radeon_device *rdev) 5773{ 5774 struct si_power_info *si_pi = si_get_pi(rdev); 5775 5776 if (rdev->family == CHIP_VERDE) { 5777 switch (rdev->pdev->device) { 5778 case 0x6820: 5779 case 0x6825: 5780 case 0x6821: 5781 case 0x6823: 5782 case 0x6827: 5783 si_pi->max_cu = 10; 5784 break; 5785 case 0x682D: 5786 case 0x6824: 5787 case 0x682F: 5788 case 0x6826: 5789 si_pi->max_cu = 8; 5790 break; 5791 case 0x6828: 5792 case 0x6830: 5793 case 0x6831: 5794 case 0x6838: 5795 case 0x6839: 5796 case 0x683D: 5797 si_pi->max_cu = 10; 5798 break; 5799 case 0x683B: 5800 case 0x683F: 5801 case 0x6829: 5802 si_pi->max_cu = 8; 5803 break; 5804 default: 5805 si_pi->max_cu = 0; 5806 break; 5807 } 5808 } else { 5809 si_pi->max_cu = 0; 5810 } 5811} 5812 5813static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5814 struct radeon_clock_voltage_dependency_table *table) 5815{ 5816 u32 i; 5817 int j; 5818 u16 leakage_voltage; 5819 5820 if (table) { 5821 for (i = 0; i < table->count; i++) { 5822 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5823 table->entries[i].v, 5824 &leakage_voltage)) { 5825 case 0: 5826 table->entries[i].v = leakage_voltage; 5827 break; 5828 case -EAGAIN: 5829 return -EINVAL; 5830 case -EINVAL: 5831 default: 5832 break; 5833 } 5834 } 5835 5836 for (j = (table->count - 2); j >= 0; j--) { 5837 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5838 table->entries[j].v : table->entries[j + 1].v; 5839 } 5840 } 5841 return 0; 5842} 5843 5844static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5845{ 5846 int ret; 5847 5848 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5849 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5850 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5851 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5852 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5853 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5854 return ret; 5855} 5856 5857static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5858 struct radeon_ps *radeon_new_state, 5859 struct radeon_ps *radeon_current_state) 5860{ 5861 u32 lane_width; 5862 u32 new_lane_width = 5863 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5864 u32 current_lane_width = 5865 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5866 5867 if (new_lane_width != current_lane_width) { 5868 radeon_set_pcie_lanes(rdev, new_lane_width); 5869 lane_width = radeon_get_pcie_lanes(rdev); 5870 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5871 } 5872} 5873 5874static void si_set_vce_clock(struct radeon_device *rdev, 5875 struct radeon_ps *new_rps, 5876 struct radeon_ps *old_rps) 5877{ 5878 if ((old_rps->evclk != new_rps->evclk) || 5879 (old_rps->ecclk != new_rps->ecclk)) { 5880 /* turn the clocks on when encoding, off otherwise */ 5881 if (new_rps->evclk || new_rps->ecclk) 5882 vce_v1_0_enable_mgcg(rdev, false); 5883 else 5884 vce_v1_0_enable_mgcg(rdev, true); 5885 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5886 } 5887} 5888 5889void si_dpm_setup_asic(struct radeon_device *rdev) 5890{ 5891 int r; 5892 5893 r = si_mc_load_microcode(rdev); 5894 if (r) 5895 DRM_ERROR("Failed to load MC firmware!\n"); 5896 rv770_get_memory_type(rdev); 5897 si_read_clock_registers(rdev); 5898 si_enable_acpi_power_management(rdev); 5899} 5900 5901static int si_thermal_enable_alert(struct radeon_device *rdev, 5902 bool enable) 5903{ 5904 u32 thermal_int = RREG32(CG_THERMAL_INT); 5905 5906 if (enable) { 5907 PPSMC_Result result; 5908 5909 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5910 WREG32(CG_THERMAL_INT, thermal_int); 5911 rdev->irq.dpm_thermal = false; 5912 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5913 if (result != PPSMC_Result_OK) { 5914 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5915 return -EINVAL; 5916 } 5917 } else { 5918 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5919 WREG32(CG_THERMAL_INT, thermal_int); 5920 rdev->irq.dpm_thermal = true; 5921 } 5922 5923 return 0; 5924} 5925 5926static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5927 int min_temp, int max_temp) 5928{ 5929 int low_temp = 0 * 1000; 5930 int high_temp = 255 * 1000; 5931 5932 if (low_temp < min_temp) 5933 low_temp = min_temp; 5934 if (high_temp > max_temp) 5935 high_temp = max_temp; 5936 if (high_temp < low_temp) { 5937 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5938 return -EINVAL; 5939 } 5940 5941 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5942 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5943 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5944 5945 rdev->pm.dpm.thermal.min_temp = low_temp; 5946 rdev->pm.dpm.thermal.max_temp = high_temp; 5947 5948 return 0; 5949} 5950 5951static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 5952{ 5953 struct si_power_info *si_pi = si_get_pi(rdev); 5954 u32 tmp; 5955 5956 if (si_pi->fan_ctrl_is_in_default_mode) { 5957 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 5958 si_pi->fan_ctrl_default_mode = tmp; 5959 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 5960 si_pi->t_min = tmp; 5961 si_pi->fan_ctrl_is_in_default_mode = false; 5962 } 5963 5964 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 5965 tmp |= TMIN(0); 5966 WREG32(CG_FDO_CTRL2, tmp); 5967 5968 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 5969 tmp |= FDO_PWM_MODE(mode); 5970 WREG32(CG_FDO_CTRL2, tmp); 5971} 5972 5973static int si_thermal_setup_fan_table(struct radeon_device *rdev) 5974{ 5975 struct si_power_info *si_pi = si_get_pi(rdev); 5976 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 5977 u32 duty100; 5978 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 5979 u16 fdo_min, slope1, slope2; 5980 u32 reference_clock, tmp; 5981 int ret; 5982 u64 tmp64; 5983 5984 if (!si_pi->fan_table_start) { 5985 rdev->pm.dpm.fan.ucode_fan_control = false; 5986 return 0; 5987 } 5988 5989 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 5990 5991 if (duty100 == 0) { 5992 rdev->pm.dpm.fan.ucode_fan_control = false; 5993 return 0; 5994 } 5995 5996 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 5997 do_div(tmp64, 10000); 5998 fdo_min = (u16)tmp64; 5999 6000 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6001 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6002 6003 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6004 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6005 6006 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6007 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6008 6009 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6010 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6011 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6012 6013 fan_table.slope1 = cpu_to_be16(slope1); 6014 fan_table.slope2 = cpu_to_be16(slope2); 6015 6016 fan_table.fdo_min = cpu_to_be16(fdo_min); 6017 6018 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6019 6020 fan_table.hys_up = cpu_to_be16(1); 6021 6022 fan_table.hys_slope = cpu_to_be16(1); 6023 6024 fan_table.temp_resp_lim = cpu_to_be16(5); 6025 6026 reference_clock = radeon_get_xclk(rdev); 6027 6028 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6029 reference_clock) / 1600); 6030 6031 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6032 6033 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6034 fan_table.temp_src = (uint8_t)tmp; 6035 6036 ret = si_copy_bytes_to_smc(rdev, 6037 si_pi->fan_table_start, 6038 (u8 *)(&fan_table), 6039 sizeof(fan_table), 6040 si_pi->sram_end); 6041 6042 if (ret) { 6043 DRM_ERROR("Failed to load fan table to the SMC."); 6044 rdev->pm.dpm.fan.ucode_fan_control = false; 6045 } 6046 6047 return 0; 6048} 6049 6050static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6051{ 6052 struct si_power_info *si_pi = si_get_pi(rdev); 6053 PPSMC_Result ret; 6054 6055 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6056 if (ret == PPSMC_Result_OK) { 6057 si_pi->fan_is_controlled_by_smc = true; 6058 return 0; 6059 } else { 6060 return -EINVAL; 6061 } 6062} 6063 6064static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6065{ 6066 struct si_power_info *si_pi = si_get_pi(rdev); 6067 PPSMC_Result ret; 6068 6069 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6070 6071 if (ret == PPSMC_Result_OK) { 6072 si_pi->fan_is_controlled_by_smc = false; 6073 return 0; 6074 } else { 6075 return -EINVAL; 6076 } 6077} 6078 6079int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6080 u32 *speed) 6081{ 6082 u32 duty, duty100; 6083 u64 tmp64; 6084 6085 if (rdev->pm.no_fan) 6086 return -ENOENT; 6087 6088 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6089 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6090 6091 if (duty100 == 0) 6092 return -EINVAL; 6093 6094 tmp64 = (u64)duty * 100; 6095 do_div(tmp64, duty100); 6096 *speed = (u32)tmp64; 6097 6098 if (*speed > 100) 6099 *speed = 100; 6100 6101 return 0; 6102} 6103 6104int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6105 u32 speed) 6106{ 6107 struct si_power_info *si_pi = si_get_pi(rdev); 6108 u32 tmp; 6109 u32 duty, duty100; 6110 u64 tmp64; 6111 6112 if (rdev->pm.no_fan) 6113 return -ENOENT; 6114 6115 if (si_pi->fan_is_controlled_by_smc) 6116 return -EINVAL; 6117 6118 if (speed > 100) 6119 return -EINVAL; 6120 6121 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6122 6123 if (duty100 == 0) 6124 return -EINVAL; 6125 6126 tmp64 = (u64)speed * duty100; 6127 do_div(tmp64, 100); 6128 duty = (u32)tmp64; 6129 6130 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6131 tmp |= FDO_STATIC_DUTY(duty); 6132 WREG32(CG_FDO_CTRL0, tmp); 6133 6134 return 0; 6135} 6136 6137void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6138{ 6139 if (mode) { 6140 /* stop auto-manage */ 6141 if (rdev->pm.dpm.fan.ucode_fan_control) 6142 si_fan_ctrl_stop_smc_fan_control(rdev); 6143 si_fan_ctrl_set_static_mode(rdev, mode); 6144 } else { 6145 /* restart auto-manage */ 6146 if (rdev->pm.dpm.fan.ucode_fan_control) 6147 si_thermal_start_smc_fan_control(rdev); 6148 else 6149 si_fan_ctrl_set_default_mode(rdev); 6150 } 6151} 6152 6153u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6154{ 6155 struct si_power_info *si_pi = si_get_pi(rdev); 6156 u32 tmp; 6157 6158 if (si_pi->fan_is_controlled_by_smc) 6159 return 0; 6160 6161 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6162 return (tmp >> FDO_PWM_MODE_SHIFT); 6163} 6164 6165#if 0 6166static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6167 u32 *speed) 6168{ 6169 u32 tach_period; 6170 u32 xclk = radeon_get_xclk(rdev); 6171 6172 if (rdev->pm.no_fan) 6173 return -ENOENT; 6174 6175 if (rdev->pm.fan_pulses_per_revolution == 0) 6176 return -ENOENT; 6177 6178 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6179 if (tach_period == 0) 6180 return -ENOENT; 6181 6182 *speed = 60 * xclk * 10000 / tach_period; 6183 6184 return 0; 6185} 6186 6187static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6188 u32 speed) 6189{ 6190 u32 tach_period, tmp; 6191 u32 xclk = radeon_get_xclk(rdev); 6192 6193 if (rdev->pm.no_fan) 6194 return -ENOENT; 6195 6196 if (rdev->pm.fan_pulses_per_revolution == 0) 6197 return -ENOENT; 6198 6199 if ((speed < rdev->pm.fan_min_rpm) || 6200 (speed > rdev->pm.fan_max_rpm)) 6201 return -EINVAL; 6202 6203 if (rdev->pm.dpm.fan.ucode_fan_control) 6204 si_fan_ctrl_stop_smc_fan_control(rdev); 6205 6206 tach_period = 60 * xclk * 10000 / (8 * speed); 6207 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6208 tmp |= TARGET_PERIOD(tach_period); 6209 WREG32(CG_TACH_CTRL, tmp); 6210 6211 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6212 6213 return 0; 6214} 6215#endif 6216 6217static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6218{ 6219 struct si_power_info *si_pi = si_get_pi(rdev); 6220 u32 tmp; 6221 6222 if (!si_pi->fan_ctrl_is_in_default_mode) { 6223 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6224 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6225 WREG32(CG_FDO_CTRL2, tmp); 6226 6227 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6228 tmp |= TMIN(si_pi->t_min); 6229 WREG32(CG_FDO_CTRL2, tmp); 6230 si_pi->fan_ctrl_is_in_default_mode = true; 6231 } 6232} 6233 6234static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6235{ 6236 if (rdev->pm.dpm.fan.ucode_fan_control) { 6237 si_fan_ctrl_start_smc_fan_control(rdev); 6238 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6239 } 6240} 6241 6242static void si_thermal_initialize(struct radeon_device *rdev) 6243{ 6244 u32 tmp; 6245 6246 if (rdev->pm.fan_pulses_per_revolution) { 6247 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6248 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6249 WREG32(CG_TACH_CTRL, tmp); 6250 } 6251 6252 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6253 tmp |= TACH_PWM_RESP_RATE(0x28); 6254 WREG32(CG_FDO_CTRL2, tmp); 6255} 6256 6257static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6258{ 6259 int ret; 6260 6261 si_thermal_initialize(rdev); 6262 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6263 if (ret) 6264 return ret; 6265 ret = si_thermal_enable_alert(rdev, true); 6266 if (ret) 6267 return ret; 6268 if (rdev->pm.dpm.fan.ucode_fan_control) { 6269 ret = si_halt_smc(rdev); 6270 if (ret) 6271 return ret; 6272 ret = si_thermal_setup_fan_table(rdev); 6273 if (ret) 6274 return ret; 6275 ret = si_resume_smc(rdev); 6276 if (ret) 6277 return ret; 6278 si_thermal_start_smc_fan_control(rdev); 6279 } 6280 6281 return 0; 6282} 6283 6284static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6285{ 6286 if (!rdev->pm.no_fan) { 6287 si_fan_ctrl_set_default_mode(rdev); 6288 si_fan_ctrl_stop_smc_fan_control(rdev); 6289 } 6290} 6291 6292int si_dpm_enable(struct radeon_device *rdev) 6293{ 6294 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6295 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6296 struct si_power_info *si_pi = si_get_pi(rdev); 6297 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6298 int ret; 6299 6300 if (si_is_smc_running(rdev)) 6301 return -EINVAL; 6302 if (pi->voltage_control || si_pi->voltage_control_svi2) 6303 si_enable_voltage_control(rdev, true); 6304 if (pi->mvdd_control) 6305 si_get_mvdd_configuration(rdev); 6306 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6307 ret = si_construct_voltage_tables(rdev); 6308 if (ret) { 6309 DRM_ERROR("si_construct_voltage_tables failed\n"); 6310 return ret; 6311 } 6312 } 6313 if (eg_pi->dynamic_ac_timing) { 6314 ret = si_initialize_mc_reg_table(rdev); 6315 if (ret) 6316 eg_pi->dynamic_ac_timing = false; 6317 } 6318 if (pi->dynamic_ss) 6319 si_enable_spread_spectrum(rdev, true); 6320 if (pi->thermal_protection) 6321 si_enable_thermal_protection(rdev, true); 6322 si_setup_bsp(rdev); 6323 si_program_git(rdev); 6324 si_program_tp(rdev); 6325 si_program_tpp(rdev); 6326 si_program_sstp(rdev); 6327 si_enable_display_gap(rdev); 6328 si_program_vc(rdev); 6329 ret = si_upload_firmware(rdev); 6330 if (ret) { 6331 DRM_ERROR("si_upload_firmware failed\n"); 6332 return ret; 6333 } 6334 ret = si_process_firmware_header(rdev); 6335 if (ret) { 6336 DRM_ERROR("si_process_firmware_header failed\n"); 6337 return ret; 6338 } 6339 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6340 if (ret) { 6341 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6342 return ret; 6343 } 6344 ret = si_init_smc_table(rdev); 6345 if (ret) { 6346 DRM_ERROR("si_init_smc_table failed\n"); 6347 return ret; 6348 } 6349 ret = si_init_smc_spll_table(rdev); 6350 if (ret) { 6351 DRM_ERROR("si_init_smc_spll_table failed\n"); 6352 return ret; 6353 } 6354 ret = si_init_arb_table_index(rdev); 6355 if (ret) { 6356 DRM_ERROR("si_init_arb_table_index failed\n"); 6357 return ret; 6358 } 6359 if (eg_pi->dynamic_ac_timing) { 6360 ret = si_populate_mc_reg_table(rdev, boot_ps); 6361 if (ret) { 6362 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6363 return ret; 6364 } 6365 } 6366 ret = si_initialize_smc_cac_tables(rdev); 6367 if (ret) { 6368 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6369 return ret; 6370 } 6371 ret = si_initialize_hardware_cac_manager(rdev); 6372 if (ret) { 6373 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6374 return ret; 6375 } 6376 ret = si_initialize_smc_dte_tables(rdev); 6377 if (ret) { 6378 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6379 return ret; 6380 } 6381 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6382 if (ret) { 6383 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6384 return ret; 6385 } 6386 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6387 if (ret) { 6388 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6389 return ret; 6390 } 6391 si_program_response_times(rdev); 6392 si_program_ds_registers(rdev); 6393 si_dpm_start_smc(rdev); 6394 ret = si_notify_smc_display_change(rdev, false); 6395 if (ret) { 6396 DRM_ERROR("si_notify_smc_display_change failed\n"); 6397 return ret; 6398 } 6399 si_enable_sclk_control(rdev, true); 6400 si_start_dpm(rdev); 6401 6402 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6403 6404 si_thermal_start_thermal_controller(rdev); 6405 6406 ni_update_current_ps(rdev, boot_ps); 6407 6408 return 0; 6409} 6410 6411static int si_set_temperature_range(struct radeon_device *rdev) 6412{ 6413 int ret; 6414 6415 ret = si_thermal_enable_alert(rdev, false); 6416 if (ret) 6417 return ret; 6418 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6419 if (ret) 6420 return ret; 6421 ret = si_thermal_enable_alert(rdev, true); 6422 if (ret) 6423 return ret; 6424 6425 return ret; 6426} 6427 6428int si_dpm_late_enable(struct radeon_device *rdev) 6429{ 6430 int ret; 6431 6432 ret = si_set_temperature_range(rdev); 6433 if (ret) 6434 return ret; 6435 6436 return ret; 6437} 6438 6439void si_dpm_disable(struct radeon_device *rdev) 6440{ 6441 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6442 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6443 6444 if (!si_is_smc_running(rdev)) 6445 return; 6446 si_thermal_stop_thermal_controller(rdev); 6447 si_disable_ulv(rdev); 6448 si_clear_vc(rdev); 6449 if (pi->thermal_protection) 6450 si_enable_thermal_protection(rdev, false); 6451 si_enable_power_containment(rdev, boot_ps, false); 6452 si_enable_smc_cac(rdev, boot_ps, false); 6453 si_enable_spread_spectrum(rdev, false); 6454 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6455 si_stop_dpm(rdev); 6456 si_reset_to_default(rdev); 6457 si_dpm_stop_smc(rdev); 6458 si_force_switch_to_arb_f0(rdev); 6459 6460 ni_update_current_ps(rdev, boot_ps); 6461} 6462 6463int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6464{ 6465 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6466 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6467 struct radeon_ps *new_ps = &requested_ps; 6468 6469 ni_update_requested_ps(rdev, new_ps); 6470 6471 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6472 6473 return 0; 6474} 6475 6476static int si_power_control_set_level(struct radeon_device *rdev) 6477{ 6478 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6479 int ret; 6480 6481 ret = si_restrict_performance_levels_before_switch(rdev); 6482 if (ret) 6483 return ret; 6484 ret = si_halt_smc(rdev); 6485 if (ret) 6486 return ret; 6487 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6488 if (ret) 6489 return ret; 6490 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6491 if (ret) 6492 return ret; 6493 ret = si_resume_smc(rdev); 6494 if (ret) 6495 return ret; 6496 ret = si_set_sw_state(rdev); 6497 if (ret) 6498 return ret; 6499 return 0; 6500} 6501 6502int si_dpm_set_power_state(struct radeon_device *rdev) 6503{ 6504 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6505 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6506 struct radeon_ps *old_ps = &eg_pi->current_rps; 6507 int ret; 6508 6509 ret = si_disable_ulv(rdev); 6510 if (ret) { 6511 DRM_ERROR("si_disable_ulv failed\n"); 6512 return ret; 6513 } 6514 ret = si_restrict_performance_levels_before_switch(rdev); 6515 if (ret) { 6516 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6517 return ret; 6518 } 6519 if (eg_pi->pcie_performance_request) 6520 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6521 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6522 ret = si_enable_power_containment(rdev, new_ps, false); 6523 if (ret) { 6524 DRM_ERROR("si_enable_power_containment failed\n"); 6525 return ret; 6526 } 6527 ret = si_enable_smc_cac(rdev, new_ps, false); 6528 if (ret) { 6529 DRM_ERROR("si_enable_smc_cac failed\n"); 6530 return ret; 6531 } 6532 ret = si_halt_smc(rdev); 6533 if (ret) { 6534 DRM_ERROR("si_halt_smc failed\n"); 6535 return ret; 6536 } 6537 ret = si_upload_sw_state(rdev, new_ps); 6538 if (ret) { 6539 DRM_ERROR("si_upload_sw_state failed\n"); 6540 return ret; 6541 } 6542 ret = si_upload_smc_data(rdev); 6543 if (ret) { 6544 DRM_ERROR("si_upload_smc_data failed\n"); 6545 return ret; 6546 } 6547 ret = si_upload_ulv_state(rdev); 6548 if (ret) { 6549 DRM_ERROR("si_upload_ulv_state failed\n"); 6550 return ret; 6551 } 6552 if (eg_pi->dynamic_ac_timing) { 6553 ret = si_upload_mc_reg_table(rdev, new_ps); 6554 if (ret) { 6555 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6556 return ret; 6557 } 6558 } 6559 ret = si_program_memory_timing_parameters(rdev, new_ps); 6560 if (ret) { 6561 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6562 return ret; 6563 } 6564 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6565 6566 ret = si_resume_smc(rdev); 6567 if (ret) { 6568 DRM_ERROR("si_resume_smc failed\n"); 6569 return ret; 6570 } 6571 ret = si_set_sw_state(rdev); 6572 if (ret) { 6573 DRM_ERROR("si_set_sw_state failed\n"); 6574 return ret; 6575 } 6576 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6577 si_set_vce_clock(rdev, new_ps, old_ps); 6578 if (eg_pi->pcie_performance_request) 6579 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6580 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6581 if (ret) { 6582 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6583 return ret; 6584 } 6585 ret = si_enable_smc_cac(rdev, new_ps, true); 6586 if (ret) { 6587 DRM_ERROR("si_enable_smc_cac failed\n"); 6588 return ret; 6589 } 6590 ret = si_enable_power_containment(rdev, new_ps, true); 6591 if (ret) { 6592 DRM_ERROR("si_enable_power_containment failed\n"); 6593 return ret; 6594 } 6595 6596 ret = si_power_control_set_level(rdev); 6597 if (ret) { 6598 DRM_ERROR("si_power_control_set_level failed\n"); 6599 return ret; 6600 } 6601 6602 return 0; 6603} 6604 6605void si_dpm_post_set_power_state(struct radeon_device *rdev) 6606{ 6607 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6608 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6609 6610 ni_update_current_ps(rdev, new_ps); 6611} 6612 6613#if 0 6614void si_dpm_reset_asic(struct radeon_device *rdev) 6615{ 6616 si_restrict_performance_levels_before_switch(rdev); 6617 si_disable_ulv(rdev); 6618 si_set_boot_state(rdev); 6619} 6620#endif 6621 6622void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6623{ 6624 si_program_display_gap(rdev); 6625} 6626 6627union power_info { 6628 struct _ATOM_POWERPLAY_INFO info; 6629 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6630 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6631 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6632 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6633 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6634}; 6635 6636union pplib_clock_info { 6637 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6638 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6639 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6640 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6641 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6642}; 6643 6644union pplib_power_state { 6645 struct _ATOM_PPLIB_STATE v1; 6646 struct _ATOM_PPLIB_STATE_V2 v2; 6647}; 6648 6649static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6650 struct radeon_ps *rps, 6651 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6652 u8 table_rev) 6653{ 6654 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6655 rps->class = le16_to_cpu(non_clock_info->usClassification); 6656 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6657 6658 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6659 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6660 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6661 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6662 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6663 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6664 } else { 6665 rps->vclk = 0; 6666 rps->dclk = 0; 6667 } 6668 6669 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6670 rdev->pm.dpm.boot_ps = rps; 6671 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6672 rdev->pm.dpm.uvd_ps = rps; 6673} 6674 6675static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6676 struct radeon_ps *rps, int index, 6677 union pplib_clock_info *clock_info) 6678{ 6679 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6680 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6681 struct si_power_info *si_pi = si_get_pi(rdev); 6682 struct ni_ps *ps = ni_get_ps(rps); 6683 u16 leakage_voltage; 6684 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6685 int ret; 6686 6687 ps->performance_level_count = index + 1; 6688 6689 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6690 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6691 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6692 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6693 6694 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6695 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6696 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6697 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6698 si_pi->sys_pcie_mask, 6699 si_pi->boot_pcie_gen, 6700 clock_info->si.ucPCIEGen); 6701 6702 /* patch up vddc if necessary */ 6703 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6704 &leakage_voltage); 6705 if (ret == 0) 6706 pl->vddc = leakage_voltage; 6707 6708 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6709 pi->acpi_vddc = pl->vddc; 6710 eg_pi->acpi_vddci = pl->vddci; 6711 si_pi->acpi_pcie_gen = pl->pcie_gen; 6712 } 6713 6714 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6715 index == 0) { 6716 /* XXX disable for A0 tahiti */ 6717 si_pi->ulv.supported = false; 6718 si_pi->ulv.pl = *pl; 6719 si_pi->ulv.one_pcie_lane_in_ulv = false; 6720 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6721 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6722 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6723 } 6724 6725 if (pi->min_vddc_in_table > pl->vddc) 6726 pi->min_vddc_in_table = pl->vddc; 6727 6728 if (pi->max_vddc_in_table < pl->vddc) 6729 pi->max_vddc_in_table = pl->vddc; 6730 6731 /* patch up boot state */ 6732 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6733 u16 vddc, vddci, mvdd; 6734 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6735 pl->mclk = rdev->clock.default_mclk; 6736 pl->sclk = rdev->clock.default_sclk; 6737 pl->vddc = vddc; 6738 pl->vddci = vddci; 6739 si_pi->mvdd_bootup_value = mvdd; 6740 } 6741 6742 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6743 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6744 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6745 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6746 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6747 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6748 } 6749} 6750 6751static int si_parse_power_table(struct radeon_device *rdev) 6752{ 6753 struct radeon_mode_info *mode_info = &rdev->mode_info; 6754 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6755 union pplib_power_state *power_state; 6756 int i, j, k, non_clock_array_index, clock_array_index; 6757 union pplib_clock_info *clock_info; 6758 struct _StateArray *state_array; 6759 struct _ClockInfoArray *clock_info_array; 6760 struct _NonClockInfoArray *non_clock_info_array; 6761 union power_info *power_info; 6762 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6763 u16 data_offset; 6764 u8 frev, crev; 6765 u8 *power_state_offset; 6766 struct ni_ps *ps; 6767 6768 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6769 &frev, &crev, &data_offset)) 6770 return -EINVAL; 6771 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6772 6773 state_array = (struct _StateArray *) 6774 (mode_info->atom_context->bios + data_offset + 6775 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6776 clock_info_array = (struct _ClockInfoArray *) 6777 (mode_info->atom_context->bios + data_offset + 6778 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6779 non_clock_info_array = (struct _NonClockInfoArray *) 6780 (mode_info->atom_context->bios + data_offset + 6781 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6782 6783 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 6784 sizeof(struct radeon_ps), 6785 GFP_KERNEL); 6786 if (!rdev->pm.dpm.ps) 6787 return -ENOMEM; 6788 power_state_offset = (u8 *)state_array->states; 6789 for (i = 0; i < state_array->ucNumEntries; i++) { 6790 u8 *idx; 6791 power_state = (union pplib_power_state *)power_state_offset; 6792 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6793 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6794 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6795 if (!rdev->pm.power_state[i].clock_info) 6796 return -EINVAL; 6797 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6798 if (ps == NULL) { 6799 kfree(rdev->pm.dpm.ps); 6800 return -ENOMEM; 6801 } 6802 rdev->pm.dpm.ps[i].ps_priv = ps; 6803 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6804 non_clock_info, 6805 non_clock_info_array->ucEntrySize); 6806 k = 0; 6807 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6808 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6809 clock_array_index = idx[j]; 6810 if (clock_array_index >= clock_info_array->ucNumEntries) 6811 continue; 6812 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6813 break; 6814 clock_info = (union pplib_clock_info *) 6815 ((u8 *)&clock_info_array->clockInfo[0] + 6816 (clock_array_index * clock_info_array->ucEntrySize)); 6817 si_parse_pplib_clock_info(rdev, 6818 &rdev->pm.dpm.ps[i], k, 6819 clock_info); 6820 k++; 6821 } 6822 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6823 } 6824 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6825 6826 /* fill in the vce power states */ 6827 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6828 u32 sclk, mclk; 6829 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6830 clock_info = (union pplib_clock_info *) 6831 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6832 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6833 sclk |= clock_info->si.ucEngineClockHigh << 16; 6834 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6835 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6836 rdev->pm.dpm.vce_states[i].sclk = sclk; 6837 rdev->pm.dpm.vce_states[i].mclk = mclk; 6838 } 6839 6840 return 0; 6841} 6842 6843int si_dpm_init(struct radeon_device *rdev) 6844{ 6845 struct rv7xx_power_info *pi; 6846 struct evergreen_power_info *eg_pi; 6847 struct ni_power_info *ni_pi; 6848 struct si_power_info *si_pi; 6849 struct atom_clock_dividers dividers; 6850 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 6851 struct pci_dev *root = rdev->pdev->bus->self; 6852 int ret; 6853 6854 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6855 if (si_pi == NULL) 6856 return -ENOMEM; 6857 rdev->pm.dpm.priv = si_pi; 6858 ni_pi = &si_pi->ni; 6859 eg_pi = &ni_pi->eg; 6860 pi = &eg_pi->rv7xx; 6861 6862 if (!pci_is_root_bus(rdev->pdev->bus)) 6863 speed_cap = pcie_get_speed_cap(root); 6864 if (speed_cap == PCI_SPEED_UNKNOWN) { 6865 si_pi->sys_pcie_mask = 0; 6866 } else { 6867 if (speed_cap == PCIE_SPEED_8_0GT) 6868 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6869 RADEON_PCIE_SPEED_50 | 6870 RADEON_PCIE_SPEED_80; 6871 else if (speed_cap == PCIE_SPEED_5_0GT) 6872 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6873 RADEON_PCIE_SPEED_50; 6874 else 6875 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 6876 } 6877 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6878 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6879 6880 si_set_max_cu_value(rdev); 6881 6882 rv770_get_max_vddc(rdev); 6883 si_get_leakage_vddc(rdev); 6884 si_patch_dependency_tables_based_on_leakage(rdev); 6885 6886 pi->acpi_vddc = 0; 6887 eg_pi->acpi_vddci = 0; 6888 pi->min_vddc_in_table = 0; 6889 pi->max_vddc_in_table = 0; 6890 6891 ret = r600_get_platform_caps(rdev); 6892 if (ret) 6893 return ret; 6894 6895 ret = r600_parse_extended_power_table(rdev); 6896 if (ret) 6897 return ret; 6898 6899 ret = si_parse_power_table(rdev); 6900 if (ret) 6901 return ret; 6902 6903 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6904 kcalloc(4, 6905 sizeof(struct radeon_clock_voltage_dependency_entry), 6906 GFP_KERNEL); 6907 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6908 r600_free_extended_power_table(rdev); 6909 return -ENOMEM; 6910 } 6911 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6912 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6913 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6914 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6915 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6916 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6917 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6918 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6919 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6920 6921 if (rdev->pm.dpm.voltage_response_time == 0) 6922 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6923 if (rdev->pm.dpm.backbias_response_time == 0) 6924 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6925 6926 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6927 0, false, ÷rs); 6928 if (ret) 6929 pi->ref_div = dividers.ref_div + 1; 6930 else 6931 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6932 6933 eg_pi->smu_uvd_hs = false; 6934 6935 pi->mclk_strobe_mode_threshold = 40000; 6936 if (si_is_special_1gb_platform(rdev)) 6937 pi->mclk_stutter_mode_threshold = 0; 6938 else 6939 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6940 pi->mclk_edc_enable_threshold = 40000; 6941 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6942 6943 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6944 6945 pi->voltage_control = 6946 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6947 VOLTAGE_OBJ_GPIO_LUT); 6948 if (!pi->voltage_control) { 6949 si_pi->voltage_control_svi2 = 6950 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6951 VOLTAGE_OBJ_SVID2); 6952 if (si_pi->voltage_control_svi2) 6953 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6954 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6955 } 6956 6957 pi->mvdd_control = 6958 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6959 VOLTAGE_OBJ_GPIO_LUT); 6960 6961 eg_pi->vddci_control = 6962 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6963 VOLTAGE_OBJ_GPIO_LUT); 6964 if (!eg_pi->vddci_control) 6965 si_pi->vddci_control_svi2 = 6966 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6967 VOLTAGE_OBJ_SVID2); 6968 6969 si_pi->vddc_phase_shed_control = 6970 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6971 VOLTAGE_OBJ_PHASE_LUT); 6972 6973 rv770_get_engine_memory_ss(rdev); 6974 6975 pi->asi = RV770_ASI_DFLT; 6976 pi->pasi = CYPRESS_HASI_DFLT; 6977 pi->vrc = SISLANDS_VRC_DFLT; 6978 6979 pi->gfx_clock_gating = true; 6980 6981 eg_pi->sclk_deep_sleep = true; 6982 si_pi->sclk_deep_sleep_above_low = false; 6983 6984 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6985 pi->thermal_protection = true; 6986 else 6987 pi->thermal_protection = false; 6988 6989 eg_pi->dynamic_ac_timing = true; 6990 6991 eg_pi->light_sleep = true; 6992#if defined(CONFIG_ACPI) 6993 eg_pi->pcie_performance_request = 6994 radeon_acpi_is_pcie_performance_request_supported(rdev); 6995#else 6996 eg_pi->pcie_performance_request = false; 6997#endif 6998 6999 si_pi->sram_end = SMC_RAM_END; 7000 7001 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7002 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7003 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7004 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7005 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7006 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7007 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7008 7009 si_initialize_powertune_defaults(rdev); 7010 7011 /* make sure dc limits are valid */ 7012 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7013 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7014 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7015 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7016 7017 si_pi->fan_ctrl_is_in_default_mode = true; 7018 7019 return 0; 7020} 7021 7022void si_dpm_fini(struct radeon_device *rdev) 7023{ 7024 int i; 7025 7026 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7027 kfree(rdev->pm.dpm.ps[i].ps_priv); 7028 } 7029 kfree(rdev->pm.dpm.ps); 7030 kfree(rdev->pm.dpm.priv); 7031 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7032 r600_free_extended_power_table(rdev); 7033} 7034 7035void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7036 struct seq_file *m) 7037{ 7038 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7039 struct radeon_ps *rps = &eg_pi->current_rps; 7040 struct ni_ps *ps = ni_get_ps(rps); 7041 struct rv7xx_pl *pl; 7042 u32 current_index = 7043 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7044 CURRENT_STATE_INDEX_SHIFT; 7045 7046 if (current_index >= ps->performance_level_count) { 7047 seq_printf(m, "invalid dpm profile %d\n", current_index); 7048 } else { 7049 pl = &ps->performance_levels[current_index]; 7050 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7051 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7052 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7053 } 7054} 7055 7056u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7057{ 7058 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7059 struct radeon_ps *rps = &eg_pi->current_rps; 7060 struct ni_ps *ps = ni_get_ps(rps); 7061 struct rv7xx_pl *pl; 7062 u32 current_index = 7063 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7064 CURRENT_STATE_INDEX_SHIFT; 7065 7066 if (current_index >= ps->performance_level_count) { 7067 return 0; 7068 } else { 7069 pl = &ps->performance_levels[current_index]; 7070 return pl->sclk; 7071 } 7072} 7073 7074u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7075{ 7076 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7077 struct radeon_ps *rps = &eg_pi->current_rps; 7078 struct ni_ps *ps = ni_get_ps(rps); 7079 struct rv7xx_pl *pl; 7080 u32 current_index = 7081 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7082 CURRENT_STATE_INDEX_SHIFT; 7083 7084 if (current_index >= ps->performance_level_count) { 7085 return 0; 7086 } else { 7087 pl = &ps->performance_levels[current_index]; 7088 return pl->mclk; 7089 } 7090}
~/
Read-only file preview.