radeon_fence.c

   1/*
   2 * Copyright 2009 Jerome Glisse.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sub license, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * The above copyright notice and this permission notice (including the
  22 * next paragraph) shall be included in all copies or substantial portions
  23 * of the Software.
  24 *
  25 */
  26/*
  27 * Authors:
  28 *    Jerome Glisse <glisse@freedesktop.org>
  29 *    Dave Airlie
  30 */
  31
  32#include <linux/atomic.h>
  33#include <linux/debugfs.h>
  34#include <linux/firmware.h>
  35#include <linux/kref.h>
  36#include <linux/sched/signal.h>
  37#include <linux/seq_file.h>
  38#include <linux/slab.h>
  39#include <linux/wait.h>
  40
  41#include <drm/drm_device.h>
  42#include <drm/drm_file.h>
  43
  44#include "radeon.h"
  45#include "radeon_reg.h"
  46#include "radeon_trace.h"
  47
  48/*
  49 * Fences mark an event in the GPUs pipeline and are used
  50 * for GPU/CPU synchronization.  When the fence is written,
  51 * it is expected that all buffers associated with that fence
  52 * are no longer in use by the associated ring on the GPU and
  53 * that the relevant GPU caches have been flushed.  Whether
  54 * we use a scratch register or memory location depends on the asic
  55 * and whether writeback is enabled.
  56 */
  57
  58/**
  59 * radeon_fence_write - write a fence value
  60 *
  61 * @rdev: radeon_device pointer
  62 * @seq: sequence number to write
  63 * @ring: ring index the fence is associated with
  64 *
  65 * Writes a fence value to memory or a scratch register (all asics).
  66 */
  67static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  68{
  69	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  70
  71	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  72		if (drv->cpu_addr)
  73			*drv->cpu_addr = cpu_to_le32(seq);
  74	} else {
  75		WREG32(drv->scratch_reg, seq);
  76	}
  77}
  78
  79/**
  80 * radeon_fence_read - read a fence value
  81 *
  82 * @rdev: radeon_device pointer
  83 * @ring: ring index the fence is associated with
  84 *
  85 * Reads a fence value from memory or a scratch register (all asics).
  86 * Returns the value of the fence read from memory or register.
  87 */
  88static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  89{
  90	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  91	u32 seq = 0;
  92
  93	if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  94		if (drv->cpu_addr)
  95			seq = le32_to_cpu(*drv->cpu_addr);
  96		else
  97			seq = lower_32_bits(atomic64_read(&drv->last_seq));
  98	} else {
  99		seq = RREG32(drv->scratch_reg);
 100	}
 101	return seq;
 102}
 103
 104/**
 105 * radeon_fence_schedule_check - schedule lockup check
 106 *
 107 * @rdev: radeon_device pointer
 108 * @ring: ring index we should work with
 109 *
 110 * Queues a delayed work item to check for lockups.
 111 */
 112static void radeon_fence_schedule_check(struct radeon_device *rdev, int ring)
 113{
 114	/*
 115	 * Do not reset the timer here with mod_delayed_work,
 116	 * this can livelock in an interaction with TTM delayed destroy.
 117	 */
 118	queue_delayed_work(system_power_efficient_wq,
 119			   &rdev->fence_drv[ring].lockup_work,
 120			   RADEON_FENCE_JIFFIES_TIMEOUT);
 121}
 122
 123/**
 124 * radeon_fence_emit - emit a fence on the requested ring
 125 *
 126 * @rdev: radeon_device pointer
 127 * @fence: radeon fence object
 128 * @ring: ring index the fence is associated with
 129 *
 130 * Emits a fence command on the requested ring (all asics).
 131 * Returns 0 on success, -ENOMEM on failure.
 132 */
 133int radeon_fence_emit(struct radeon_device *rdev,
 134		      struct radeon_fence **fence,
 135		      int ring)
 136{
 137	u64 seq;
 138
 139	/* we are protected by the ring emission mutex */
 140	*fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
 141	if ((*fence) == NULL)
 142		return -ENOMEM;
 143
 144	(*fence)->rdev = rdev;
 145	(*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
 146	(*fence)->ring = ring;
 147	(*fence)->is_vm_update = false;
 148	dma_fence_init(&(*fence)->base, &radeon_fence_ops,
 149		       &rdev->fence_queue.lock,
 150		       rdev->fence_context + ring,
 151		       seq);
 152	radeon_fence_ring_emit(rdev, ring, *fence);
 153	trace_radeon_fence_emit(rdev_to_drm(rdev), ring, (*fence)->seq);
 154	radeon_fence_schedule_check(rdev, ring);
 155	return 0;
 156}
 157
 158/*
 159 * radeon_fence_check_signaled - callback from fence_queue
 160 *
 161 * this function is called with fence_queue lock held, which is also used
 162 * for the fence locking itself, so unlocked variants are used for
 163 * fence_signal, and remove_wait_queue.
 164 */
 165static int radeon_fence_check_signaled(wait_queue_entry_t *wait,
 166				       unsigned int mode, int flags, void *key)
 167{
 168	struct radeon_fence *fence;
 169	u64 seq;
 170
 171	fence = container_of(wait, struct radeon_fence, fence_wake);
 172
 173	/*
 174	 * We cannot use radeon_fence_process here because we're already
 175	 * in the waitqueue, in a call from wake_up_all.
 176	 */
 177	seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
 178	if (seq >= fence->seq) {
 179		dma_fence_signal_locked(&fence->base);
 180		radeon_irq_kms_sw_irq_put(fence->rdev, fence->ring);
 181		__remove_wait_queue(&fence->rdev->fence_queue, &fence->fence_wake);
 182		dma_fence_put(&fence->base);
 183	}
 184	return 0;
 185}
 186
 187/**
 188 * radeon_fence_activity - check for fence activity
 189 *
 190 * @rdev: radeon_device pointer
 191 * @ring: ring index the fence is associated with
 192 *
 193 * Checks the current fence value and calculates the last
 194 * signalled fence value. Returns true if activity occured
 195 * on the ring, and the fence_queue should be waken up.
 196 */
 197static bool radeon_fence_activity(struct radeon_device *rdev, int ring)
 198{
 199	uint64_t seq, last_seq, last_emitted;
 200	unsigned int count_loop = 0;
 201	bool wake = false;
 202
 203	/* Note there is a scenario here for an infinite loop but it's
 204	 * very unlikely to happen. For it to happen, the current polling
 205	 * process need to be interrupted by another process and another
 206	 * process needs to update the last_seq btw the atomic read and
 207	 * xchg of the current process.
 208	 *
 209	 * More over for this to go in infinite loop there need to be
 210	 * continuously new fence signaled ie radeon_fence_read needs
 211	 * to return a different value each time for both the currently
 212	 * polling process and the other process that xchg the last_seq
 213	 * btw atomic read and xchg of the current process. And the
 214	 * value the other process set as last seq must be higher than
 215	 * the seq value we just read. Which means that current process
 216	 * need to be interrupted after radeon_fence_read and before
 217	 * atomic xchg.
 218	 *
 219	 * To be even more safe we count the number of time we loop and
 220	 * we bail after 10 loop just accepting the fact that we might
 221	 * have temporarly set the last_seq not to the true real last
 222	 * seq but to an older one.
 223	 */
 224	last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
 225	do {
 226		last_emitted = rdev->fence_drv[ring].sync_seq[ring];
 227		seq = radeon_fence_read(rdev, ring);
 228		seq |= last_seq & 0xffffffff00000000LL;
 229		if (seq < last_seq) {
 230			seq &= 0xffffffff;
 231			seq |= last_emitted & 0xffffffff00000000LL;
 232		}
 233
 234		if (seq <= last_seq || seq > last_emitted)
 235			break;
 236
 237		/* If we loop over we don't want to return without
 238		 * checking if a fence is signaled as it means that the
 239		 * seq we just read is different from the previous on.
 240		 */
 241		wake = true;
 242		last_seq = seq;
 243		if ((count_loop++) > 10) {
 244			/* We looped over too many time leave with the
 245			 * fact that we might have set an older fence
 246			 * seq then the current real last seq as signaled
 247			 * by the hw.
 248			 */
 249			break;
 250		}
 251	} while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
 252
 253	if (seq < last_emitted)
 254		radeon_fence_schedule_check(rdev, ring);
 255
 256	return wake;
 257}
 258
 259/**
 260 * radeon_fence_check_lockup - check for hardware lockup
 261 *
 262 * @work: delayed work item
 263 *
 264 * Checks for fence activity and if there is none probe
 265 * the hardware if a lockup occured.
 266 */
 267static void radeon_fence_check_lockup(struct work_struct *work)
 268{
 269	struct radeon_fence_driver *fence_drv;
 270	struct radeon_device *rdev;
 271	int ring;
 272
 273	fence_drv = container_of(work, struct radeon_fence_driver,
 274				 lockup_work.work);
 275	rdev = fence_drv->rdev;
 276	ring = fence_drv - &rdev->fence_drv[0];
 277
 278	if (!down_read_trylock(&rdev->exclusive_lock)) {
 279		/* just reschedule the check if a reset is going on */
 280		radeon_fence_schedule_check(rdev, ring);
 281		return;
 282	}
 283
 284	if (fence_drv->delayed_irq && rdev->irq.installed) {
 285		unsigned long irqflags;
 286
 287		fence_drv->delayed_irq = false;
 288		spin_lock_irqsave(&rdev->irq.lock, irqflags);
 289		radeon_irq_set(rdev);
 290		spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 291	}
 292
 293	if (radeon_fence_activity(rdev, ring))
 294		wake_up_all(&rdev->fence_queue);
 295
 296	else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
 297
 298		/* good news we believe it's a lockup */
 299		dev_warn(rdev->dev, "GPU lockup (current fence id 0x%016llx last fence id 0x%016llx on ring %d)\n",
 300			 (uint64_t)atomic64_read(&fence_drv->last_seq),
 301			 fence_drv->sync_seq[ring], ring);
 302
 303		/* remember that we need an reset */
 304		rdev->needs_reset = true;
 305		wake_up_all(&rdev->fence_queue);
 306	}
 307	up_read(&rdev->exclusive_lock);
 308}
 309
 310/**
 311 * radeon_fence_process - process a fence
 312 *
 313 * @rdev: radeon_device pointer
 314 * @ring: ring index the fence is associated with
 315 *
 316 * Checks the current fence value and wakes the fence queue
 317 * if the sequence number has increased (all asics).
 318 */
 319void radeon_fence_process(struct radeon_device *rdev, int ring)
 320{
 321	if (radeon_fence_activity(rdev, ring))
 322		wake_up_all(&rdev->fence_queue);
 323}
 324
 325/**
 326 * radeon_fence_seq_signaled - check if a fence sequence number has signaled
 327 *
 328 * @rdev: radeon device pointer
 329 * @seq: sequence number
 330 * @ring: ring index the fence is associated with
 331 *
 332 * Check if the last signaled fence sequnce number is >= the requested
 333 * sequence number (all asics).
 334 * Returns true if the fence has signaled (current fence value
 335 * is >= requested value) or false if it has not (current fence
 336 * value is < the requested value.  Helper function for
 337 * radeon_fence_signaled().
 338 */
 339static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
 340				      u64 seq, unsigned int ring)
 341{
 342	if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
 343		return true;
 344
 345	/* poll new last sequence at least once */
 346	radeon_fence_process(rdev, ring);
 347	if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
 348		return true;
 349
 350	return false;
 351}
 352
 353static bool radeon_fence_is_signaled(struct dma_fence *f)
 354{
 355	struct radeon_fence *fence = to_radeon_fence(f);
 356	struct radeon_device *rdev = fence->rdev;
 357	unsigned int ring = fence->ring;
 358	u64 seq = fence->seq;
 359
 360	if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
 361		return true;
 362
 363	return false;
 364}
 365
 366/**
 367 * radeon_fence_enable_signaling - enable signalling on fence
 368 * @f: fence
 369 *
 370 * This function is called with fence_queue lock held, and adds a callback
 371 * to fence_queue that checks if this fence is signaled, and if so it
 372 * signals the fence and removes itself.
 373 */
 374static bool radeon_fence_enable_signaling(struct dma_fence *f)
 375{
 376	struct radeon_fence *fence = to_radeon_fence(f);
 377	struct radeon_device *rdev = fence->rdev;
 378
 379	if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
 380		return false;
 381
 382	if (down_read_trylock(&rdev->exclusive_lock)) {
 383		radeon_irq_kms_sw_irq_get(rdev, fence->ring);
 384
 385		if (radeon_fence_activity(rdev, fence->ring))
 386			wake_up_all_locked(&rdev->fence_queue);
 387
 388		/* did fence get signaled after we enabled the sw irq? */
 389		if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
 390			radeon_irq_kms_sw_irq_put(rdev, fence->ring);
 391			up_read(&rdev->exclusive_lock);
 392			return false;
 393		}
 394
 395		up_read(&rdev->exclusive_lock);
 396	} else {
 397		/* we're probably in a lockup, lets not fiddle too much */
 398		if (radeon_irq_kms_sw_irq_get_delayed(rdev, fence->ring))
 399			rdev->fence_drv[fence->ring].delayed_irq = true;
 400		radeon_fence_schedule_check(rdev, fence->ring);
 401	}
 402
 403	fence->fence_wake.flags = 0;
 404	fence->fence_wake.private = NULL;
 405	fence->fence_wake.func = radeon_fence_check_signaled;
 406	__add_wait_queue(&rdev->fence_queue, &fence->fence_wake);
 407	dma_fence_get(f);
 408	return true;
 409}
 410
 411/**
 412 * radeon_fence_signaled - check if a fence has signaled
 413 *
 414 * @fence: radeon fence object
 415 *
 416 * Check if the requested fence has signaled (all asics).
 417 * Returns true if the fence has signaled or false if it has not.
 418 */
 419bool radeon_fence_signaled(struct radeon_fence *fence)
 420{
 421	if (!fence)
 422		return true;
 423
 424	if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
 425		dma_fence_signal(&fence->base);
 426		return true;
 427	}
 428	return false;
 429}
 430
 431/**
 432 * radeon_fence_any_seq_signaled - check if any sequence number is signaled
 433 *
 434 * @rdev: radeon device pointer
 435 * @seq: sequence numbers
 436 *
 437 * Check if the last signaled fence sequnce number is >= the requested
 438 * sequence number (all asics).
 439 * Returns true if any has signaled (current value is >= requested value)
 440 * or false if it has not. Helper function for radeon_fence_wait_seq.
 441 */
 442static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
 443{
 444	unsigned int i;
 445
 446	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 447		if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
 448			return true;
 449	}
 450	return false;
 451}
 452
 453/**
 454 * radeon_fence_wait_seq_timeout - wait for a specific sequence numbers
 455 *
 456 * @rdev: radeon device pointer
 457 * @target_seq: sequence number(s) we want to wait for
 458 * @intr: use interruptable sleep
 459 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
 460 *
 461 * Wait for the requested sequence number(s) to be written by any ring
 462 * (all asics).  Sequnce number array is indexed by ring id.
 463 * @intr selects whether to use interruptable (true) or non-interruptable
 464 * (false) sleep when waiting for the sequence number.  Helper function
 465 * for radeon_fence_wait_*().
 466 * Returns remaining time if the sequence number has passed, 0 when
 467 * the wait timeout, or an error for all other cases.
 468 * -EDEADLK is returned when a GPU lockup has been detected.
 469 */
 470static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
 471					  u64 *target_seq, bool intr,
 472					  long timeout)
 473{
 474	long r;
 475	int i;
 476
 477	if (radeon_fence_any_seq_signaled(rdev, target_seq))
 478		return timeout;
 479
 480	/* enable IRQs and tracing */
 481	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 482		if (!target_seq[i])
 483			continue;
 484
 485		trace_radeon_fence_wait_begin(rdev_to_drm(rdev), i, target_seq[i]);
 486		radeon_irq_kms_sw_irq_get(rdev, i);
 487	}
 488
 489	if (intr) {
 490		r = wait_event_interruptible_timeout(rdev->fence_queue, (
 491			radeon_fence_any_seq_signaled(rdev, target_seq)
 492			 || rdev->needs_reset), timeout);
 493	} else {
 494		r = wait_event_timeout(rdev->fence_queue, (
 495			radeon_fence_any_seq_signaled(rdev, target_seq)
 496			 || rdev->needs_reset), timeout);
 497	}
 498
 499	if (rdev->needs_reset)
 500		r = -EDEADLK;
 501
 502	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 503		if (!target_seq[i])
 504			continue;
 505
 506		radeon_irq_kms_sw_irq_put(rdev, i);
 507		trace_radeon_fence_wait_end(rdev_to_drm(rdev), i, target_seq[i]);
 508	}
 509
 510	return r;
 511}
 512
 513/**
 514 * radeon_fence_wait_timeout - wait for a fence to signal with timeout
 515 *
 516 * @fence: radeon fence object
 517 * @intr: use interruptible sleep
 518 *
 519 * Wait for the requested fence to signal (all asics).
 520 * @intr selects whether to use interruptable (true) or non-interruptable
 521 * (false) sleep when waiting for the fence.
 522 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
 523 * Returns remaining time if the sequence number has passed, 0 when
 524 * the wait timeout, or an error for all other cases.
 525 */
 526long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
 527{
 528	uint64_t seq[RADEON_NUM_RINGS] = {};
 529	long r;
 530
 531	/*
 532	 * This function should not be called on !radeon fences.
 533	 * If this is the case, it would mean this function can
 534	 * also be called on radeon fences belonging to another card.
 535	 * exclusive_lock is not held in that case.
 536	 */
 537	if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
 538		return dma_fence_wait(&fence->base, intr);
 539
 540	seq[fence->ring] = fence->seq;
 541	r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
 542	if (r <= 0)
 543		return r;
 544
 545	dma_fence_signal(&fence->base);
 546	return r;
 547}
 548
 549/**
 550 * radeon_fence_wait - wait for a fence to signal
 551 *
 552 * @fence: radeon fence object
 553 * @intr: use interruptible sleep
 554 *
 555 * Wait for the requested fence to signal (all asics).
 556 * @intr selects whether to use interruptable (true) or non-interruptable
 557 * (false) sleep when waiting for the fence.
 558 * Returns 0 if the fence has passed, error for all other cases.
 559 */
 560int radeon_fence_wait(struct radeon_fence *fence, bool intr)
 561{
 562	long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
 563
 564	if (r > 0)
 565		return 0;
 566	else
 567		return r;
 568}
 569
 570/**
 571 * radeon_fence_wait_next - wait for the next fence to signal
 572 *
 573 * @rdev: radeon device pointer
 574 * @ring: ring index the fence is associated with
 575 *
 576 * Wait for the next fence on the requested ring to signal (all asics).
 577 * Returns 0 if the next fence has passed, error for all other cases.
 578 * Caller must hold ring lock.
 579 */
 580int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
 581{
 582	uint64_t seq[RADEON_NUM_RINGS] = {};
 583	long r;
 584
 585	seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
 586	if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
 587		/* nothing to wait for, last_seq is already
 588		 * the last emited fence
 589		 */
 590		return -ENOENT;
 591	}
 592
 593	r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
 594	if (r < 0)
 595		return r;
 596
 597	return 0;
 598}
 599
 600/**
 601 * radeon_fence_wait_empty - wait for all fences to signal
 602 *
 603 * @rdev: radeon device pointer
 604 * @ring: ring index the fence is associated with
 605 *
 606 * Wait for all fences on the requested ring to signal (all asics).
 607 * Returns 0 if the fences have passed, error for all other cases.
 608 * Caller must hold ring lock.
 609 */
 610int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)
 611{
 612	uint64_t seq[RADEON_NUM_RINGS] = {};
 613	long r;
 614
 615	seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
 616	if (!seq[ring])
 617		return 0;
 618
 619	r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
 620	if (r < 0) {
 621		if (r == -EDEADLK)
 622			return -EDEADLK;
 623
 624		dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
 625			ring, r);
 626	}
 627	return 0;
 628}
 629
 630/**
 631 * radeon_fence_ref - take a ref on a fence
 632 *
 633 * @fence: radeon fence object
 634 *
 635 * Take a reference on a fence (all asics).
 636 * Returns the fence.
 637 */
 638struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
 639{
 640	dma_fence_get(&fence->base);
 641	return fence;
 642}
 643
 644/**
 645 * radeon_fence_unref - remove a ref on a fence
 646 *
 647 * @fence: radeon fence object
 648 *
 649 * Remove a reference on a fence (all asics).
 650 */
 651void radeon_fence_unref(struct radeon_fence **fence)
 652{
 653	struct radeon_fence *tmp = *fence;
 654
 655	*fence = NULL;
 656	if (tmp)
 657		dma_fence_put(&tmp->base);
 658}
 659
 660/**
 661 * radeon_fence_count_emitted - get the count of emitted fences
 662 *
 663 * @rdev: radeon device pointer
 664 * @ring: ring index the fence is associated with
 665 *
 666 * Get the number of fences emitted on the requested ring (all asics).
 667 * Returns the number of emitted fences on the ring.  Used by the
 668 * dynpm code to ring track activity.
 669 */
 670unsigned int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
 671{
 672	uint64_t emitted;
 673
 674	/* We are not protected by ring lock when reading the last sequence
 675	 * but it's ok to report slightly wrong fence count here.
 676	 */
 677	radeon_fence_process(rdev, ring);
 678	emitted = rdev->fence_drv[ring].sync_seq[ring]
 679		- atomic64_read(&rdev->fence_drv[ring].last_seq);
 680	/* to avoid 32bits warp around */
 681	if (emitted > 0x10000000)
 682		emitted = 0x10000000;
 683
 684	return (unsigned int)emitted;
 685}
 686
 687/**
 688 * radeon_fence_need_sync - do we need a semaphore
 689 *
 690 * @fence: radeon fence object
 691 * @dst_ring: which ring to check against
 692 *
 693 * Check if the fence needs to be synced against another ring
 694 * (all asics).  If so, we need to emit a semaphore.
 695 * Returns true if we need to sync with another ring, false if
 696 * not.
 697 */
 698bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
 699{
 700	struct radeon_fence_driver *fdrv;
 701
 702	if (!fence)
 703		return false;
 704
 705	if (fence->ring == dst_ring)
 706		return false;
 707
 708	/* we are protected by the ring mutex */
 709	fdrv = &fence->rdev->fence_drv[dst_ring];
 710	if (fence->seq <= fdrv->sync_seq[fence->ring])
 711		return false;
 712
 713	return true;
 714}
 715
 716/**
 717 * radeon_fence_note_sync - record the sync point
 718 *
 719 * @fence: radeon fence object
 720 * @dst_ring: which ring to check against
 721 *
 722 * Note the sequence number at which point the fence will
 723 * be synced with the requested ring (all asics).
 724 */
 725void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
 726{
 727	struct radeon_fence_driver *dst, *src;
 728	unsigned int i;
 729
 730	if (!fence)
 731		return;
 732
 733	if (fence->ring == dst_ring)
 734		return;
 735
 736	/* we are protected by the ring mutex */
 737	src = &fence->rdev->fence_drv[fence->ring];
 738	dst = &fence->rdev->fence_drv[dst_ring];
 739	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 740		if (i == dst_ring)
 741			continue;
 742
 743		dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
 744	}
 745}
 746
 747/**
 748 * radeon_fence_driver_start_ring - make the fence driver
 749 * ready for use on the requested ring.
 750 *
 751 * @rdev: radeon device pointer
 752 * @ring: ring index to start the fence driver on
 753 *
 754 * Make the fence driver ready for processing (all asics).
 755 * Not all asics have all rings, so each asic will only
 756 * start the fence driver on the rings it has.
 757 * Returns 0 for success, errors for failure.
 758 */
 759int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
 760{
 761	uint64_t index;
 762	int r;
 763
 764	radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 765	if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
 766		rdev->fence_drv[ring].scratch_reg = 0;
 767		if (ring != R600_RING_TYPE_UVD_INDEX) {
 768			index = R600_WB_EVENT_OFFSET + ring * 4;
 769			rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
 770			rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
 771							 index;
 772
 773		} else {
 774			/* put fence directly behind firmware */
 775			index = ALIGN(rdev->uvd_fw->size, 8);
 776			rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
 777			rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
 778		}
 779
 780	} else {
 781		r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
 782		if (r) {
 783			dev_err(rdev->dev, "fence failed to get scratch register\n");
 784			return r;
 785		}
 786		index = RADEON_WB_SCRATCH_OFFSET +
 787			rdev->fence_drv[ring].scratch_reg -
 788			rdev->scratch.reg_base;
 789		rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
 790		rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
 791	}
 792	radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
 793	rdev->fence_drv[ring].initialized = true;
 794	dev_info(rdev->dev, "fence driver on ring %d uses gpu addr 0x%016llx\n",
 795		 ring, rdev->fence_drv[ring].gpu_addr);
 796	return 0;
 797}
 798
 799/**
 800 * radeon_fence_driver_init_ring - init the fence driver
 801 * for the requested ring.
 802 *
 803 * @rdev: radeon device pointer
 804 * @ring: ring index to start the fence driver on
 805 *
 806 * Init the fence driver for the requested ring (all asics).
 807 * Helper function for radeon_fence_driver_init().
 808 */
 809static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
 810{
 811	int i;
 812
 813	rdev->fence_drv[ring].scratch_reg = -1;
 814	rdev->fence_drv[ring].cpu_addr = NULL;
 815	rdev->fence_drv[ring].gpu_addr = 0;
 816	for (i = 0; i < RADEON_NUM_RINGS; ++i)
 817		rdev->fence_drv[ring].sync_seq[i] = 0;
 818	atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
 819	rdev->fence_drv[ring].initialized = false;
 820	INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,
 821			  radeon_fence_check_lockup);
 822	rdev->fence_drv[ring].rdev = rdev;
 823}
 824
 825/**
 826 * radeon_fence_driver_init - init the fence driver
 827 * for all possible rings.
 828 *
 829 * @rdev: radeon device pointer
 830 *
 831 * Init the fence driver for all possible rings (all asics).
 832 * Not all asics have all rings, so each asic will only
 833 * start the fence driver on the rings it has using
 834 * radeon_fence_driver_start_ring().
 835 */
 836void radeon_fence_driver_init(struct radeon_device *rdev)
 837{
 838	int ring;
 839
 840	init_waitqueue_head(&rdev->fence_queue);
 841	for (ring = 0; ring < RADEON_NUM_RINGS; ring++)
 842		radeon_fence_driver_init_ring(rdev, ring);
 843
 844	radeon_debugfs_fence_init(rdev);
 845}
 846
 847/**
 848 * radeon_fence_driver_fini - tear down the fence driver
 849 * for all possible rings.
 850 *
 851 * @rdev: radeon device pointer
 852 *
 853 * Tear down the fence driver for all possible rings (all asics).
 854 */
 855void radeon_fence_driver_fini(struct radeon_device *rdev)
 856{
 857	int ring, r;
 858
 859	mutex_lock(&rdev->ring_lock);
 860	for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 861		if (!rdev->fence_drv[ring].initialized)
 862			continue;
 863		r = radeon_fence_wait_empty(rdev, ring);
 864		if (r) {
 865			/* no need to trigger GPU reset as we are unloading */
 866			radeon_fence_driver_force_completion(rdev, ring);
 867		}
 868		cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
 869		wake_up_all(&rdev->fence_queue);
 870		radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 871		rdev->fence_drv[ring].initialized = false;
 872	}
 873	mutex_unlock(&rdev->ring_lock);
 874}
 875
 876/**
 877 * radeon_fence_driver_force_completion - force all fence waiter to complete
 878 *
 879 * @rdev: radeon device pointer
 880 * @ring: the ring to complete
 881 *
 882 * In case of GPU reset failure make sure no process keep waiting on fence
 883 * that will never complete.
 884 */
 885void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring)
 886{
 887	if (rdev->fence_drv[ring].initialized) {
 888		radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
 889		cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
 890	}
 891}
 892
 893
 894/*
 895 * Fence debugfs
 896 */
 897#if defined(CONFIG_DEBUG_FS)
 898static int radeon_debugfs_fence_info_show(struct seq_file *m, void *data)
 899{
 900	struct radeon_device *rdev = m->private;
 901	int i, j;
 902
 903	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 904		if (!rdev->fence_drv[i].initialized)
 905			continue;
 906
 907		radeon_fence_process(rdev, i);
 908
 909		seq_printf(m, "--- ring %d ---\n", i);
 910		seq_printf(m, "Last signaled fence 0x%016llx\n",
 911			   (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
 912		seq_printf(m, "Last emitted        0x%016llx\n",
 913			   rdev->fence_drv[i].sync_seq[i]);
 914
 915		for (j = 0; j < RADEON_NUM_RINGS; ++j) {
 916			if (i != j && rdev->fence_drv[j].initialized)
 917				seq_printf(m, "Last sync to ring %d 0x%016llx\n",
 918					   j, rdev->fence_drv[i].sync_seq[j]);
 919		}
 920	}
 921	return 0;
 922}
 923
 924/*
 925 * radeon_debugfs_gpu_reset - manually trigger a gpu reset
 926 *
 927 * Manually trigger a gpu reset at the next fence wait.
 928 */
 929static int radeon_debugfs_gpu_reset(void *data, u64 *val)
 930{
 931	struct radeon_device *rdev = (struct radeon_device *)data;
 932
 933	down_read(&rdev->exclusive_lock);
 934	*val = rdev->needs_reset;
 935	rdev->needs_reset = true;
 936	wake_up_all(&rdev->fence_queue);
 937	up_read(&rdev->exclusive_lock);
 938
 939	return 0;
 940}
 941DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_fence_info);
 942DEFINE_DEBUGFS_ATTRIBUTE(radeon_debugfs_gpu_reset_fops,
 943			 radeon_debugfs_gpu_reset, NULL, "%lld\n");
 944#endif
 945
 946void radeon_debugfs_fence_init(struct radeon_device *rdev)
 947{
 948#if defined(CONFIG_DEBUG_FS)
 949	struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
 950
 951	debugfs_create_file("radeon_gpu_reset", 0444, root, rdev,
 952			    &radeon_debugfs_gpu_reset_fops);
 953	debugfs_create_file("radeon_fence_info", 0444, root, rdev,
 954			    &radeon_debugfs_fence_info_fops);
 955
 956
 957#endif
 958}
 959
 960static const char *radeon_fence_get_driver_name(struct dma_fence *fence)
 961{
 962	return "radeon";
 963}
 964
 965static const char *radeon_fence_get_timeline_name(struct dma_fence *f)
 966{
 967	struct radeon_fence *fence = to_radeon_fence(f);
 968
 969	switch (fence->ring) {
 970	case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx";
 971	case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1";
 972	case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2";
 973	case R600_RING_TYPE_DMA_INDEX: return "radeon.dma";
 974	case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1";
 975	case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
 976	case TN_RING_TYPE_VCE1_INDEX: return "radeon.vce1";
 977	case TN_RING_TYPE_VCE2_INDEX: return "radeon.vce2";
 978	default:
 979		WARN_ON_ONCE(1);
 980		return "radeon.unk";
 981	}
 982}
 983
 984static inline bool radeon_test_signaled(struct radeon_fence *fence)
 985{
 986	return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
 987}
 988
 989struct radeon_wait_cb {
 990	struct dma_fence_cb base;
 991	struct task_struct *task;
 992};
 993
 994static void
 995radeon_fence_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
 996{
 997	struct radeon_wait_cb *wait =
 998		container_of(cb, struct radeon_wait_cb, base);
 999
1000	wake_up_process(wait->task);
1001}
1002
1003static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,
1004					     signed long t)
1005{
1006	struct radeon_fence *fence = to_radeon_fence(f);
1007	struct radeon_device *rdev = fence->rdev;
1008	struct radeon_wait_cb cb;
1009
1010	cb.task = current;
1011
1012	if (dma_fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
1013		return t;
1014
1015	while (t > 0) {
1016		if (intr)
1017			set_current_state(TASK_INTERRUPTIBLE);
1018		else
1019			set_current_state(TASK_UNINTERRUPTIBLE);
1020
1021		/*
1022		 * radeon_test_signaled must be called after
1023		 * set_current_state to prevent a race with wake_up_process
1024		 */
1025		if (radeon_test_signaled(fence))
1026			break;
1027
1028		if (rdev->needs_reset) {
1029			t = -EDEADLK;
1030			break;
1031		}
1032
1033		t = schedule_timeout(t);
1034
1035		if (t > 0 && intr && signal_pending(current))
1036			t = -ERESTARTSYS;
1037	}
1038
1039	__set_current_state(TASK_RUNNING);
1040	dma_fence_remove_callback(f, &cb.base);
1041
1042	return t;
1043}
1044
1045const struct dma_fence_ops radeon_fence_ops = {
1046	.get_driver_name = radeon_fence_get_driver_name,
1047	.get_timeline_name = radeon_fence_get_timeline_name,
1048	.enable_signaling = radeon_fence_enable_signaling,
1049	.signaled = radeon_fence_is_signaled,
1050	.wait = radeon_fence_default_wait,
1051	.release = NULL,
1052};