radeon_drv.c

  1/*
  2 * \file radeon_drv.c
  3 * ATI Radeon driver
  4 *
  5 * \author Gareth Hughes <gareth@valinux.com>
  6 */
  7
  8/*
  9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 10 * All Rights Reserved.
 11 *
 12 * Permission is hereby granted, free of charge, to any person obtaining a
 13 * copy of this software and associated documentation files (the "Software"),
 14 * to deal in the Software without restriction, including without limitation
 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 16 * and/or sell copies of the Software, and to permit persons to whom the
 17 * Software is furnished to do so, subject to the following conditions:
 18 *
 19 * The above copyright notice and this permission notice (including the next
 20 * paragraph) shall be included in all copies or substantial portions of the
 21 * Software.
 22 *
 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 29 * OTHER DEALINGS IN THE SOFTWARE.
 30 */
 31
 32#include <linux/aperture.h>
 33#include <linux/compat.h>
 34#include <linux/module.h>
 35#include <linux/pm_runtime.h>
 36#include <linux/vga_switcheroo.h>
 37#include <linux/mmu_notifier.h>
 38#include <linux/pci.h>
 39
 40#include <drm/clients/drm_client_setup.h>
 41#include <drm/drm_drv.h>
 42#include <drm/drm_file.h>
 43#include <drm/drm_fourcc.h>
 44#include <drm/drm_gem.h>
 45#include <drm/drm_ioctl.h>
 46#include <drm/drm_pciids.h>
 47#include <drm/drm_probe_helper.h>
 48#include <drm/drm_vblank.h>
 49#include <drm/radeon_drm.h>
 50
 51#include "radeon_drv.h"
 52#include "radeon.h"
 53#include "radeon_kms.h"
 54#include "radeon_ttm.h"
 55#include "radeon_device.h"
 56#include "radeon_prime.h"
 57
 58/*
 59 * KMS wrapper.
 60 * - 2.0.0 - initial interface
 61 * - 2.1.0 - add square tiling interface
 62 * - 2.2.0 - add r6xx/r7xx const buffer support
 63 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
 64 * - 2.4.0 - add crtc id query
 65 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
 66 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
 67 *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
 68 *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
 69 *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
 70 *   2.10.0 - fusion 2D tiling
 71 *   2.11.0 - backend map, initial compute support for the CS checker
 72 *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
 73 *   2.13.0 - virtual memory support, streamout
 74 *   2.14.0 - add evergreen tiling informations
 75 *   2.15.0 - add max_pipes query
 76 *   2.16.0 - fix evergreen 2D tiled surface calculation
 77 *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
 78 *   2.18.0 - r600-eg: allow "invalid" DB formats
 79 *   2.19.0 - r600-eg: MSAA textures
 80 *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
 81 *   2.21.0 - r600-r700: FMASK and CMASK
 82 *   2.22.0 - r600 only: RESOLVE_BOX allowed
 83 *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
 84 *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
 85 *   2.25.0 - eg+: new info request for num SE and num SH
 86 *   2.26.0 - r600-eg: fix htile size computation
 87 *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
 88 *   2.28.0 - r600-eg: Add MEM_WRITE packet support
 89 *   2.29.0 - R500 FP16 color clear registers
 90 *   2.30.0 - fix for FMASK texturing
 91 *   2.31.0 - Add fastfb support for rs690
 92 *   2.32.0 - new info request for rings working
 93 *   2.33.0 - Add SI tiling mode array query
 94 *   2.34.0 - Add CIK tiling mode array query
 95 *   2.35.0 - Add CIK macrotile mode array query
 96 *   2.36.0 - Fix CIK DCE tiling setup
 97 *   2.37.0 - allow GS ring setup on r6xx/r7xx
 98 *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
 99 *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
100 *   2.39.0 - Add INFO query for number of active CUs
101 *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
102 *            CS to GPU on >= r600
103 *   2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
104 *   2.42.0 - Add VCE/VUI (Video Usability Information) support
105 *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
106 *   2.44.0 - SET_APPEND_CNT packet3 support
107 *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
108 *   2.46.0 - Add PFP_SYNC_ME support on evergreen
109 *   2.47.0 - Add UVD_NO_OP register support
110 *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
111 *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
112 *   2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
113 *   2.51.0 - Add evergreen/cayman OpenGL 4.6 compatibility
114 */
115#define KMS_DRIVER_MAJOR	2
116#define KMS_DRIVER_MINOR	51
117#define KMS_DRIVER_PATCHLEVEL	0
118
119int radeon_no_wb;
120int radeon_modeset = -1;
121int radeon_dynclks = -1;
122int radeon_r4xx_atom;
123int radeon_agpmode = -1;
124int radeon_vram_limit;
125int radeon_gart_size = -1; /* auto */
126int radeon_benchmarking;
127int radeon_testing;
128int radeon_connector_table;
129int radeon_tv = 1;
130int radeon_audio = -1;
131int radeon_disp_priority;
132int radeon_hw_i2c;
133int radeon_pcie_gen2 = -1;
134int radeon_msi = -1;
135int radeon_lockup_timeout = 10000;
136int radeon_fastfb;
137int radeon_dpm = -1;
138int radeon_aspm = -1;
139int radeon_runtime_pm = -1;
140int radeon_hard_reset;
141int radeon_vm_size = 8;
142int radeon_vm_block_size = -1;
143int radeon_deep_color;
144int radeon_use_pflipirq = 2;
145int radeon_bapm = -1;
146int radeon_backlight = -1;
147int radeon_auxch = -1;
148int radeon_uvd = 1;
149int radeon_vce = 1;
150
151MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
152module_param_named(no_wb, radeon_no_wb, int, 0444);
153
154MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
155module_param_named(modeset, radeon_modeset, int, 0400);
156
157MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
158module_param_named(dynclks, radeon_dynclks, int, 0444);
159
160MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
161module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
162
163MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
164module_param_named(vramlimit, radeon_vram_limit, int, 0600);
165
166MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
167module_param_named(agpmode, radeon_agpmode, int, 0444);
168
169MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
170module_param_named(gartsize, radeon_gart_size, int, 0600);
171
172MODULE_PARM_DESC(benchmark, "Run benchmark");
173module_param_named(benchmark, radeon_benchmarking, int, 0444);
174
175MODULE_PARM_DESC(test, "Run tests");
176module_param_named(test, radeon_testing, int, 0444);
177
178MODULE_PARM_DESC(connector_table, "Force connector table");
179module_param_named(connector_table, radeon_connector_table, int, 0444);
180
181MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
182module_param_named(tv, radeon_tv, int, 0444);
183
184MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
185module_param_named(audio, radeon_audio, int, 0444);
186
187MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
188module_param_named(disp_priority, radeon_disp_priority, int, 0444);
189
190MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
191module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
192
193MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
194module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
195
196MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
197module_param_named(msi, radeon_msi, int, 0444);
198
199MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
200module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
201
202MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
203module_param_named(fastfb, radeon_fastfb, int, 0444);
204
205MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
206module_param_named(dpm, radeon_dpm, int, 0444);
207
208MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
209module_param_named(aspm, radeon_aspm, int, 0444);
210
211MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
212module_param_named(runpm, radeon_runtime_pm, int, 0444);
213
214MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
215module_param_named(hard_reset, radeon_hard_reset, int, 0444);
216
217MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
218module_param_named(vm_size, radeon_vm_size, int, 0444);
219
220MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
221module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
222
223MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
224module_param_named(deep_color, radeon_deep_color, int, 0444);
225
226MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
227module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
228
229MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
230module_param_named(bapm, radeon_bapm, int, 0444);
231
232MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
233module_param_named(backlight, radeon_backlight, int, 0444);
234
235MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
236module_param_named(auxch, radeon_auxch, int, 0444);
237
238MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
239module_param_named(uvd, radeon_uvd, int, 0444);
240
241MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
242module_param_named(vce, radeon_vce, int, 0444);
243
244int radeon_si_support = -1;
245MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)");
246module_param_named(si_support, radeon_si_support, int, 0444);
247
248int radeon_cik_support = -1;
249MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)");
250module_param_named(cik_support, radeon_cik_support, int, 0444);
251
252static const struct pci_device_id pciidlist[] = {
253	radeon_PCI_IDS
254};
255MODULE_DEVICE_TABLE(pci, pciidlist);
256
257static const struct drm_driver kms_driver;
258
259static bool radeon_support_enabled(struct device *dev,
260				   const enum radeon_family family)
261{
262	const char *gen;
263	int module_param = -1;
264	bool amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU);
265	bool support_by_default = true;
266
267	switch (family) {
268	case CHIP_TAHITI:
269	case CHIP_PITCAIRN:
270	case CHIP_VERDE:
271	case CHIP_OLAND:
272	case CHIP_HAINAN:
273		gen = "SI";
274		module_param = radeon_si_support;
275		amdgpu_support_built &= IS_ENABLED(CONFIG_DRM_AMDGPU_SI);
276		support_by_default = false;
277		break;
278
279	case CHIP_BONAIRE:
280	case CHIP_HAWAII:
281		support_by_default = false;
282		fallthrough;
283	case CHIP_KAVERI:
284	case CHIP_KABINI:
285	case CHIP_MULLINS:
286		gen = "CIK";
287		module_param = radeon_cik_support;
288		amdgpu_support_built &= IS_ENABLED(CONFIG_DRM_AMDGPU_CIK);
289		break;
290
291	default:
292		/* All other chips are supported by radeon only */
293		return true;
294	}
295
296	if ((module_param == -1 && (support_by_default || !amdgpu_support_built)) ||
297	    module_param == 1)
298		return true;
299
300	if (!module_param)
301		dev_info(dev, "%s support disabled by module param\n", gen);
302
303	return false;
304}
305
306static int radeon_pci_probe(struct pci_dev *pdev,
307			    const struct pci_device_id *ent)
308{
309	unsigned long flags = 0;
310	struct drm_device *ddev;
311	struct radeon_device *rdev;
312	struct device *dev = &pdev->dev;
313	const struct drm_format_info *format;
314	int ret;
315
316	if (!ent)
317		return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
318
319	flags = ent->driver_data;
320
321	if (!radeon_support_enabled(dev, flags & RADEON_FAMILY_MASK))
322		return -ENODEV;
323
324	if (vga_switcheroo_client_probe_defer(pdev))
325		return -EPROBE_DEFER;
326
327	/* Get rid of things like offb */
328	ret = aperture_remove_conflicting_pci_devices(pdev, kms_driver.name);
329	if (ret)
330		return ret;
331
332	rdev = devm_drm_dev_alloc(dev, &kms_driver, typeof(*rdev), ddev);
333	if (IS_ERR(rdev))
334		return PTR_ERR(rdev);
335
336	rdev->dev = dev;
337	rdev->pdev = pdev;
338	ddev = rdev_to_drm(rdev);
339	ddev->dev_private = rdev;
340
341	ret = pci_enable_device(pdev);
342	if (ret)
343		return ret;
344
345	pci_set_drvdata(pdev, ddev);
346
347	ret = radeon_driver_load_kms(ddev, flags);
348	if (ret)
349		goto err;
350
351	ret = drm_dev_register(ddev, flags);
352	if (ret)
353		goto err;
354
355	if (rdev->mc.real_vram_size <= (8 * 1024 * 1024))
356		format = drm_format_info(DRM_FORMAT_C8);
357	else if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32 * 1024 * 1024))
358		format = drm_format_info(DRM_FORMAT_RGB565);
359	else
360		format = NULL;
361
362	drm_client_setup(ddev, format);
363
364	return 0;
365
366err:
367	pci_disable_device(pdev);
368	return ret;
369}
370
371static void
372radeon_pci_shutdown(struct pci_dev *pdev)
373{
374#if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
375	/*
376	 * Some adapters need to be suspended before a
377	 * shutdown occurs in order to prevent an error
378	 * during kexec, shutdown or reboot.
379	 * Make this power and Loongson specific because
380	 * it breaks some other boards.
381	 */
382	radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
383#endif
384}
385
386static int radeon_pmops_suspend(struct device *dev)
387{
388	struct drm_device *drm_dev = dev_get_drvdata(dev);
389
390	return radeon_suspend_kms(drm_dev, true, true, false);
391}
392
393static int radeon_pmops_resume(struct device *dev)
394{
395	struct drm_device *drm_dev = dev_get_drvdata(dev);
396
397	/* GPU comes up enabled by the bios on resume */
398	if (radeon_is_px(drm_dev)) {
399		pm_runtime_disable(dev);
400		pm_runtime_set_active(dev);
401		pm_runtime_enable(dev);
402	}
403
404	return radeon_resume_kms(drm_dev, true, true);
405}
406
407static int radeon_pmops_freeze(struct device *dev)
408{
409	struct drm_device *drm_dev = dev_get_drvdata(dev);
410
411	return radeon_suspend_kms(drm_dev, false, true, true);
412}
413
414static int radeon_pmops_thaw(struct device *dev)
415{
416	struct drm_device *drm_dev = dev_get_drvdata(dev);
417
418	return radeon_resume_kms(drm_dev, false, true);
419}
420
421static int radeon_pmops_runtime_suspend(struct device *dev)
422{
423	struct pci_dev *pdev = to_pci_dev(dev);
424	struct drm_device *drm_dev = pci_get_drvdata(pdev);
425
426	if (!radeon_is_px(drm_dev)) {
427		pm_runtime_forbid(dev);
428		return -EBUSY;
429	}
430
431	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
432	drm_kms_helper_poll_disable(drm_dev);
433
434	radeon_suspend_kms(drm_dev, false, false, false);
435	pci_save_state(pdev);
436	pci_disable_device(pdev);
437	pci_ignore_hotplug(pdev);
438	if (radeon_is_atpx_hybrid())
439		pci_set_power_state(pdev, PCI_D3cold);
440	else if (!radeon_has_atpx_dgpu_power_cntl())
441		pci_set_power_state(pdev, PCI_D3hot);
442	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
443
444	return 0;
445}
446
447static int radeon_pmops_runtime_resume(struct device *dev)
448{
449	struct pci_dev *pdev = to_pci_dev(dev);
450	struct drm_device *drm_dev = pci_get_drvdata(pdev);
451	int ret;
452
453	if (!radeon_is_px(drm_dev))
454		return -EINVAL;
455
456	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
457
458	if (radeon_is_atpx_hybrid() ||
459	    !radeon_has_atpx_dgpu_power_cntl())
460		pci_set_power_state(pdev, PCI_D0);
461	pci_restore_state(pdev);
462	ret = pci_enable_device(pdev);
463	if (ret)
464		return ret;
465	pci_set_master(pdev);
466
467	ret = radeon_resume_kms(drm_dev, false, false);
468	drm_kms_helper_poll_enable(drm_dev);
469	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
470	return 0;
471}
472
473static int radeon_pmops_runtime_idle(struct device *dev)
474{
475	struct drm_device *drm_dev = dev_get_drvdata(dev);
476	struct drm_crtc *crtc;
477
478	if (!radeon_is_px(drm_dev)) {
479		pm_runtime_forbid(dev);
480		return -EBUSY;
481	}
482
483	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
484		if (crtc->enabled) {
485			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
486			return -EBUSY;
487		}
488	}
489
490	pm_runtime_autosuspend(dev);
491	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
492	return 1;
493}
494
495long radeon_drm_ioctl(struct file *filp,
496		      unsigned int cmd, unsigned long arg)
497{
498	struct drm_file *file_priv = filp->private_data;
499	struct drm_device *dev;
500	long ret;
501
502	dev = file_priv->minor->dev;
503	ret = pm_runtime_get_sync(dev->dev);
504	if (ret < 0) {
505		pm_runtime_put_autosuspend(dev->dev);
506		return ret;
507	}
508
509	ret = drm_ioctl(filp, cmd, arg);
510
511	pm_runtime_put_autosuspend(dev->dev);
512	return ret;
513}
514
515#ifdef CONFIG_COMPAT
516static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
517{
518	unsigned int nr = DRM_IOCTL_NR(cmd);
519
520	if (nr < DRM_COMMAND_BASE)
521		return drm_compat_ioctl(filp, cmd, arg);
522
523	return radeon_drm_ioctl(filp, cmd, arg);
524}
525#endif
526
527static const struct dev_pm_ops radeon_pm_ops = {
528	.suspend = radeon_pmops_suspend,
529	.resume = radeon_pmops_resume,
530	.freeze = radeon_pmops_freeze,
531	.thaw = radeon_pmops_thaw,
532	.poweroff = radeon_pmops_freeze,
533	.restore = radeon_pmops_resume,
534	.runtime_suspend = radeon_pmops_runtime_suspend,
535	.runtime_resume = radeon_pmops_runtime_resume,
536	.runtime_idle = radeon_pmops_runtime_idle,
537};
538
539static const struct file_operations radeon_driver_kms_fops = {
540	.owner = THIS_MODULE,
541	.open = drm_open,
542	.release = drm_release,
543	.unlocked_ioctl = radeon_drm_ioctl,
544	.mmap = drm_gem_mmap,
545	.poll = drm_poll,
546	.read = drm_read,
547#ifdef CONFIG_COMPAT
548	.compat_ioctl = radeon_kms_compat_ioctl,
549#endif
550	.fop_flags = FOP_UNSIGNED_OFFSET,
551};
552
553static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
554	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
555	DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
556	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
557	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
558	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
559	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
560	DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
561	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
562	DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
563	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
564	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
565	DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
566	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
567	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
568	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
569	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
570	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
571	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
572	DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
573	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
574	DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
575	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
576	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
577	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
578	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
579	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
580	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
581	/* KMS */
582	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
583	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
584	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
585	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
586	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
587	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
588	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
589	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
590	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
591	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
592	DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
593	DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
594	DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
595};
596
597static const struct drm_driver kms_driver = {
598	.driver_features =
599	    DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
600	.open = radeon_driver_open_kms,
601	.postclose = radeon_driver_postclose_kms,
602	.unload = radeon_driver_unload_kms,
603	.ioctls = radeon_ioctls_kms,
604	.num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
605	.dumb_create = radeon_mode_dumb_create,
606	.dumb_map_offset = radeon_mode_dumb_mmap,
607	.fops = &radeon_driver_kms_fops,
608
609	.gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
610
611	RADEON_FBDEV_DRIVER_OPS,
612
613	.name = DRIVER_NAME,
614	.desc = DRIVER_DESC,
615	.major = KMS_DRIVER_MAJOR,
616	.minor = KMS_DRIVER_MINOR,
617	.patchlevel = KMS_DRIVER_PATCHLEVEL,
618};
619
620static struct pci_driver radeon_kms_pci_driver = {
621	.name = DRIVER_NAME,
622	.id_table = pciidlist,
623	.probe = radeon_pci_probe,
624	.shutdown = radeon_pci_shutdown,
625	.driver.pm = &radeon_pm_ops,
626};
627
628static int __init radeon_module_init(void)
629{
630	if (drm_firmware_drivers_only() && radeon_modeset == -1)
631		radeon_modeset = 0;
632
633	if (radeon_modeset == 0)
634		return -EINVAL;
635
636	DRM_INFO("radeon kernel modesetting enabled.\n");
637	radeon_register_atpx_handler();
638
639	return pci_register_driver(&radeon_kms_pci_driver);
640}
641
642static void __exit radeon_module_exit(void)
643{
644	pci_unregister_driver(&radeon_kms_pci_driver);
645	radeon_unregister_atpx_handler();
646	mmu_notifier_synchronize();
647}
648
649module_init(radeon_module_init);
650module_exit(radeon_module_exit);
651
652MODULE_AUTHOR(DRIVER_AUTHOR);
653MODULE_DESCRIPTION(DRIVER_DESC);
654MODULE_LICENSE("GPL and additional rights");