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atombios.h
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linux-6.19.14/drivers/gpu/drm/radeon/atombios.h
1/* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 24/****************************************************************************/ 25/*Portion I: Definitions shared between VBIOS and Driver */ 26/****************************************************************************/ 27 28 29#ifndef _ATOMBIOS_H 30#define _ATOMBIOS_H 31 32#define ATOM_VERSION_MAJOR 0x00020000 33#define ATOM_VERSION_MINOR 0x00000002 34 35#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 36 37/* Endianness should be specified before inclusion, 38 * default to little endian 39 */ 40#ifndef ATOM_BIG_ENDIAN 41#error Endian not specified 42#endif 43 44#ifdef _H2INC 45 #ifndef ULONG 46 typedef unsigned long ULONG; 47 #endif 48 49 #ifndef UCHAR 50 typedef unsigned char UCHAR; 51 #endif 52 53 #ifndef USHORT 54 typedef unsigned short USHORT; 55 #endif 56#endif 57 58#define ATOM_DAC_A 0 59#define ATOM_DAC_B 1 60#define ATOM_EXT_DAC 2 61 62#define ATOM_CRTC1 0 63#define ATOM_CRTC2 1 64#define ATOM_CRTC3 2 65#define ATOM_CRTC4 3 66#define ATOM_CRTC5 4 67#define ATOM_CRTC6 5 68#define ATOM_CRTC_INVALID 0xFF 69 70#define ATOM_DIGA 0 71#define ATOM_DIGB 1 72 73#define ATOM_PPLL1 0 74#define ATOM_PPLL2 1 75#define ATOM_DCPLL 2 76#define ATOM_PPLL0 2 77#define ATOM_PPLL3 3 78 79#define ATOM_EXT_PLL1 8 80#define ATOM_EXT_PLL2 9 81#define ATOM_EXT_CLOCK 10 82#define ATOM_PPLL_INVALID 0xFF 83 84#define ENCODER_REFCLK_SRC_P1PLL 0 85#define ENCODER_REFCLK_SRC_P2PLL 1 86#define ENCODER_REFCLK_SRC_DCPLL 2 87#define ENCODER_REFCLK_SRC_EXTCLK 3 88#define ENCODER_REFCLK_SRC_INVALID 0xFF 89 90#define ATOM_SCALER1 0 91#define ATOM_SCALER2 1 92 93#define ATOM_SCALER_DISABLE 0 94#define ATOM_SCALER_CENTER 1 95#define ATOM_SCALER_EXPANSION 2 96#define ATOM_SCALER_MULTI_EX 3 97 98#define ATOM_DISABLE 0 99#define ATOM_ENABLE 1 100#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 101#define ATOM_LCD_BLON (ATOM_ENABLE+2) 102#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 103#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 104#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 105#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 106#define ATOM_INIT (ATOM_DISABLE+7) 107#define ATOM_GET_STATUS (ATOM_DISABLE+8) 108 109#define ATOM_BLANKING 1 110#define ATOM_BLANKING_OFF 0 111 112#define ATOM_CURSOR1 0 113#define ATOM_CURSOR2 1 114 115#define ATOM_ICON1 0 116#define ATOM_ICON2 1 117 118#define ATOM_CRT1 0 119#define ATOM_CRT2 1 120 121#define ATOM_TV_NTSC 1 122#define ATOM_TV_NTSCJ 2 123#define ATOM_TV_PAL 3 124#define ATOM_TV_PALM 4 125#define ATOM_TV_PALCN 5 126#define ATOM_TV_PALN 6 127#define ATOM_TV_PAL60 7 128#define ATOM_TV_SECAM 8 129#define ATOM_TV_CV 16 130 131#define ATOM_DAC1_PS2 1 132#define ATOM_DAC1_CV 2 133#define ATOM_DAC1_NTSC 3 134#define ATOM_DAC1_PAL 4 135 136#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 137#define ATOM_DAC2_CV ATOM_DAC1_CV 138#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 139#define ATOM_DAC2_PAL ATOM_DAC1_PAL 140 141#define ATOM_PM_ON 0 142#define ATOM_PM_STANDBY 1 143#define ATOM_PM_SUSPEND 2 144#define ATOM_PM_OFF 3 145 146/* Bit0:{=0:single, =1:dual}, 147 Bit1 {=0:666RGB, =1:888RGB}, 148 Bit2:3:{Grey level} 149 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 150 151#define ATOM_PANEL_MISC_DUAL 0x00000001 152#define ATOM_PANEL_MISC_888RGB 0x00000002 153#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 154#define ATOM_PANEL_MISC_FPDI 0x00000010 155#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 156#define ATOM_PANEL_MISC_SPATIAL 0x00000020 157#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 158#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 159 160 161#define MEMTYPE_DDR1 "DDR1" 162#define MEMTYPE_DDR2 "DDR2" 163#define MEMTYPE_DDR3 "DDR3" 164#define MEMTYPE_DDR4 "DDR4" 165 166#define ASIC_BUS_TYPE_PCI "PCI" 167#define ASIC_BUS_TYPE_AGP "AGP" 168#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 169 170/* Maximum size of that FireGL flag string */ 171 172#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 173#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 174 175#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 176#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 177 178#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 179#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 180 181#define HW_ASSISTED_I2C_STATUS_FAILURE 2 182#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 183 184#pragma pack(1) /* BIOS data must use byte alignment */ 185 186/* Define offset to location of ROM header. */ 187 188#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 189#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 190 191#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 192#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 193#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 194#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 195 196/* Common header for all ROM Data tables. 197 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 198 And the pointer actually points to this header. */ 199 200typedef struct _ATOM_COMMON_TABLE_HEADER 201{ 202 USHORT usStructureSize; 203 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 204 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 205 /*Image can't be updated, while Driver needs to carry the new table! */ 206}ATOM_COMMON_TABLE_HEADER; 207 208/****************************************************************************/ 209// Structure stores the ROM header. 210/****************************************************************************/ 211typedef struct _ATOM_ROM_HEADER 212{ 213 ATOM_COMMON_TABLE_HEADER sHeader; 214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 215 atombios should init it as "ATOM", don't change the position */ 216 USHORT usBiosRuntimeSegmentAddress; 217 USHORT usProtectedModeInfoOffset; 218 USHORT usConfigFilenameOffset; 219 USHORT usCRC_BlockOffset; 220 USHORT usBIOS_BootupMessageOffset; 221 USHORT usInt10Offset; 222 USHORT usPciBusDevInitCode; 223 USHORT usIoBaseAddress; 224 USHORT usSubsystemVendorID; 225 USHORT usSubsystemID; 226 USHORT usPCI_InfoOffset; 227 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 228 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 229 UCHAR ucExtendedFunctionCode; 230 UCHAR ucReserved; 231}ATOM_ROM_HEADER; 232 233/*==============================Command Table Portion==================================== */ 234 235#ifdef UEFI_BUILD 236 #define UTEMP USHORT 237 #define USHORT void* 238#endif 239 240/****************************************************************************/ 241// Structures used in Command.mtb 242/****************************************************************************/ 243typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 244 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 245 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 246 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 247 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 248 USHORT DIGxEncoderControl; //Only used by Bios 249 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 250 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 251 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 252 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 253 USHORT GPIOPinControl; //Atomic Table, only used by Bios 254 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 255 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 256 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 257 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 258 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 259 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 260 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 261 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 262 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 263 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 264 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 265 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 266 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 267 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 268 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 269 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 270 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 271 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 272 USHORT GetConditionalGoldenSetting; //Only used by Bios 273 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 274 USHORT PatchMCSetting; //only used by BIOS 275 USHORT MC_SEQ_Control; //only used by BIOS 276 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 277 USHORT EnableScaler; //Atomic Table, used only by Bios 278 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 279 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 280 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 281 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 282 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 283 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 284 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 285 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 286 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 287 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 288 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 289 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 290 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 291 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 292 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 293 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 294 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 295 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 296 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 297 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 298 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 299 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 300 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 301 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 302 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 303 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 304 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 305 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 306 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 307 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 308 USHORT MemoryTraining; //Atomic Table, used only by Bios 309 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 310 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 311 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 312 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 313 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 314 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 315 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 316 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 317 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 318 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 319 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 320 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 321 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 322 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 323 USHORT DPEncoderService; //Function Table,only used by Bios 324 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 325}ATOM_MASTER_LIST_OF_COMMAND_TABLES; 326 327// For backward compatible 328#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 329#define DPTranslatorControl DIG2EncoderControl 330#define UNIPHYTransmitterControl DIG1TransmitterControl 331#define LVTMATransmitterControl DIG2TransmitterControl 332#define SetCRTC_DPM_State GetConditionalGoldenSetting 333#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 334#define HPDInterruptService ReadHWAssistedI2CStatus 335#define EnableVGA_Access GetSCLKOverMCLKRatio 336#define EnableYUV GetDispObjectInfo 337#define DynamicClockGating EnableDispPowerGating 338#define SetupHWAssistedI2CStatus ComputeMemoryClockParam 339 340#define TMDSAEncoderControl PatchMCSetting 341#define LVDSEncoderControl MC_SEQ_Control 342#define LCD1OutputControl HW_Misc_Operation 343#define TV1OutputControl Gfx_Harvesting 344 345typedef struct _ATOM_MASTER_COMMAND_TABLE 346{ 347 ATOM_COMMON_TABLE_HEADER sHeader; 348 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 349}ATOM_MASTER_COMMAND_TABLE; 350 351/****************************************************************************/ 352// Structures used in every command table 353/****************************************************************************/ 354typedef struct _ATOM_TABLE_ATTRIBUTE 355{ 356#if ATOM_BIG_ENDIAN 357 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 358 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 360#else 361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 362 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 363 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 364#endif 365}ATOM_TABLE_ATTRIBUTE; 366 367typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 368{ 369 ATOM_TABLE_ATTRIBUTE sbfAccess; 370 USHORT susAccess; 371}ATOM_TABLE_ATTRIBUTE_ACCESS; 372 373/****************************************************************************/ 374// Common header for all command tables. 375// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 376// And the pointer actually points to this header. 377/****************************************************************************/ 378typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 379{ 380 ATOM_COMMON_TABLE_HEADER CommonHeader; 381 ATOM_TABLE_ATTRIBUTE TableAttribute; 382}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 383 384/****************************************************************************/ 385// Structures used by ComputeMemoryEnginePLLTable 386/****************************************************************************/ 387#define COMPUTE_MEMORY_PLL_PARAM 1 388#define COMPUTE_ENGINE_PLL_PARAM 2 389#define ADJUST_MC_SETTING_PARAM 3 390 391/****************************************************************************/ 392// Structures used by AdjustMemoryControllerTable 393/****************************************************************************/ 394typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 395{ 396#if ATOM_BIG_ENDIAN 397 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 398 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 399 ULONG ulClockFreq:24; 400#else 401 ULONG ulClockFreq:24; 402 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 403 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 404#endif 405}ATOM_ADJUST_MEMORY_CLOCK_FREQ; 406#define POINTER_RETURN_FLAG 0x80 407 408typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 409{ 410 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 411 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 412 UCHAR ucReserved; //may expand to return larger Fbdiv later 413 UCHAR ucFbDiv; //return value 414 UCHAR ucPostDiv; //return value 415}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 416 417typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 418{ 419 ULONG ulClock; //When return, [23:0] return real clock 420 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 421 USHORT usFbDiv; //return Feedback value to be written to register 422 UCHAR ucPostDiv; //return post div to be written to register 423}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 424#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 425 426 427#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 428#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 429#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 430#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 431#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 432#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 433#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 434 435#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 436#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 437#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 438#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 439#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 440 441typedef struct _ATOM_COMPUTE_CLOCK_FREQ 442{ 443#if ATOM_BIG_ENDIAN 444 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 445 ULONG ulClockFreq:24; // in unit of 10kHz 446#else 447 ULONG ulClockFreq:24; // in unit of 10kHz 448 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 449#endif 450}ATOM_COMPUTE_CLOCK_FREQ; 451 452typedef struct _ATOM_S_MPLL_FB_DIVIDER 453{ 454 USHORT usFbDivFrac; 455 USHORT usFbDiv; 456}ATOM_S_MPLL_FB_DIVIDER; 457 458typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 459{ 460 union 461 { 462 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 463 ULONG ulClockParams; //ULONG access for BE 464 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 465 }; 466 UCHAR ucRefDiv; //Output Parameter 467 UCHAR ucPostDiv; //Output Parameter 468 UCHAR ucCntlFlag; //Output Parameter 469 UCHAR ucReserved; 470}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 471 472// ucCntlFlag 473#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 474#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 475#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 476#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 477 478 479// V4 are only used for APU which PLL outside GPU 480typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 481{ 482#if ATOM_BIG_ENDIAN 483 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 484 ULONG ulClock:24; //Input= target clock, output = actual clock 485#else 486 ULONG ulClock:24; //Input= target clock, output = actual clock 487 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 488#endif 489}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 490 491typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 492{ 493 union 494 { 495 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 496 ULONG ulClockParams; //ULONG access for BE 497 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 498 }; 499 UCHAR ucRefDiv; //Output Parameter 500 UCHAR ucPostDiv; //Output Parameter 501 union 502 { 503 UCHAR ucCntlFlag; //Output Flags 504 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 505 }; 506 UCHAR ucReserved; 507}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 508 509 510typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 511{ 512 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 513 ULONG ulReserved[2]; 514}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 515 516//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 517#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 518#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 519#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 520 521typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 522{ 523 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 524 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 525 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 526 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 527 UCHAR ucPllCntlFlag; //Output Flags: control flag 528 UCHAR ucReserved; 529}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 530 531//ucPllCntlFlag 532#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 533 534 535// ucInputFlag 536#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 537 538// use for ComputeMemoryClockParamTable 539typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 540{ 541 union 542 { 543 ULONG ulClock; 544 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 545 }; 546 UCHAR ucDllSpeed; //Output 547 UCHAR ucPostDiv; //Output 548 union{ 549 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 550 UCHAR ucPllCntlFlag; //Output: 551 }; 552 UCHAR ucBWCntl; 553}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 554 555// definition of ucInputFlag 556#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 557// definition of ucPllCntlFlag 558#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 559#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 560#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 561#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 562 563//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 564#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 565 566typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 567{ 568 ATOM_COMPUTE_CLOCK_FREQ ulClock; 569 ULONG ulReserved[2]; 570}DYNAMICE_MEMORY_SETTINGS_PARAMETER; 571 572typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 573{ 574 ATOM_COMPUTE_CLOCK_FREQ ulClock; 575 ULONG ulMemoryClock; 576 ULONG ulReserved; 577}DYNAMICE_ENGINE_SETTINGS_PARAMETER; 578 579/****************************************************************************/ 580// Structures used by SetEngineClockTable 581/****************************************************************************/ 582typedef struct _SET_ENGINE_CLOCK_PARAMETERS 583{ 584 ULONG ulTargetEngineClock; //In 10Khz unit 585}SET_ENGINE_CLOCK_PARAMETERS; 586 587typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 588{ 589 ULONG ulTargetEngineClock; //In 10Khz unit 590 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 591}SET_ENGINE_CLOCK_PS_ALLOCATION; 592 593/****************************************************************************/ 594// Structures used by SetMemoryClockTable 595/****************************************************************************/ 596typedef struct _SET_MEMORY_CLOCK_PARAMETERS 597{ 598 ULONG ulTargetMemoryClock; //In 10Khz unit 599}SET_MEMORY_CLOCK_PARAMETERS; 600 601typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 602{ 603 ULONG ulTargetMemoryClock; //In 10Khz unit 604 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 605}SET_MEMORY_CLOCK_PS_ALLOCATION; 606 607/****************************************************************************/ 608// Structures used by ASIC_Init.ctb 609/****************************************************************************/ 610typedef struct _ASIC_INIT_PARAMETERS 611{ 612 ULONG ulDefaultEngineClock; //In 10Khz unit 613 ULONG ulDefaultMemoryClock; //In 10Khz unit 614}ASIC_INIT_PARAMETERS; 615 616typedef struct _ASIC_INIT_PS_ALLOCATION 617{ 618 ASIC_INIT_PARAMETERS sASICInitClocks; 619 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 620}ASIC_INIT_PS_ALLOCATION; 621 622/****************************************************************************/ 623// Structure used by DynamicClockGatingTable.ctb 624/****************************************************************************/ 625typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 626{ 627 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 628 UCHAR ucPadding[3]; 629}DYNAMIC_CLOCK_GATING_PARAMETERS; 630#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 631 632/****************************************************************************/ 633// Structure used by EnableDispPowerGatingTable.ctb 634/****************************************************************************/ 635typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 636{ 637 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 638 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 639 UCHAR ucPadding[2]; 640}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 641 642/****************************************************************************/ 643// Structure used by EnableASIC_StaticPwrMgtTable.ctb 644/****************************************************************************/ 645typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 646{ 647 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 648 UCHAR ucPadding[3]; 649}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 650#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 651 652/****************************************************************************/ 653// Structures used by DAC_LoadDetectionTable.ctb 654/****************************************************************************/ 655typedef struct _DAC_LOAD_DETECTION_PARAMETERS 656{ 657 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 658 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 659 UCHAR ucMisc; //Valid only when table revision =1.3 and above 660}DAC_LOAD_DETECTION_PARAMETERS; 661 662// DAC_LOAD_DETECTION_PARAMETERS.ucMisc 663#define DAC_LOAD_MISC_YPrPb 0x01 664 665typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 666{ 667 DAC_LOAD_DETECTION_PARAMETERS sDacload; 668 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 669}DAC_LOAD_DETECTION_PS_ALLOCATION; 670 671/****************************************************************************/ 672// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 673/****************************************************************************/ 674typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 675{ 676 USHORT usPixelClock; // in 10KHz; for bios convenient 677 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 678 UCHAR ucAction; // 0: turn off encoder 679 // 1: setup and turn on encoder 680 // 7: ATOM_ENCODER_INIT Initialize DAC 681}DAC_ENCODER_CONTROL_PARAMETERS; 682 683#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 684 685/****************************************************************************/ 686// Structures used by DIG1EncoderControlTable 687// DIG2EncoderControlTable 688// ExternalEncoderControlTable 689/****************************************************************************/ 690typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 691{ 692 USHORT usPixelClock; // in 10KHz; for bios convenient 693 UCHAR ucConfig; 694 // [2] Link Select: 695 // =0: PHY linkA if bfLane<3 696 // =1: PHY linkB if bfLanes<3 697 // =0: PHY linkA+B if bfLanes=3 698 // [3] Transmitter Sel 699 // =0: UNIPHY or PCIEPHY 700 // =1: LVTMA 701 UCHAR ucAction; // =0: turn off encoder 702 // =1: turn on encoder 703 UCHAR ucEncoderMode; 704 // =0: DP encoder 705 // =1: LVDS encoder 706 // =2: DVI encoder 707 // =3: HDMI encoder 708 // =4: SDVO encoder 709 UCHAR ucLaneNum; // how many lanes to enable 710 UCHAR ucReserved[2]; 711}DIG_ENCODER_CONTROL_PARAMETERS; 712#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 713#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 714 715//ucConfig 716#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 717#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 718#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 719#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 720#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 721#define ATOM_ENCODER_CONFIG_LINKA 0x00 722#define ATOM_ENCODER_CONFIG_LINKB 0x04 723#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 724#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 725#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 726#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 727#define ATOM_ENCODER_CONFIG_LVTMA 0x08 728#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 729#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 730#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 731// ucAction 732// ATOM_ENABLE: Enable Encoder 733// ATOM_DISABLE: Disable Encoder 734 735//ucEncoderMode 736#define ATOM_ENCODER_MODE_DP 0 737#define ATOM_ENCODER_MODE_LVDS 1 738#define ATOM_ENCODER_MODE_DVI 2 739#define ATOM_ENCODER_MODE_HDMI 3 740#define ATOM_ENCODER_MODE_SDVO 4 741#define ATOM_ENCODER_MODE_DP_AUDIO 5 742#define ATOM_ENCODER_MODE_TV 13 743#define ATOM_ENCODER_MODE_CV 14 744#define ATOM_ENCODER_MODE_CRT 15 745#define ATOM_ENCODER_MODE_DVO 16 746#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 747#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 748 749typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 750{ 751#if ATOM_BIG_ENDIAN 752 UCHAR ucReserved1:2; 753 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 754 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 755 UCHAR ucReserved:1; 756 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 757#else 758 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 759 UCHAR ucReserved:1; 760 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 761 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 762 UCHAR ucReserved1:2; 763#endif 764}ATOM_DIG_ENCODER_CONFIG_V2; 765 766 767typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 768{ 769 USHORT usPixelClock; // in 10KHz; for bios convenient 770 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 771 UCHAR ucAction; 772 UCHAR ucEncoderMode; 773 // =0: DP encoder 774 // =1: LVDS encoder 775 // =2: DVI encoder 776 // =3: HDMI encoder 777 // =4: SDVO encoder 778 UCHAR ucLaneNum; // how many lanes to enable 779 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 780 UCHAR ucReserved; 781}DIG_ENCODER_CONTROL_PARAMETERS_V2; 782 783//ucConfig 784#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 785#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 786#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 787#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 788#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 789#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 790#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 791#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 792#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 793#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 794 795// ucAction: 796// ATOM_DISABLE 797// ATOM_ENABLE 798#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 799#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 800#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 801#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 802#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 803#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 804#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 805#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 806#define ATOM_ENCODER_CMD_SETUP 0x0f 807#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 808 809// ucStatus 810#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 811#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 812 813//ucTableFormatRevision=1 814//ucTableContentRevision=3 815// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 816typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 817{ 818#if ATOM_BIG_ENDIAN 819 UCHAR ucReserved1:1; 820 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 821 UCHAR ucReserved:3; 822 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 823#else 824 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 825 UCHAR ucReserved:3; 826 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 827 UCHAR ucReserved1:1; 828#endif 829}ATOM_DIG_ENCODER_CONFIG_V3; 830 831#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 832#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 833#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 834#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 835#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 836#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 837#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 838#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 839#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 840#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 841 842typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 843{ 844 USHORT usPixelClock; // in 10KHz; for bios convenient 845 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 846 UCHAR ucAction; 847 union { 848 UCHAR ucEncoderMode; 849 // =0: DP encoder 850 // =1: LVDS encoder 851 // =2: DVI encoder 852 // =3: HDMI encoder 853 // =4: SDVO encoder 854 // =5: DP audio 855 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 856 // =0: external DP 857 // =1: internal DP2 858 // =0x11: internal DP1 for NutMeg/Travis DP translator 859 }; 860 UCHAR ucLaneNum; // how many lanes to enable 861 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 862 UCHAR ucReserved; 863}DIG_ENCODER_CONTROL_PARAMETERS_V3; 864 865//ucTableFormatRevision=1 866//ucTableContentRevision=4 867// start from NI 868// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 869typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 870{ 871#if ATOM_BIG_ENDIAN 872 UCHAR ucReserved1:1; 873 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 874 UCHAR ucReserved:2; 875 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 876#else 877 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 878 UCHAR ucReserved:2; 879 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 880 UCHAR ucReserved1:1; 881#endif 882}ATOM_DIG_ENCODER_CONFIG_V4; 883 884#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 885#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 886#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 887#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 888#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 889#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 890#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 891#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 892#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 893#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 894#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 895#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 896#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 897 898typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 899{ 900 USHORT usPixelClock; // in 10KHz; for bios convenient 901 union{ 902 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 903 UCHAR ucConfig; 904 }; 905 UCHAR ucAction; 906 union { 907 UCHAR ucEncoderMode; 908 // =0: DP encoder 909 // =1: LVDS encoder 910 // =2: DVI encoder 911 // =3: HDMI encoder 912 // =4: SDVO encoder 913 // =5: DP audio 914 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 915 // =0: external DP 916 // =1: internal DP2 917 // =0x11: internal DP1 for NutMeg/Travis DP translator 918 }; 919 UCHAR ucLaneNum; // how many lanes to enable 920 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 921 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 922}DIG_ENCODER_CONTROL_PARAMETERS_V4; 923 924// define ucBitPerColor: 925#define PANEL_BPC_UNDEFINE 0x00 926#define PANEL_6BIT_PER_COLOR 0x01 927#define PANEL_8BIT_PER_COLOR 0x02 928#define PANEL_10BIT_PER_COLOR 0x03 929#define PANEL_12BIT_PER_COLOR 0x04 930#define PANEL_16BIT_PER_COLOR 0x05 931 932//define ucPanelMode 933#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 934#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 935#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 936 937/****************************************************************************/ 938// Structures used by UNIPHYTransmitterControlTable 939// LVTMATransmitterControlTable 940// DVOOutputControlTable 941/****************************************************************************/ 942typedef struct _ATOM_DP_VS_MODE 943{ 944 UCHAR ucLaneSel; 945 UCHAR ucLaneSet; 946}ATOM_DP_VS_MODE; 947 948typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 949{ 950 union 951 { 952 USHORT usPixelClock; // in 10KHz; for bios convenient 953 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 954 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 955 }; 956 UCHAR ucConfig; 957 // [0]=0: 4 lane Link, 958 // =1: 8 lane Link ( Dual Links TMDS ) 959 // [1]=0: InCoherent mode 960 // =1: Coherent Mode 961 // [2] Link Select: 962 // =0: PHY linkA if bfLane<3 963 // =1: PHY linkB if bfLanes<3 964 // =0: PHY linkA+B if bfLanes=3 965 // [5:4]PCIE lane Sel 966 // =0: lane 0~3 or 0~7 967 // =1: lane 4~7 968 // =2: lane 8~11 or 8~15 969 // =3: lane 12~15 970 UCHAR ucAction; // =0: turn off encoder 971 // =1: turn on encoder 972 UCHAR ucReserved[4]; 973}DIG_TRANSMITTER_CONTROL_PARAMETERS; 974 975#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 976 977//ucInitInfo 978#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 979 980//ucConfig 981#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 982#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 983#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 984#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 985#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 986#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 987#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 988 989#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 990#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 991#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 992 993#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 994#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 995#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 996#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 997#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 998#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 999#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1000#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1001#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1002#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1003#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1004 1005//ucAction 1006#define ATOM_TRANSMITTER_ACTION_DISABLE 0 1007#define ATOM_TRANSMITTER_ACTION_ENABLE 1 1008#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1009#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1010#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1011#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1012#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1013#define ATOM_TRANSMITTER_ACTION_INIT 7 1014#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1015#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1016#define ATOM_TRANSMITTER_ACTION_SETUP 10 1017#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1018#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1019#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1020 1021// Following are used for DigTransmitterControlTable ver1.2 1022typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1023{ 1024#if ATOM_BIG_ENDIAN 1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1026 // =1 Dig Transmitter 2 ( Uniphy CD ) 1027 // =2 Dig Transmitter 3 ( Uniphy EF ) 1028 UCHAR ucReserved:1; 1029 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1030 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1031 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1032 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1033 1034 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1035 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1036#else 1037 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1038 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1039 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1040 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1041 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1042 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1043 UCHAR ucReserved:1; 1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1045 // =1 Dig Transmitter 2 ( Uniphy CD ) 1046 // =2 Dig Transmitter 3 ( Uniphy EF ) 1047#endif 1048}ATOM_DIG_TRANSMITTER_CONFIG_V2; 1049 1050//ucConfig 1051//Bit0 1052#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1053 1054//Bit1 1055#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1056 1057//Bit2 1058#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1059#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1060#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1061 1062// Bit3 1063#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1064#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1065#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1066 1067// Bit4 1068#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1069 1070// Bit7:6 1071#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1072#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1073#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1074#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1075 1076typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1077{ 1078 union 1079 { 1080 USHORT usPixelClock; // in 10KHz; for bios convenient 1081 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1082 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1083 }; 1084 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1085 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1086 UCHAR ucReserved[4]; 1087}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1088 1089typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1090{ 1091#if ATOM_BIG_ENDIAN 1092 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1093 // =1 Dig Transmitter 2 ( Uniphy CD ) 1094 // =2 Dig Transmitter 3 ( Uniphy EF ) 1095 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1096 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1097 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1098 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1099 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1101#else 1102 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1103 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1104 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1105 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1106 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1107 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1108 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1109 // =1 Dig Transmitter 2 ( Uniphy CD ) 1110 // =2 Dig Transmitter 3 ( Uniphy EF ) 1111#endif 1112}ATOM_DIG_TRANSMITTER_CONFIG_V3; 1113 1114 1115typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1116{ 1117 union 1118 { 1119 USHORT usPixelClock; // in 10KHz; for bios convenient 1120 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1121 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1122 }; 1123 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1124 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1125 UCHAR ucLaneNum; 1126 UCHAR ucReserved[3]; 1127}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1128 1129//ucConfig 1130//Bit0 1131#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1132 1133//Bit1 1134#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1135 1136//Bit2 1137#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1138#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1139#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1140 1141// Bit3 1142#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1143#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1144#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1145 1146// Bit5:4 1147#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1148#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1149#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1150#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1151 1152// Bit7:6 1153#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1154#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1155#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1156#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1157 1158 1159/****************************************************************************/ 1160// Structures used by UNIPHYTransmitterControlTable V1.4 1161// ASIC Families: NI 1162// ucTableFormatRevision=1 1163// ucTableContentRevision=4 1164/****************************************************************************/ 1165typedef struct _ATOM_DP_VS_MODE_V4 1166{ 1167 UCHAR ucLaneSel; 1168 union 1169 { 1170 UCHAR ucLaneSet; 1171 struct { 1172#if ATOM_BIG_ENDIAN 1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1175 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1176#else 1177 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1180#endif 1181 }; 1182 }; 1183}ATOM_DP_VS_MODE_V4; 1184 1185typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1186{ 1187#if ATOM_BIG_ENDIAN 1188 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1189 // =1 Dig Transmitter 2 ( Uniphy CD ) 1190 // =2 Dig Transmitter 3 ( Uniphy EF ) 1191 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1192 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1193 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1194 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1195 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1196 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1197#else 1198 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1199 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1200 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1201 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1202 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1203 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1204 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1205 // =1 Dig Transmitter 2 ( Uniphy CD ) 1206 // =2 Dig Transmitter 3 ( Uniphy EF ) 1207#endif 1208}ATOM_DIG_TRANSMITTER_CONFIG_V4; 1209 1210typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1211{ 1212 union 1213 { 1214 USHORT usPixelClock; // in 10KHz; for bios convenient 1215 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1216 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1217 }; 1218 union 1219 { 1220 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1221 UCHAR ucConfig; 1222 }; 1223 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1224 UCHAR ucLaneNum; 1225 UCHAR ucReserved[3]; 1226}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1227 1228//ucConfig 1229//Bit0 1230#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1231//Bit1 1232#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1233//Bit2 1234#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1235#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1236#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1237// Bit3 1238#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1239#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1240#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1241// Bit5:4 1242#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1243#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1244#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1245#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1246#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1247// Bit7:6 1248#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1249#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1250#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1251#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1252 1253 1254typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1255{ 1256#if ATOM_BIG_ENDIAN 1257 UCHAR ucReservd1:1; 1258 UCHAR ucHPDSel:3; 1259 UCHAR ucPhyClkSrcId:2; 1260 UCHAR ucCoherentMode:1; 1261 UCHAR ucReserved:1; 1262#else 1263 UCHAR ucReserved:1; 1264 UCHAR ucCoherentMode:1; 1265 UCHAR ucPhyClkSrcId:2; 1266 UCHAR ucHPDSel:3; 1267 UCHAR ucReservd1:1; 1268#endif 1269}ATOM_DIG_TRANSMITTER_CONFIG_V5; 1270 1271typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1272{ 1273 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1274 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1275 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1276 UCHAR ucLaneNum; // indicate lane number 1-8 1277 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1278 UCHAR ucDigMode; // indicate DIG mode 1279 union{ 1280 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1281 UCHAR ucConfig; 1282 }; 1283 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1284 UCHAR ucDPLaneSet; 1285 UCHAR ucReserved; 1286 UCHAR ucReserved1; 1287}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1288 1289//ucPhyId 1290#define ATOM_PHY_ID_UNIPHYA 0 1291#define ATOM_PHY_ID_UNIPHYB 1 1292#define ATOM_PHY_ID_UNIPHYC 2 1293#define ATOM_PHY_ID_UNIPHYD 3 1294#define ATOM_PHY_ID_UNIPHYE 4 1295#define ATOM_PHY_ID_UNIPHYF 5 1296#define ATOM_PHY_ID_UNIPHYG 6 1297 1298// ucDigEncoderSel 1299#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1300#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1301#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1302#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1303#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1304#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1305#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1306 1307// ucDigMode 1308#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1309#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1310#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1311#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1312#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1313#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1314 1315// ucDPLaneSet 1316#define DP_LANE_SET__0DB_0_4V 0x00 1317#define DP_LANE_SET__0DB_0_6V 0x01 1318#define DP_LANE_SET__0DB_0_8V 0x02 1319#define DP_LANE_SET__0DB_1_2V 0x03 1320#define DP_LANE_SET__3_5DB_0_4V 0x08 1321#define DP_LANE_SET__3_5DB_0_6V 0x09 1322#define DP_LANE_SET__3_5DB_0_8V 0x0a 1323#define DP_LANE_SET__6DB_0_4V 0x10 1324#define DP_LANE_SET__6DB_0_6V 0x11 1325#define DP_LANE_SET__9_5DB_0_4V 0x18 1326 1327// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1328// Bit1 1329#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1330 1331// Bit3:2 1332#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1333#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1334 1335#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1336#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1337#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1338#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1339// Bit6:4 1340#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1341#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1342 1343#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1344#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1345#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1346#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1347#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1348#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1349#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1350 1351#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1352 1353 1354/****************************************************************************/ 1355// Structures used by ExternalEncoderControlTable V1.3 1356// ASIC Families: Evergreen, Llano, NI 1357// ucTableFormatRevision=1 1358// ucTableContentRevision=3 1359/****************************************************************************/ 1360 1361typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1362{ 1363 union{ 1364 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1365 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1366 }; 1367 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1368 UCHAR ucAction; // 1369 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1370 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1371 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1372 UCHAR ucReserved; 1373}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1374 1375// ucAction 1376#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1377#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1378#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1379#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1380#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1381#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1382#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1383#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1384 1385// ucConfig 1386#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1387#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1388#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1389#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1390#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 1391#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1392#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1393#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1394 1395typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1396{ 1397 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1398 ULONG ulReserved[2]; 1399}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1400 1401 1402/****************************************************************************/ 1403// Structures used by DAC1OuputControlTable 1404// DAC2OuputControlTable 1405// LVTMAOutputControlTable (Before DEC30) 1406// TMDSAOutputControlTable (Before DEC30) 1407/****************************************************************************/ 1408typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1409{ 1410 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1411 // When the display is LCD, in addition to above: 1412 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1413 // ATOM_LCD_SELFTEST_STOP 1414 1415 UCHAR aucPadding[3]; // padding to DWORD aligned 1416}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1417 1418#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1419 1420 1421#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1422#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1423 1424#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1425#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1426 1427#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1428#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1429 1430#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1431#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1432 1433#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1434#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1435 1436#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1437#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1438 1439#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1440#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1441 1442#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1443#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1444#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1445 1446/****************************************************************************/ 1447// Structures used by BlankCRTCTable 1448/****************************************************************************/ 1449typedef struct _BLANK_CRTC_PARAMETERS 1450{ 1451 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1452 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1453 USHORT usBlackColorRCr; 1454 USHORT usBlackColorGY; 1455 USHORT usBlackColorBCb; 1456}BLANK_CRTC_PARAMETERS; 1457#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1458 1459/****************************************************************************/ 1460// Structures used by EnableCRTCTable 1461// EnableCRTCMemReqTable 1462// UpdateCRTC_DoubleBufferRegistersTable 1463/****************************************************************************/ 1464typedef struct _ENABLE_CRTC_PARAMETERS 1465{ 1466 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1467 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1468 UCHAR ucPadding[2]; 1469}ENABLE_CRTC_PARAMETERS; 1470#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1471 1472/****************************************************************************/ 1473// Structures used by SetCRTC_OverScanTable 1474/****************************************************************************/ 1475typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1476{ 1477 USHORT usOverscanRight; // right 1478 USHORT usOverscanLeft; // left 1479 USHORT usOverscanBottom; // bottom 1480 USHORT usOverscanTop; // top 1481 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1482 UCHAR ucPadding[3]; 1483}SET_CRTC_OVERSCAN_PARAMETERS; 1484#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1485 1486/****************************************************************************/ 1487// Structures used by SetCRTC_ReplicationTable 1488/****************************************************************************/ 1489typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1490{ 1491 UCHAR ucH_Replication; // horizontal replication 1492 UCHAR ucV_Replication; // vertical replication 1493 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1494 UCHAR ucPadding; 1495}SET_CRTC_REPLICATION_PARAMETERS; 1496#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1497 1498/****************************************************************************/ 1499// Structures used by SelectCRTC_SourceTable 1500/****************************************************************************/ 1501typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1502{ 1503 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1504 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1505 UCHAR ucPadding[2]; 1506}SELECT_CRTC_SOURCE_PARAMETERS; 1507#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1508 1509typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1510{ 1511 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1512 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1513 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1514 UCHAR ucPadding; 1515}SELECT_CRTC_SOURCE_PARAMETERS_V2; 1516 1517//ucEncoderID 1518//#define ASIC_INT_DAC1_ENCODER_ID 0x00 1519//#define ASIC_INT_TV_ENCODER_ID 0x02 1520//#define ASIC_INT_DIG1_ENCODER_ID 0x03 1521//#define ASIC_INT_DAC2_ENCODER_ID 0x04 1522//#define ASIC_EXT_TV_ENCODER_ID 0x06 1523//#define ASIC_INT_DVO_ENCODER_ID 0x07 1524//#define ASIC_INT_DIG2_ENCODER_ID 0x09 1525//#define ASIC_EXT_DIG_ENCODER_ID 0x05 1526 1527//ucEncodeMode 1528//#define ATOM_ENCODER_MODE_DP 0 1529//#define ATOM_ENCODER_MODE_LVDS 1 1530//#define ATOM_ENCODER_MODE_DVI 2 1531//#define ATOM_ENCODER_MODE_HDMI 3 1532//#define ATOM_ENCODER_MODE_SDVO 4 1533//#define ATOM_ENCODER_MODE_TV 13 1534//#define ATOM_ENCODER_MODE_CV 14 1535//#define ATOM_ENCODER_MODE_CRT 15 1536 1537/****************************************************************************/ 1538// Structures used by SetPixelClockTable 1539// GetPixelClockTable 1540/****************************************************************************/ 1541//Major revision=1., Minor revision=1 1542typedef struct _PIXEL_CLOCK_PARAMETERS 1543{ 1544 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1545 // 0 means disable PPLL 1546 USHORT usRefDiv; // Reference divider 1547 USHORT usFbDiv; // feedback divider 1548 UCHAR ucPostDiv; // post divider 1549 UCHAR ucFracFbDiv; // fractional feedback divider 1550 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1551 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1552 UCHAR ucCRTC; // Which CRTC uses this Ppll 1553 UCHAR ucPadding; 1554}PIXEL_CLOCK_PARAMETERS; 1555 1556//Major revision=1., Minor revision=2, add ucMiscIfno 1557//ucMiscInfo: 1558#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1559#define MISC_DEVICE_INDEX_MASK 0xF0 1560#define MISC_DEVICE_INDEX_SHIFT 4 1561 1562typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1563{ 1564 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1565 // 0 means disable PPLL 1566 USHORT usRefDiv; // Reference divider 1567 USHORT usFbDiv; // feedback divider 1568 UCHAR ucPostDiv; // post divider 1569 UCHAR ucFracFbDiv; // fractional feedback divider 1570 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1571 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1572 UCHAR ucCRTC; // Which CRTC uses this Ppll 1573 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1574}PIXEL_CLOCK_PARAMETERS_V2; 1575 1576//Major revision=1., Minor revision=3, structure/definition change 1577//ucEncoderMode: 1578//ATOM_ENCODER_MODE_DP 1579//ATOM_ENOCDER_MODE_LVDS 1580//ATOM_ENOCDER_MODE_DVI 1581//ATOM_ENOCDER_MODE_HDMI 1582//ATOM_ENOCDER_MODE_SDVO 1583//ATOM_ENCODER_MODE_TV 13 1584//ATOM_ENCODER_MODE_CV 14 1585//ATOM_ENCODER_MODE_CRT 15 1586 1587//ucDVOConfig 1588//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1589//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1590//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1591//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1592//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1593//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1594//#define DVO_ENCODER_CONFIG_24BIT 0x08 1595 1596//ucMiscInfo: also changed, see below 1597#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1598#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1599#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1600#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1601#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1602#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1603#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1604// V1.4 for RoadRunner 1605#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1606#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1607 1608 1609typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1610{ 1611 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1612 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1613 USHORT usRefDiv; // Reference divider 1614 USHORT usFbDiv; // feedback divider 1615 UCHAR ucPostDiv; // post divider 1616 UCHAR ucFracFbDiv; // fractional feedback divider 1617 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1618 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1619 union 1620 { 1621 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1622 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1623 }; 1624 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1625 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1626 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1627}PIXEL_CLOCK_PARAMETERS_V3; 1628 1629#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1630#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1631 1632typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1633{ 1634 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1635 // drive the pixel clock. not used for DCPLL case. 1636 union{ 1637 UCHAR ucReserved; 1638 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1639 }; 1640 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1641 // 0 means disable PPLL/DCPLL. 1642 USHORT usFbDiv; // feedback divider integer part. 1643 UCHAR ucPostDiv; // post divider. 1644 UCHAR ucRefDiv; // Reference divider 1645 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1646 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1647 // indicate which graphic encoder will be used. 1648 UCHAR ucEncoderMode; // Encoder mode: 1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1650 // bit[1]= when VGA timing is used. 1651 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1652 // bit[4]= RefClock source for PPLL. 1653 // =0: XTLAIN( default mode ) 1654 // =1: other external clock source, which is pre-defined 1655 // by VBIOS depend on the feature required. 1656 // bit[7:5]: reserved. 1657 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1658 1659}PIXEL_CLOCK_PARAMETERS_V5; 1660 1661#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1662#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1663#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1664#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1665#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1666#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1667#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1668 1669typedef struct _CRTC_PIXEL_CLOCK_FREQ 1670{ 1671#if ATOM_BIG_ENDIAN 1672 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1673 // drive the pixel clock. not used for DCPLL case. 1674 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1675 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1676#else 1677 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1678 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1679 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1680 // drive the pixel clock. not used for DCPLL case. 1681#endif 1682}CRTC_PIXEL_CLOCK_FREQ; 1683 1684typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1685{ 1686 union{ 1687 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1688 ULONG ulDispEngClkFreq; // dispclk frequency 1689 }; 1690 USHORT usFbDiv; // feedback divider integer part. 1691 UCHAR ucPostDiv; // post divider. 1692 UCHAR ucRefDiv; // Reference divider 1693 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1694 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1695 // indicate which graphic encoder will be used. 1696 UCHAR ucEncoderMode; // Encoder mode: 1697 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1698 // bit[1]= when VGA timing is used. 1699 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1700 // bit[4]= RefClock source for PPLL. 1701 // =0: XTLAIN( default mode ) 1702 // =1: other external clock source, which is pre-defined 1703 // by VBIOS depend on the feature required. 1704 // bit[7:5]: reserved. 1705 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1706 1707}PIXEL_CLOCK_PARAMETERS_V6; 1708 1709#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1710#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1711#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1712#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1713#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1714#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) 1715#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1716#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) 1717#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1718#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1719#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1720 1721typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1722{ 1723 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1724}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1725 1726typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1727{ 1728 UCHAR ucStatus; 1729 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1730 UCHAR ucReserved[2]; 1731}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1732 1733typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1734{ 1735 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1736}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1737 1738/****************************************************************************/ 1739// Structures used by AdjustDisplayPllTable 1740/****************************************************************************/ 1741typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1742{ 1743 USHORT usPixelClock; 1744 UCHAR ucTransmitterID; 1745 UCHAR ucEncodeMode; 1746 union 1747 { 1748 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1749 UCHAR ucConfig; //if none DVO, not defined yet 1750 }; 1751 UCHAR ucReserved[3]; 1752}ADJUST_DISPLAY_PLL_PARAMETERS; 1753 1754#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1755#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1756 1757typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1758{ 1759 USHORT usPixelClock; // target pixel clock 1760 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1761 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1762 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1763 UCHAR ucExtTransmitterID; // external encoder id. 1764 UCHAR ucReserved[2]; 1765}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1766 1767// usDispPllConfig v1.2 for RoadRunner 1768#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1769#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1770#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1771#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1772#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1773#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1774#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1775#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1776#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1777#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1778 1779 1780typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1781{ 1782 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1783 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1784 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1785 UCHAR ucReserved[2]; 1786}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1787 1788typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1789{ 1790 union 1791 { 1792 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1793 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1794 }; 1795} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1796 1797/****************************************************************************/ 1798// Structures used by EnableYUVTable 1799/****************************************************************************/ 1800typedef struct _ENABLE_YUV_PARAMETERS 1801{ 1802 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1803 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1804 UCHAR ucPadding[2]; 1805}ENABLE_YUV_PARAMETERS; 1806#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1807 1808/****************************************************************************/ 1809// Structures used by GetMemoryClockTable 1810/****************************************************************************/ 1811typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1812{ 1813 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1814} GET_MEMORY_CLOCK_PARAMETERS; 1815#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1816 1817/****************************************************************************/ 1818// Structures used by GetEngineClockTable 1819/****************************************************************************/ 1820typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1821{ 1822 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1823} GET_ENGINE_CLOCK_PARAMETERS; 1824#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1825 1826/****************************************************************************/ 1827// Following Structures and constant may be obsolete 1828/****************************************************************************/ 1829//Maxium 8 bytes,the data read in will be placed in the parameter space. 1830//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1831typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1832{ 1833 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1834 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID 1835 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1836 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1837 UCHAR ucSlaveAddr; //Read from which slave 1838 UCHAR ucLineNumber; //Read from which HW assisted line 1839}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1840#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1841 1842 1843#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1844#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1845#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1846#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1847#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1848 1849typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1850{ 1851 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1852 USHORT usByteOffset; //Write to which byte 1853 //Upper portion of usByteOffset is Format of data 1854 //1bytePS+offsetPS 1855 //2bytesPS+offsetPS 1856 //blockID+offsetPS 1857 //blockID+offsetID 1858 //blockID+counterID+offsetID 1859 UCHAR ucData; //PS data1 1860 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1861 UCHAR ucSlaveAddr; //Write to which slave 1862 UCHAR ucLineNumber; //Write from which HW assisted line 1863}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1864 1865#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1866 1867typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1868{ 1869 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1870 UCHAR ucSlaveAddr; //Write to which slave 1871 UCHAR ucLineNumber; //Write from which HW assisted line 1872}SET_UP_HW_I2C_DATA_PARAMETERS; 1873 1874 1875/**************************************************************************/ 1876#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1877 1878 1879/****************************************************************************/ 1880// Structures used by PowerConnectorDetectionTable 1881/****************************************************************************/ 1882typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1883{ 1884 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1885 UCHAR ucPwrBehaviorId; 1886 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1887}POWER_CONNECTOR_DETECTION_PARAMETERS; 1888 1889typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1890{ 1891 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1892 UCHAR ucReserved; 1893 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1894 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1895}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1896 1897/****************************LVDS SS Command Table Definitions**********************/ 1898 1899/****************************************************************************/ 1900// Structures used by EnableSpreadSpectrumOnPPLLTable 1901/****************************************************************************/ 1902typedef struct _ENABLE_LVDS_SS_PARAMETERS 1903{ 1904 USHORT usSpreadSpectrumPercentage; 1905 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1906 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1907 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1908 UCHAR ucPadding[3]; 1909}ENABLE_LVDS_SS_PARAMETERS; 1910 1911//ucTableFormatRevision=1,ucTableContentRevision=2 1912typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1913{ 1914 USHORT usSpreadSpectrumPercentage; 1915 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1916 UCHAR ucSpreadSpectrumStep; // 1917 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1918 UCHAR ucSpreadSpectrumDelay; 1919 UCHAR ucSpreadSpectrumRange; 1920 UCHAR ucPadding; 1921}ENABLE_LVDS_SS_PARAMETERS_V2; 1922 1923//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1924typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1925{ 1926 USHORT usSpreadSpectrumPercentage; 1927 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1928 UCHAR ucSpreadSpectrumStep; // 1929 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1930 UCHAR ucSpreadSpectrumDelay; 1931 UCHAR ucSpreadSpectrumRange; 1932 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1933}ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1934 1935typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1936{ 1937 USHORT usSpreadSpectrumPercentage; 1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1939 // Bit[1]: 1-Ext. 0-Int. 1940 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1941 // Bits[7:4] reserved 1942 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1943 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1944 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1945}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1946 1947#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1948#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1949#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1950#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1951#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1952#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1953#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1954#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1955#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1956#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1957#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1958 1959// Used by DCE5.0 1960 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 1961{ 1962 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1964 // Bit[1]: 1-Ext. 0-Int. 1965 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1966 // Bits[7:4] reserved 1967 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1968 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1969 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1970}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 1971 1972#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 1973#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 1974#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 1975#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 1976#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 1977#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 1978#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 1979#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 1980#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 1981#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 1982#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 1983#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 1984 1985#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1986 1987/**************************************************************************/ 1988 1989typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1990{ 1991 PIXEL_CLOCK_PARAMETERS sPCLKInput; 1992 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1993}SET_PIXEL_CLOCK_PS_ALLOCATION; 1994 1995#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1996 1997/****************************************************************************/ 1998// Structures used by ### 1999/****************************************************************************/ 2000typedef struct _MEMORY_TRAINING_PARAMETERS 2001{ 2002 ULONG ulTargetMemoryClock; //In 10Khz unit 2003}MEMORY_TRAINING_PARAMETERS; 2004#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2005 2006 2007/****************************LVDS and other encoder command table definitions **********************/ 2008 2009 2010/****************************************************************************/ 2011// Structures used by LVDSEncoderControlTable (Before DCE30) 2012// LVTMAEncoderControlTable (Before DCE30) 2013// TMDSAEncoderControlTable (Before DCE30) 2014/****************************************************************************/ 2015typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2016{ 2017 USHORT usPixelClock; // in 10KHz; for bios convenient 2018 UCHAR ucMisc; // bit0=0: Enable single link 2019 // =1: Enable dual link 2020 // Bit1=0: 666RGB 2021 // =1: 888RGB 2022 UCHAR ucAction; // 0: turn off encoder 2023 // 1: setup and turn on encoder 2024}LVDS_ENCODER_CONTROL_PARAMETERS; 2025 2026#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2027 2028#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2029#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2030 2031#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2032#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2033 2034 2035//ucTableFormatRevision=1,ucTableContentRevision=2 2036typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2037{ 2038 USHORT usPixelClock; // in 10KHz; for bios convenient 2039 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2040 UCHAR ucAction; // 0: turn off encoder 2041 // 1: setup and turn on encoder 2042 UCHAR ucTruncate; // bit0=0: Disable truncate 2043 // =1: Enable truncate 2044 // bit4=0: 666RGB 2045 // =1: 888RGB 2046 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2047 // =1: Enable spatial dithering 2048 // bit4=0: 666RGB 2049 // =1: 888RGB 2050 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2051 // =1: Enable temporal dithering 2052 // bit4=0: 666RGB 2053 // =1: 888RGB 2054 // bit5=0: Gray level 2 2055 // =1: Gray level 4 2056 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2057 // =1: 25FRC_SEL pattern F 2058 // bit6:5=0: 50FRC_SEL pattern A 2059 // =1: 50FRC_SEL pattern B 2060 // =2: 50FRC_SEL pattern C 2061 // =3: 50FRC_SEL pattern D 2062 // bit7=0: 75FRC_SEL pattern E 2063 // =1: 75FRC_SEL pattern F 2064}LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2065 2066#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2067 2068#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2069#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2070 2071#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2072#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2073 2074#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2075#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2076 2077#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2078#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2079 2080#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2081#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2082 2083/****************************************************************************/ 2084// Structures used by ### 2085/****************************************************************************/ 2086typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2087{ 2088 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2089 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2090 UCHAR ucPadding[2]; 2091}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2092 2093typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2094{ 2095 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2096 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2097}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2098 2099#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2100 2101typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2102{ 2103 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2104 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2105}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2106 2107typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2108{ 2109 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2110 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2111}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2112 2113/****************************************************************************/ 2114// Structures used by DVOEncoderControlTable 2115/****************************************************************************/ 2116//ucTableFormatRevision=1,ucTableContentRevision=3 2117 2118//ucDVOConfig: 2119#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2120#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2121#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2122#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2123#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2124#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2125#define DVO_ENCODER_CONFIG_24BIT 0x08 2126 2127typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2128{ 2129 USHORT usPixelClock; 2130 UCHAR ucDVOConfig; 2131 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2132 UCHAR ucReseved[4]; 2133}DVO_ENCODER_CONTROL_PARAMETERS_V3; 2134#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2135 2136typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2137{ 2138 USHORT usPixelClock; 2139 UCHAR ucDVOConfig; 2140 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2141 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2142 UCHAR ucReseved[3]; 2143}DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2144#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2145 2146 2147//ucTableFormatRevision=1 2148//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2149// bit1=0: non-coherent mode 2150// =1: coherent mode 2151 2152//========================================================================================== 2153//Only change is here next time when changing encoder parameter definitions again! 2154#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2155#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2156 2157#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2158#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2159 2160#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2161#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2162 2163#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2164#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2165 2166//========================================================================================== 2167#define PANEL_ENCODER_MISC_DUAL 0x01 2168#define PANEL_ENCODER_MISC_COHERENT 0x02 2169#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2170#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2171 2172#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2173#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2174#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2175 2176#define PANEL_ENCODER_TRUNCATE_EN 0x01 2177#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2178#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2179#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2180#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2181#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2182#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2183#define PANEL_ENCODER_25FRC_MASK 0x10 2184#define PANEL_ENCODER_25FRC_E 0x00 2185#define PANEL_ENCODER_25FRC_F 0x10 2186#define PANEL_ENCODER_50FRC_MASK 0x60 2187#define PANEL_ENCODER_50FRC_A 0x00 2188#define PANEL_ENCODER_50FRC_B 0x20 2189#define PANEL_ENCODER_50FRC_C 0x40 2190#define PANEL_ENCODER_50FRC_D 0x60 2191#define PANEL_ENCODER_75FRC_MASK 0x80 2192#define PANEL_ENCODER_75FRC_E 0x00 2193#define PANEL_ENCODER_75FRC_F 0x80 2194 2195/****************************************************************************/ 2196// Structures used by SetVoltageTable 2197/****************************************************************************/ 2198#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2199#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2200#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2201#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2202#define SET_VOLTAGE_INIT_MODE 5 2203#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2204 2205#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2206#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2207#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2208 2209#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2210#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2211#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2212 2213typedef struct _SET_VOLTAGE_PARAMETERS 2214{ 2215 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2216 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2217 UCHAR ucVoltageIndex; // An index to tell which voltage level 2218 UCHAR ucReserved; 2219}SET_VOLTAGE_PARAMETERS; 2220 2221typedef struct _SET_VOLTAGE_PARAMETERS_V2 2222{ 2223 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2224 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2225 USHORT usVoltageLevel; // real voltage level 2226}SET_VOLTAGE_PARAMETERS_V2; 2227 2228// used by both SetVoltageTable v1.3 and v1.4 2229typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2230{ 2231 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2232 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2233 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2234}SET_VOLTAGE_PARAMETERS_V1_3; 2235 2236//ucVoltageType 2237#define VOLTAGE_TYPE_VDDC 1 2238#define VOLTAGE_TYPE_MVDDC 2 2239#define VOLTAGE_TYPE_MVDDQ 3 2240#define VOLTAGE_TYPE_VDDCI 4 2241 2242//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2243#define ATOM_SET_VOLTAGE 0 //Set voltage Level 2244#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2245#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2246#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2247#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2248#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2249 2250// define vitual voltage id in usVoltageLevel 2251#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2252#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2253#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2254#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2255#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2256#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2257#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2258#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2259 2260typedef struct _SET_VOLTAGE_PS_ALLOCATION 2261{ 2262 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2263 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2264}SET_VOLTAGE_PS_ALLOCATION; 2265 2266// New Added from SI for GetVoltageInfoTable, input parameter structure 2267typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2268{ 2269 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2270 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2271 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2272 ULONG ulReserved; 2273}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2274 2275// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2276typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2277{ 2278 ULONG ulVotlageGpioState; 2279 ULONG ulVoltageGPioMask; 2280}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2281 2282// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2283typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2284{ 2285 USHORT usVoltageLevel; 2286 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2287 ULONG ulReseved; 2288}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2289 2290 2291// GetVoltageInfo v1.1 ucVoltageMode 2292#define ATOM_GET_VOLTAGE_VID 0x00 2293#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2294#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2295#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2296 2297// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2298#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2299// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2300#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2301 2302#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2303#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2304 2305// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2306typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2307{ 2308 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2309 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2310 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2311 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2312}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2313 2314// New in GetVoltageInfo v1.2 ucVoltageMode 2315#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2316 2317// New Added from CI Hawaii for EVV feature 2318typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2319{ 2320 USHORT usVoltageLevel; // real voltage level in unit of mv 2321 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2322 ULONG ulReseved; 2323}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2324 2325/****************************************************************************/ 2326// Structures used by TVEncoderControlTable 2327/****************************************************************************/ 2328typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2329{ 2330 USHORT usPixelClock; // in 10KHz; for bios convenient 2331 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2332 UCHAR ucAction; // 0: turn off encoder 2333 // 1: setup and turn on encoder 2334}TV_ENCODER_CONTROL_PARAMETERS; 2335 2336typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2337{ 2338 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2339 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2340}TV_ENCODER_CONTROL_PS_ALLOCATION; 2341 2342//==============================Data Table Portion==================================== 2343 2344/****************************************************************************/ 2345// Structure used in Data.mtb 2346/****************************************************************************/ 2347typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2348{ 2349 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2350 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2351 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2352 USHORT StandardVESA_Timing; // Only used by Bios 2353 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2354 USHORT PaletteData; // Only used by BIOS 2355 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2356 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2357 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2358 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2359 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2360 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2361 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2362 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2363 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2364 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2365 USHORT CompassionateData; // Will be obsolete from R600 2366 USHORT SaveRestoreInfo; // Only used by Bios 2367 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2368 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2369 USHORT XTMDS_Info; // Will be obsolete from R600 2370 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2371 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2372 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2373 USHORT MC_InitParameter; // Only used by command table 2374 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2375 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2376 USHORT TV_VideoMode; // Only used by command table 2377 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2378 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2379 USHORT IntegratedSystemInfo; // Shared by various SW components 2380 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2381 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2382 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2383}ATOM_MASTER_LIST_OF_DATA_TABLES; 2384 2385typedef struct _ATOM_MASTER_DATA_TABLE 2386{ 2387 ATOM_COMMON_TABLE_HEADER sHeader; 2388 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2389}ATOM_MASTER_DATA_TABLE; 2390 2391// For backward compatible 2392#define LVDS_Info LCD_Info 2393#define DAC_Info PaletteData 2394#define TMDS_Info DIGTransmitterInfo 2395 2396/****************************************************************************/ 2397// Structure used in MultimediaCapabilityInfoTable 2398/****************************************************************************/ 2399typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2400{ 2401 ATOM_COMMON_TABLE_HEADER sHeader; 2402 ULONG ulSignature; // HW info table signature string "$ATI" 2403 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2404 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2405 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2406 UCHAR ucHostPortInfo; // Provides host port configuration information 2407}ATOM_MULTIMEDIA_CAPABILITY_INFO; 2408 2409/****************************************************************************/ 2410// Structure used in MultimediaConfigInfoTable 2411/****************************************************************************/ 2412typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2413{ 2414 ATOM_COMMON_TABLE_HEADER sHeader; 2415 ULONG ulSignature; // MM info table signature sting "$MMT" 2416 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2417 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2418 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2419 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2420 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2421 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2422 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2423 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2424 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2425 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2426 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2427 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2428}ATOM_MULTIMEDIA_CONFIG_INFO; 2429 2430 2431/****************************************************************************/ 2432// Structures used in FirmwareInfoTable 2433/****************************************************************************/ 2434 2435// usBIOSCapability Definition: 2436// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2437// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2438// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2439// Others: Reserved 2440#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2441#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2442#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2443#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2444#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2445#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2446#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2447#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2448#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2449#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2450#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2451#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2452#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2453#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2454 2455#ifndef _H2INC 2456 2457//Please don't add or expand this bitfield structure below, this one will retire soon.! 2458typedef struct _ATOM_FIRMWARE_CAPABILITY 2459{ 2460#if ATOM_BIG_ENDIAN 2461 USHORT Reserved:1; 2462 USHORT SCL2Redefined:1; 2463 USHORT PostWithoutModeSet:1; 2464 USHORT HyperMemory_Size:4; 2465 USHORT HyperMemory_Support:1; 2466 USHORT PPMode_Assigned:1; 2467 USHORT WMI_SUPPORT:1; 2468 USHORT GPUControlsBL:1; 2469 USHORT EngineClockSS_Support:1; 2470 USHORT MemoryClockSS_Support:1; 2471 USHORT ExtendedDesktopSupport:1; 2472 USHORT DualCRTC_Support:1; 2473 USHORT FirmwarePosted:1; 2474#else 2475 USHORT FirmwarePosted:1; 2476 USHORT DualCRTC_Support:1; 2477 USHORT ExtendedDesktopSupport:1; 2478 USHORT MemoryClockSS_Support:1; 2479 USHORT EngineClockSS_Support:1; 2480 USHORT GPUControlsBL:1; 2481 USHORT WMI_SUPPORT:1; 2482 USHORT PPMode_Assigned:1; 2483 USHORT HyperMemory_Support:1; 2484 USHORT HyperMemory_Size:4; 2485 USHORT PostWithoutModeSet:1; 2486 USHORT SCL2Redefined:1; 2487 USHORT Reserved:1; 2488#endif 2489}ATOM_FIRMWARE_CAPABILITY; 2490 2491typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2492{ 2493 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2494 USHORT susAccess; 2495}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2496 2497#else 2498 2499typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2500{ 2501 USHORT susAccess; 2502}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2503 2504#endif 2505 2506typedef struct _ATOM_FIRMWARE_INFO 2507{ 2508 ATOM_COMMON_TABLE_HEADER sHeader; 2509 ULONG ulFirmwareRevision; 2510 ULONG ulDefaultEngineClock; //In 10Khz unit 2511 ULONG ulDefaultMemoryClock; //In 10Khz unit 2512 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2513 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2514 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2515 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2516 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2517 ULONG ulASICMaxEngineClock; //In 10Khz unit 2518 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2519 UCHAR ucASICMaxTemperature; 2520 UCHAR ucPadding[3]; //Don't use them 2521 ULONG aulReservedForBIOS[3]; //Don't use them 2522 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2523 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2524 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2525 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2526 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2527 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2528 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2529 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2530 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2531 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2532 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2533 USHORT usReferenceClock; //In 10Khz unit 2534 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2535 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2536 UCHAR ucDesign_ID; //Indicate what is the board design 2537 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2538}ATOM_FIRMWARE_INFO; 2539 2540typedef struct _ATOM_FIRMWARE_INFO_V1_2 2541{ 2542 ATOM_COMMON_TABLE_HEADER sHeader; 2543 ULONG ulFirmwareRevision; 2544 ULONG ulDefaultEngineClock; //In 10Khz unit 2545 ULONG ulDefaultMemoryClock; //In 10Khz unit 2546 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2547 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2548 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2549 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2550 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2551 ULONG ulASICMaxEngineClock; //In 10Khz unit 2552 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2553 UCHAR ucASICMaxTemperature; 2554 UCHAR ucMinAllowedBL_Level; 2555 UCHAR ucPadding[2]; //Don't use them 2556 ULONG aulReservedForBIOS[2]; //Don't use them 2557 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2558 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2559 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2560 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2561 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2562 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2563 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2564 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2565 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2566 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2567 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2568 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2569 USHORT usReferenceClock; //In 10Khz unit 2570 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2571 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2572 UCHAR ucDesign_ID; //Indicate what is the board design 2573 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2574}ATOM_FIRMWARE_INFO_V1_2; 2575 2576typedef struct _ATOM_FIRMWARE_INFO_V1_3 2577{ 2578 ATOM_COMMON_TABLE_HEADER sHeader; 2579 ULONG ulFirmwareRevision; 2580 ULONG ulDefaultEngineClock; //In 10Khz unit 2581 ULONG ulDefaultMemoryClock; //In 10Khz unit 2582 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2583 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2584 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2585 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2586 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2587 ULONG ulASICMaxEngineClock; //In 10Khz unit 2588 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2589 UCHAR ucASICMaxTemperature; 2590 UCHAR ucMinAllowedBL_Level; 2591 UCHAR ucPadding[2]; //Don't use them 2592 ULONG aulReservedForBIOS; //Don't use them 2593 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2594 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2595 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2596 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2597 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2598 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2599 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2600 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2601 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2602 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2603 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2604 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2605 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2606 USHORT usReferenceClock; //In 10Khz unit 2607 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2608 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2609 UCHAR ucDesign_ID; //Indicate what is the board design 2610 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2611}ATOM_FIRMWARE_INFO_V1_3; 2612 2613typedef struct _ATOM_FIRMWARE_INFO_V1_4 2614{ 2615 ATOM_COMMON_TABLE_HEADER sHeader; 2616 ULONG ulFirmwareRevision; 2617 ULONG ulDefaultEngineClock; //In 10Khz unit 2618 ULONG ulDefaultMemoryClock; //In 10Khz unit 2619 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2620 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2621 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2622 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2623 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2624 ULONG ulASICMaxEngineClock; //In 10Khz unit 2625 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2626 UCHAR ucASICMaxTemperature; 2627 UCHAR ucMinAllowedBL_Level; 2628 USHORT usBootUpVDDCVoltage; //In MV unit 2629 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2630 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2631 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2632 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2633 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2634 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2635 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2636 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2637 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2638 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2639 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2640 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2641 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2642 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2643 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2644 USHORT usReferenceClock; //In 10Khz unit 2645 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2646 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2647 UCHAR ucDesign_ID; //Indicate what is the board design 2648 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2649}ATOM_FIRMWARE_INFO_V1_4; 2650 2651//the structure below to be used from Cypress 2652typedef struct _ATOM_FIRMWARE_INFO_V2_1 2653{ 2654 ATOM_COMMON_TABLE_HEADER sHeader; 2655 ULONG ulFirmwareRevision; 2656 ULONG ulDefaultEngineClock; //In 10Khz unit 2657 ULONG ulDefaultMemoryClock; //In 10Khz unit 2658 ULONG ulReserved1; 2659 ULONG ulReserved2; 2660 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2661 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2662 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2663 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2664 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2665 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2666 UCHAR ucMinAllowedBL_Level; 2667 USHORT usBootUpVDDCVoltage; //In MV unit 2668 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2669 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2670 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2671 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2672 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2673 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2674 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2675 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2676 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2677 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2678 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2679 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2680 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2681 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2682 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2683 USHORT usCoreReferenceClock; //In 10Khz unit 2684 USHORT usMemoryReferenceClock; //In 10Khz unit 2685 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2686 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2687 UCHAR ucReserved4[3]; 2688}ATOM_FIRMWARE_INFO_V2_1; 2689 2690//the structure below to be used from NI 2691//ucTableFormatRevision=2 2692//ucTableContentRevision=2 2693typedef struct _ATOM_FIRMWARE_INFO_V2_2 2694{ 2695 ATOM_COMMON_TABLE_HEADER sHeader; 2696 ULONG ulFirmwareRevision; 2697 ULONG ulDefaultEngineClock; //In 10Khz unit 2698 ULONG ulDefaultMemoryClock; //In 10Khz unit 2699 ULONG ulSPLL_OutputFreq; //In 10Khz unit 2700 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 2701 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2702 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2703 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2704 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2705 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2706 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2707 UCHAR ucMinAllowedBL_Level; 2708 USHORT usBootUpVDDCVoltage; //In MV unit 2709 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2710 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2711 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2712 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2713 UCHAR ucRemoteDisplayConfig; 2714 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2715 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2716 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2717 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2718 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2719 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2720 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2721 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2722 USHORT usCoreReferenceClock; //In 10Khz unit 2723 USHORT usMemoryReferenceClock; //In 10Khz unit 2724 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2725 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2726 UCHAR ucReserved9[3]; 2727 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2728 USHORT usReserved12; 2729 ULONG ulReserved10[3]; // New added comparing to previous version 2730}ATOM_FIRMWARE_INFO_V2_2; 2731 2732#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2733 2734 2735// definition of ucRemoteDisplayConfig 2736#define REMOTE_DISPLAY_DISABLE 0x00 2737#define REMOTE_DISPLAY_ENABLE 0x01 2738 2739/****************************************************************************/ 2740// Structures used in IntegratedSystemInfoTable 2741/****************************************************************************/ 2742#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2743#define IGP_CAP_FLAG_AC_CARD 0x4 2744#define IGP_CAP_FLAG_SDVO_CARD 0x8 2745#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2746 2747typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2748{ 2749 ATOM_COMMON_TABLE_HEADER sHeader; 2750 ULONG ulBootUpEngineClock; //in 10kHz unit 2751 ULONG ulBootUpMemoryClock; //in 10kHz unit 2752 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2753 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2754 UCHAR ucNumberOfCyclesInPeriodHi; 2755 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2756 USHORT usReserved1; 2757 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2758 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2759 ULONG ulReserved[2]; 2760 2761 USHORT usFSBClock; //In MHz unit 2762 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2763 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2764 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2765 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2766 USHORT usK8MemoryClock; //in MHz unit 2767 USHORT usK8SyncStartDelay; //in 0.01 us unit 2768 USHORT usK8DataReturnTime; //in 0.01 us unit 2769 UCHAR ucMaxNBVoltage; 2770 UCHAR ucMinNBVoltage; 2771 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2772 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2773 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2774 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2775 UCHAR ucMaxNBVoltageHigh; 2776 UCHAR ucMinNBVoltageHigh; 2777}ATOM_INTEGRATED_SYSTEM_INFO; 2778 2779/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2780ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2781 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2782ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2783 For AMD IGP,for now this can be 0 2784ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2785 For AMD IGP,for now this can be 0 2786 2787usFSBClock: For Intel IGP,it's FSB Freq 2788 For AMD IGP,it's HT Link Speed 2789 2790usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2791usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2792usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2793 2794VC:Voltage Control 2795ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2796ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2797 2798ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2799ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2800 2801ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2802ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2803 2804 2805usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2806usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2807*/ 2808 2809 2810/* 2811The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2812Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2813The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2814 2815SW components can access the IGP system infor structure in the same way as before 2816*/ 2817 2818 2819typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2820{ 2821 ATOM_COMMON_TABLE_HEADER sHeader; 2822 ULONG ulBootUpEngineClock; //in 10kHz unit 2823 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2824 ULONG ulBootUpUMAClock; //in 10kHz unit 2825 ULONG ulBootUpSidePortClock; //in 10kHz unit 2826 ULONG ulMinSidePortClock; //in 10kHz unit 2827 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2828 ULONG ulSystemConfig; //see explanation below 2829 ULONG ulBootUpReqDisplayVector; 2830 ULONG ulOtherDisplayMisc; 2831 ULONG ulDDISlot1Config; 2832 ULONG ulDDISlot2Config; 2833 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2834 UCHAR ucUMAChannelNumber; 2835 UCHAR ucDockingPinBit; 2836 UCHAR ucDockingPinPolarity; 2837 ULONG ulDockingPinCFGInfo; 2838 ULONG ulCPUCapInfo; 2839 USHORT usNumberOfCyclesInPeriod; 2840 USHORT usMaxNBVoltage; 2841 USHORT usMinNBVoltage; 2842 USHORT usBootUpNBVoltage; 2843 ULONG ulHTLinkFreq; //in 10Khz 2844 USHORT usMinHTLinkWidth; 2845 USHORT usMaxHTLinkWidth; 2846 USHORT usUMASyncStartDelay; 2847 USHORT usUMADataReturnTime; 2848 USHORT usLinkStatusZeroTime; 2849 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2850 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2851 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2852 USHORT usMaxUpStreamHTLinkWidth; 2853 USHORT usMaxDownStreamHTLinkWidth; 2854 USHORT usMinUpStreamHTLinkWidth; 2855 USHORT usMinDownStreamHTLinkWidth; 2856 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2857 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2858 ULONG ulReserved3[96]; //must be 0x0 2859}ATOM_INTEGRATED_SYSTEM_INFO_V2; 2860 2861/* 2862ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2863ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2864ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2865 2866ulSystemConfig: 2867Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2868Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2869 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2870Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2871Bit[3]=1: Only one power state(Performance) will be supported. 2872 =0: Multiple power states supported from PowerPlay table. 2873Bit[4]=1: CLMC is supported and enabled on current system. 2874 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2875Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2876 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2877Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2878 =0: Voltage settings is determined by powerplay table. 2879Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2880 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2881Bit[8]=1: CDLF is supported and enabled on current system. 2882 =0: CDLF is not supported or enabled on current system. 2883Bit[9]=1: DLL Shut Down feature is enabled on current system. 2884 =0: DLL Shut Down feature is not enabled or supported on current system. 2885 2886ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2887 2888ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2889 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; 2890 2891ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2892 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2893 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2894 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2895 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2896 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2897 2898 [15:8] - Lane configuration attribute; 2899 [23:16]- Connector type, possible value: 2900 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2901 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2902 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2903 CONNECTOR_OBJECT_ID_DISPLAYPORT 2904 CONNECTOR_OBJECT_ID_eDP 2905 [31:24]- Reserved 2906 2907ulDDISlot2Config: Same as Slot1. 2908ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2909For IGP, Hypermemory is the only memory type showed in CCC. 2910 2911ucUMAChannelNumber: how many channels for the UMA; 2912 2913ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2914ucDockingPinBit: which bit in this register to read the pin status; 2915ucDockingPinPolarity:Polarity of the pin when docked; 2916 2917ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 2918 2919usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2920 2921usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 2922usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 2923 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 2924 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 2925 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 2926 2927usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 2928 2929ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 2930usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 2931 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2932usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 2933 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2934 2935usUMASyncStartDelay: Memory access latency, required for watermark calculation 2936usUMADataReturnTime: Memory access latency, required for watermark calculation 2937usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 2938for Griffin or Greyhound. SBIOS needs to convert to actual time by: 2939 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 2940 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 2941 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 2942 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 2943 2944ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 2945 This must be less than or equal to ulHTLinkFreq(bootup frequency). 2946ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 2947 This must be less than or equal to ulHighVoltageHTLinkFreq. 2948 2949usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 2950usMaxDownStreamHTLinkWidth: same as above. 2951usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 2952usMinDownStreamHTLinkWidth: same as above. 2953*/ 2954 2955// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 2956#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 2957#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 2958#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 2959#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 2960#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 2961#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 2962 2963#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 2964 2965#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2966#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2967#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2968#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2969#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2970#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2971#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2972#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2973#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2974#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2975 2976#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2977 2978#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2979#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2980#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2981#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2982#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2983#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2984 2985#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2986#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2987#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2988 2989#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2990 2991// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2992typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2993{ 2994 ATOM_COMMON_TABLE_HEADER sHeader; 2995 ULONG ulBootUpEngineClock; //in 10kHz unit 2996 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2997 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 2998 ULONG ulBootUpUMAClock; //in 10kHz unit 2999 ULONG ulReserved1[8]; //must be 0x0 for the reserved 3000 ULONG ulBootUpReqDisplayVector; 3001 ULONG ulOtherDisplayMisc; 3002 ULONG ulReserved2[4]; //must be 0x0 for the reserved 3003 ULONG ulSystemConfig; //TBD 3004 ULONG ulCPUCapInfo; //TBD 3005 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3006 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3007 USHORT usBootUpNBVoltage; //boot up NB voltage 3008 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3009 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3010 ULONG ulReserved3[4]; //must be 0x0 for the reserved 3011 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3012 ULONG ulDDISlot2Config; 3013 ULONG ulDDISlot3Config; 3014 ULONG ulDDISlot4Config; 3015 ULONG ulReserved4[4]; //must be 0x0 for the reserved 3016 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3017 UCHAR ucUMAChannelNumber; 3018 USHORT usReserved; 3019 ULONG ulReserved5[4]; //must be 0x0 for the reserved 3020 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3021 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3022 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3023 ULONG ulReserved6[61]; //must be 0x0 3024}ATOM_INTEGRATED_SYSTEM_INFO_V5; 3025 3026#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3027#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3028#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3029#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3030#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3031#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3032#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3033#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3034#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3035#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3036#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3037#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3038#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3039#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3040 3041// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3042#define ASIC_INT_DAC1_ENCODER_ID 0x00 3043#define ASIC_INT_TV_ENCODER_ID 0x02 3044#define ASIC_INT_DIG1_ENCODER_ID 0x03 3045#define ASIC_INT_DAC2_ENCODER_ID 0x04 3046#define ASIC_EXT_TV_ENCODER_ID 0x06 3047#define ASIC_INT_DVO_ENCODER_ID 0x07 3048#define ASIC_INT_DIG2_ENCODER_ID 0x09 3049#define ASIC_EXT_DIG_ENCODER_ID 0x05 3050#define ASIC_EXT_DIG2_ENCODER_ID 0x08 3051#define ASIC_INT_DIG3_ENCODER_ID 0x0a 3052#define ASIC_INT_DIG4_ENCODER_ID 0x0b 3053#define ASIC_INT_DIG5_ENCODER_ID 0x0c 3054#define ASIC_INT_DIG6_ENCODER_ID 0x0d 3055#define ASIC_INT_DIG7_ENCODER_ID 0x0e 3056 3057//define Encoder attribute 3058#define ATOM_ANALOG_ENCODER 0 3059#define ATOM_DIGITAL_ENCODER 1 3060#define ATOM_DP_ENCODER 2 3061 3062#define ATOM_ENCODER_ENUM_MASK 0x70 3063#define ATOM_ENCODER_ENUM_ID1 0x00 3064#define ATOM_ENCODER_ENUM_ID2 0x10 3065#define ATOM_ENCODER_ENUM_ID3 0x20 3066#define ATOM_ENCODER_ENUM_ID4 0x30 3067#define ATOM_ENCODER_ENUM_ID5 0x40 3068#define ATOM_ENCODER_ENUM_ID6 0x50 3069 3070#define ATOM_DEVICE_CRT1_INDEX 0x00000000 3071#define ATOM_DEVICE_LCD1_INDEX 0x00000001 3072#define ATOM_DEVICE_TV1_INDEX 0x00000002 3073#define ATOM_DEVICE_DFP1_INDEX 0x00000003 3074#define ATOM_DEVICE_CRT2_INDEX 0x00000004 3075#define ATOM_DEVICE_LCD2_INDEX 0x00000005 3076#define ATOM_DEVICE_DFP6_INDEX 0x00000006 3077#define ATOM_DEVICE_DFP2_INDEX 0x00000007 3078#define ATOM_DEVICE_CV_INDEX 0x00000008 3079#define ATOM_DEVICE_DFP3_INDEX 0x00000009 3080#define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3081#define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3082 3083#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3084#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3085#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3086#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3087#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3088#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3089#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3090 3091#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3092 3093#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3094#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3095#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3096#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3097#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3098#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3099#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3100#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3101#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3102#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3103#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3104#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3105 3106#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3107#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3108#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 3109#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3110 3111#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3112#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3113#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3114#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3115#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3116#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3117#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3118#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3119#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3120#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3121#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3122#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3123#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3124#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3125#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3126 3127 3128#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3129#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3130#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3131#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3132#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3133#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3134 3135#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3136 3137#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3138#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3139 3140#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3141#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3142#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3143#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3144#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3145#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3146 3147#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3148#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3149#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3150#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3151 3152// usDeviceSupport: 3153// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3154// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3155// Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3156// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3157// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3158// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3159// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3160// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3161// Bit 8 = 0 - no CV support= 1- CV is supported 3162// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3163// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 3164// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 3165// 3166// 3167 3168/****************************************************************************/ 3169/* Structure used in MclkSS_InfoTable */ 3170/****************************************************************************/ 3171// ucI2C_ConfigID 3172// [7:0] - I2C LINE Associate ID 3173// = 0 - no I2C 3174// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3175// = 0, [6:0]=SW assisted I2C ID 3176// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3177// = 2, HW engine for Multimedia use 3178// = 3-7 Reserved for future I2C engines 3179// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3180 3181typedef struct _ATOM_I2C_ID_CONFIG 3182{ 3183#if ATOM_BIG_ENDIAN 3184 UCHAR bfHW_Capable:1; 3185 UCHAR bfHW_EngineID:3; 3186 UCHAR bfI2C_LineMux:4; 3187#else 3188 UCHAR bfI2C_LineMux:4; 3189 UCHAR bfHW_EngineID:3; 3190 UCHAR bfHW_Capable:1; 3191#endif 3192}ATOM_I2C_ID_CONFIG; 3193 3194typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3195{ 3196 ATOM_I2C_ID_CONFIG sbfAccess; 3197 UCHAR ucAccess; 3198}ATOM_I2C_ID_CONFIG_ACCESS; 3199 3200 3201/****************************************************************************/ 3202// Structure used in GPIO_I2C_InfoTable 3203/****************************************************************************/ 3204typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3205{ 3206 USHORT usClkMaskRegisterIndex; 3207 USHORT usClkEnRegisterIndex; 3208 USHORT usClkY_RegisterIndex; 3209 USHORT usClkA_RegisterIndex; 3210 USHORT usDataMaskRegisterIndex; 3211 USHORT usDataEnRegisterIndex; 3212 USHORT usDataY_RegisterIndex; 3213 USHORT usDataA_RegisterIndex; 3214 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3215 UCHAR ucClkMaskShift; 3216 UCHAR ucClkEnShift; 3217 UCHAR ucClkY_Shift; 3218 UCHAR ucClkA_Shift; 3219 UCHAR ucDataMaskShift; 3220 UCHAR ucDataEnShift; 3221 UCHAR ucDataY_Shift; 3222 UCHAR ucDataA_Shift; 3223 UCHAR ucReserved1; 3224 UCHAR ucReserved2; 3225}ATOM_GPIO_I2C_ASSIGMENT; 3226 3227typedef struct _ATOM_GPIO_I2C_INFO 3228{ 3229 ATOM_COMMON_TABLE_HEADER sHeader; 3230 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3231}ATOM_GPIO_I2C_INFO; 3232 3233/****************************************************************************/ 3234// Common Structure used in other structures 3235/****************************************************************************/ 3236 3237#ifndef _H2INC 3238 3239//Please don't add or expand this bitfield structure below, this one will retire soon.! 3240typedef struct _ATOM_MODE_MISC_INFO 3241{ 3242#if ATOM_BIG_ENDIAN 3243 USHORT Reserved:6; 3244 USHORT RGB888:1; 3245 USHORT DoubleClock:1; 3246 USHORT Interlace:1; 3247 USHORT CompositeSync:1; 3248 USHORT V_ReplicationBy2:1; 3249 USHORT H_ReplicationBy2:1; 3250 USHORT VerticalCutOff:1; 3251 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3252 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3253 USHORT HorizontalCutOff:1; 3254#else 3255 USHORT HorizontalCutOff:1; 3256 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3257 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3258 USHORT VerticalCutOff:1; 3259 USHORT H_ReplicationBy2:1; 3260 USHORT V_ReplicationBy2:1; 3261 USHORT CompositeSync:1; 3262 USHORT Interlace:1; 3263 USHORT DoubleClock:1; 3264 USHORT RGB888:1; 3265 USHORT Reserved:6; 3266#endif 3267}ATOM_MODE_MISC_INFO; 3268 3269typedef union _ATOM_MODE_MISC_INFO_ACCESS 3270{ 3271 ATOM_MODE_MISC_INFO sbfAccess; 3272 USHORT usAccess; 3273}ATOM_MODE_MISC_INFO_ACCESS; 3274 3275#else 3276 3277typedef union _ATOM_MODE_MISC_INFO_ACCESS 3278{ 3279 USHORT usAccess; 3280}ATOM_MODE_MISC_INFO_ACCESS; 3281 3282#endif 3283 3284// usModeMiscInfo- 3285#define ATOM_H_CUTOFF 0x01 3286#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3287#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3288#define ATOM_V_CUTOFF 0x08 3289#define ATOM_H_REPLICATIONBY2 0x10 3290#define ATOM_V_REPLICATIONBY2 0x20 3291#define ATOM_COMPOSITESYNC 0x40 3292#define ATOM_INTERLACE 0x80 3293#define ATOM_DOUBLE_CLOCK_MODE 0x100 3294#define ATOM_RGB888_MODE 0x200 3295 3296//usRefreshRate- 3297#define ATOM_REFRESH_43 43 3298#define ATOM_REFRESH_47 47 3299#define ATOM_REFRESH_56 56 3300#define ATOM_REFRESH_60 60 3301#define ATOM_REFRESH_65 65 3302#define ATOM_REFRESH_70 70 3303#define ATOM_REFRESH_72 72 3304#define ATOM_REFRESH_75 75 3305#define ATOM_REFRESH_85 85 3306 3307// ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3308// Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3309// 3310// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3311// = EDID_HA + EDID_HBL 3312// VESA_HDISP = VESA_ACTIVE = EDID_HA 3313// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3314// = EDID_HA + EDID_HSO 3315// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3316// VESA_BORDER = EDID_BORDER 3317 3318/****************************************************************************/ 3319// Structure used in SetCRTC_UsingDTDTimingTable 3320/****************************************************************************/ 3321typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3322{ 3323 USHORT usH_Size; 3324 USHORT usH_Blanking_Time; 3325 USHORT usV_Size; 3326 USHORT usV_Blanking_Time; 3327 USHORT usH_SyncOffset; 3328 USHORT usH_SyncWidth; 3329 USHORT usV_SyncOffset; 3330 USHORT usV_SyncWidth; 3331 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3332 UCHAR ucH_Border; // From DFP EDID 3333 UCHAR ucV_Border; 3334 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3335 UCHAR ucPadding[3]; 3336}SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3337 3338/****************************************************************************/ 3339// Structure used in SetCRTC_TimingTable 3340/****************************************************************************/ 3341typedef struct _SET_CRTC_TIMING_PARAMETERS 3342{ 3343 USHORT usH_Total; // horizontal total 3344 USHORT usH_Disp; // horizontal display 3345 USHORT usH_SyncStart; // horozontal Sync start 3346 USHORT usH_SyncWidth; // horizontal Sync width 3347 USHORT usV_Total; // vertical total 3348 USHORT usV_Disp; // vertical display 3349 USHORT usV_SyncStart; // vertical Sync start 3350 USHORT usV_SyncWidth; // vertical Sync width 3351 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3352 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3353 UCHAR ucOverscanRight; // right 3354 UCHAR ucOverscanLeft; // left 3355 UCHAR ucOverscanBottom; // bottom 3356 UCHAR ucOverscanTop; // top 3357 UCHAR ucReserved; 3358}SET_CRTC_TIMING_PARAMETERS; 3359#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3360 3361/****************************************************************************/ 3362// Structure used in StandardVESA_TimingTable 3363// AnalogTV_InfoTable 3364// ComponentVideoInfoTable 3365/****************************************************************************/ 3366typedef struct _ATOM_MODE_TIMING 3367{ 3368 USHORT usCRTC_H_Total; 3369 USHORT usCRTC_H_Disp; 3370 USHORT usCRTC_H_SyncStart; 3371 USHORT usCRTC_H_SyncWidth; 3372 USHORT usCRTC_V_Total; 3373 USHORT usCRTC_V_Disp; 3374 USHORT usCRTC_V_SyncStart; 3375 USHORT usCRTC_V_SyncWidth; 3376 USHORT usPixelClock; //in 10Khz unit 3377 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3378 USHORT usCRTC_OverscanRight; 3379 USHORT usCRTC_OverscanLeft; 3380 USHORT usCRTC_OverscanBottom; 3381 USHORT usCRTC_OverscanTop; 3382 USHORT usReserve; 3383 UCHAR ucInternalModeNumber; 3384 UCHAR ucRefreshRate; 3385}ATOM_MODE_TIMING; 3386 3387typedef struct _ATOM_DTD_FORMAT 3388{ 3389 USHORT usPixClk; 3390 USHORT usHActive; 3391 USHORT usHBlanking_Time; 3392 USHORT usVActive; 3393 USHORT usVBlanking_Time; 3394 USHORT usHSyncOffset; 3395 USHORT usHSyncWidth; 3396 USHORT usVSyncOffset; 3397 USHORT usVSyncWidth; 3398 USHORT usImageHSize; 3399 USHORT usImageVSize; 3400 UCHAR ucHBorder; 3401 UCHAR ucVBorder; 3402 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3403 UCHAR ucInternalModeNumber; 3404 UCHAR ucRefreshRate; 3405}ATOM_DTD_FORMAT; 3406 3407/****************************************************************************/ 3408// Structure used in LVDS_InfoTable 3409// * Need a document to describe this table 3410/****************************************************************************/ 3411#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3412#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3413#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3414#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3415 3416//ucTableFormatRevision=1 3417//ucTableContentRevision=1 3418typedef struct _ATOM_LVDS_INFO 3419{ 3420 ATOM_COMMON_TABLE_HEADER sHeader; 3421 ATOM_DTD_FORMAT sLCDTiming; 3422 USHORT usModePatchTableOffset; 3423 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3424 USHORT usOffDelayInMs; 3425 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3426 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3427 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3428 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3429 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3430 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3431 UCHAR ucPanelDefaultRefreshRate; 3432 UCHAR ucPanelIdentification; 3433 UCHAR ucSS_Id; 3434}ATOM_LVDS_INFO; 3435 3436//ucTableFormatRevision=1 3437//ucTableContentRevision=2 3438typedef struct _ATOM_LVDS_INFO_V12 3439{ 3440 ATOM_COMMON_TABLE_HEADER sHeader; 3441 ATOM_DTD_FORMAT sLCDTiming; 3442 USHORT usExtInfoTableOffset; 3443 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3444 USHORT usOffDelayInMs; 3445 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3446 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3447 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3448 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3449 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3450 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3451 UCHAR ucPanelDefaultRefreshRate; 3452 UCHAR ucPanelIdentification; 3453 UCHAR ucSS_Id; 3454 USHORT usLCDVenderID; 3455 USHORT usLCDProductID; 3456 UCHAR ucLCDPanel_SpecialHandlingCap; 3457 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3458 UCHAR ucReserved[2]; 3459}ATOM_LVDS_INFO_V12; 3460 3461//Definitions for ucLCDPanel_SpecialHandlingCap: 3462 3463//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3464//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3465#define LCDPANEL_CAP_READ_EDID 0x1 3466 3467//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3468//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3469//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3470#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3471 3472//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3473#define LCDPANEL_CAP_eDP 0x4 3474 3475 3476//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3477//Bit 6 5 4 3478 // 0 0 0 - Color bit depth is undefined 3479 // 0 0 1 - 6 Bits per Primary Color 3480 // 0 1 0 - 8 Bits per Primary Color 3481 // 0 1 1 - 10 Bits per Primary Color 3482 // 1 0 0 - 12 Bits per Primary Color 3483 // 1 0 1 - 14 Bits per Primary Color 3484 // 1 1 0 - 16 Bits per Primary Color 3485 // 1 1 1 - Reserved 3486 3487#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3488 3489// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3490#define PANEL_RANDOM_DITHER 0x80 3491#define PANEL_RANDOM_DITHER_MASK 0x80 3492 3493#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3494 3495/****************************************************************************/ 3496// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3497// ASIC Families: NI 3498// ucTableFormatRevision=1 3499// ucTableContentRevision=3 3500/****************************************************************************/ 3501typedef struct _ATOM_LCD_INFO_V13 3502{ 3503 ATOM_COMMON_TABLE_HEADER sHeader; 3504 ATOM_DTD_FORMAT sLCDTiming; 3505 USHORT usExtInfoTableOffset; 3506 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3507 ULONG ulReserved0; 3508 UCHAR ucLCD_Misc; // Reorganized in V13 3509 // Bit0: {=0:single, =1:dual}, 3510 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3511 // Bit3:2: {Grey level} 3512 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3513 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3514 UCHAR ucPanelDefaultRefreshRate; 3515 UCHAR ucPanelIdentification; 3516 UCHAR ucSS_Id; 3517 USHORT usLCDVenderID; 3518 USHORT usLCDProductID; 3519 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3520 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3521 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3522 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3523 // Bit7-3: Reserved 3524 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3525 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3526 3527 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3528 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3529 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3530 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3531 3532 UCHAR ucOffDelay_in4Ms; 3533 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3534 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3535 UCHAR ucReserved1; 3536 3537 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3538 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3539 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3540 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3541 3542 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3543 UCHAR uceDPToLVDSRxId; 3544 UCHAR ucLcdReservd; 3545 ULONG ulReserved[2]; 3546}ATOM_LCD_INFO_V13; 3547 3548#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3549 3550//Definitions for ucLCD_Misc 3551#define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3552#define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3553#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3554#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3555#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3556#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3557#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3558 3559//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3560//Bit 6 5 4 3561 // 0 0 0 - Color bit depth is undefined 3562 // 0 0 1 - 6 Bits per Primary Color 3563 // 0 1 0 - 8 Bits per Primary Color 3564 // 0 1 1 - 10 Bits per Primary Color 3565 // 1 0 0 - 12 Bits per Primary Color 3566 // 1 0 1 - 14 Bits per Primary Color 3567 // 1 1 0 - 16 Bits per Primary Color 3568 // 1 1 1 - Reserved 3569 3570//Definitions for ucLCDPanel_SpecialHandlingCap: 3571 3572//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3573//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3574#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3575 3576//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3577//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3578//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3579#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3580 3581//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3582#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3583 3584//uceDPToLVDSRxId 3585#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3586#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3587#define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init 3588 3589typedef struct _ATOM_PATCH_RECORD_MODE 3590{ 3591 UCHAR ucRecordType; 3592 USHORT usHDisp; 3593 USHORT usVDisp; 3594}ATOM_PATCH_RECORD_MODE; 3595 3596typedef struct _ATOM_LCD_RTS_RECORD 3597{ 3598 UCHAR ucRecordType; 3599 UCHAR ucRTSValue; 3600}ATOM_LCD_RTS_RECORD; 3601 3602//!! If the record below exists, it should always be the first record for easy use in command table!!! 3603// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3604typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3605{ 3606 UCHAR ucRecordType; 3607 USHORT usLCDCap; 3608}ATOM_LCD_MODE_CONTROL_CAP; 3609 3610#define LCD_MODE_CAP_BL_OFF 1 3611#define LCD_MODE_CAP_CRTC_OFF 2 3612#define LCD_MODE_CAP_PANEL_OFF 4 3613 3614typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3615{ 3616 UCHAR ucRecordType; 3617 UCHAR ucFakeEDIDLength; 3618 UCHAR ucFakeEDIDString[]; // This actually has ucFakeEdidLength elements. 3619} ATOM_FAKE_EDID_PATCH_RECORD; 3620 3621typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3622{ 3623 UCHAR ucRecordType; 3624 USHORT usHSize; 3625 USHORT usVSize; 3626}ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3627 3628#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3629#define LCD_RTS_RECORD_TYPE 2 3630#define LCD_CAP_RECORD_TYPE 3 3631#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3632#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3633#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3634#define ATOM_RECORD_END_TYPE 0xFF 3635 3636/****************************Spread Spectrum Info Table Definitions **********************/ 3637 3638//ucTableFormatRevision=1 3639//ucTableContentRevision=2 3640typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3641{ 3642 USHORT usSpreadSpectrumPercentage; 3643 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3644 UCHAR ucSS_Step; 3645 UCHAR ucSS_Delay; 3646 UCHAR ucSS_Id; 3647 UCHAR ucRecommendedRef_Div; 3648 UCHAR ucSS_Range; //it was reserved for V11 3649}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3650 3651#define ATOM_MAX_SS_ENTRY 16 3652#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3653#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3654#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3655#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3656 3657 3658#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3659#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3660#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3661#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3662#define ATOM_INTERNAL_SS_MASK 0x00000000 3663#define ATOM_EXTERNAL_SS_MASK 0x00000002 3664#define EXEC_SS_STEP_SIZE_SHIFT 2 3665#define EXEC_SS_DELAY_SHIFT 4 3666#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3667 3668typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3669{ 3670 ATOM_COMMON_TABLE_HEADER sHeader; 3671 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3672}ATOM_SPREAD_SPECTRUM_INFO; 3673 3674/****************************************************************************/ 3675// Structure used in AnalogTV_InfoTable (Top level) 3676/****************************************************************************/ 3677//ucTVBootUpDefaultStd definition: 3678 3679//ATOM_TV_NTSC 1 3680//ATOM_TV_NTSCJ 2 3681//ATOM_TV_PAL 3 3682//ATOM_TV_PALM 4 3683//ATOM_TV_PALCN 5 3684//ATOM_TV_PALN 6 3685//ATOM_TV_PAL60 7 3686//ATOM_TV_SECAM 8 3687 3688//ucTVSupportedStd definition: 3689#define NTSC_SUPPORT 0x1 3690#define NTSCJ_SUPPORT 0x2 3691 3692#define PAL_SUPPORT 0x4 3693#define PALM_SUPPORT 0x8 3694#define PALCN_SUPPORT 0x10 3695#define PALN_SUPPORT 0x20 3696#define PAL60_SUPPORT 0x40 3697#define SECAM_SUPPORT 0x80 3698 3699#define MAX_SUPPORTED_TV_TIMING 2 3700 3701typedef struct _ATOM_ANALOG_TV_INFO 3702{ 3703 ATOM_COMMON_TABLE_HEADER sHeader; 3704 UCHAR ucTV_SupportedStandard; 3705 UCHAR ucTV_BootUpDefaultStandard; 3706 UCHAR ucExt_TV_ASIC_ID; 3707 UCHAR ucExt_TV_ASIC_SlaveAddr; 3708 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 3709 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3710}ATOM_ANALOG_TV_INFO; 3711 3712#define MAX_SUPPORTED_TV_TIMING_V1_2 3 3713 3714typedef struct _ATOM_ANALOG_TV_INFO_V1_2 3715{ 3716 ATOM_COMMON_TABLE_HEADER sHeader; 3717 UCHAR ucTV_SupportedStandard; 3718 UCHAR ucTV_BootUpDefaultStandard; 3719 UCHAR ucExt_TV_ASIC_ID; 3720 UCHAR ucExt_TV_ASIC_SlaveAddr; 3721 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 3722}ATOM_ANALOG_TV_INFO_V1_2; 3723 3724typedef struct _ATOM_DPCD_INFO 3725{ 3726 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3727 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3729 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3730}ATOM_DPCD_INFO; 3731 3732#define ATOM_DPCD_MAX_LANE_MASK 0x1F 3733 3734/**************************************************************************/ 3735// VRAM usage and their defintions 3736 3737// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3738// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3739// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3740// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3741// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3742 3743#ifndef VESA_MEMORY_IN_64K_BLOCK 3744#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3745#endif 3746 3747#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3748#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3749#define ATOM_HWICON_INFOTABLE_SIZE 32 3750#define MAX_DTD_MODE_IN_VRAM 6 3751#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3752#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3753//20 bytes for Encoder Type and DPCD in STD EDID area 3754#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3755#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3756 3757#define ATOM_HWICON1_SURFACE_ADDR 0 3758#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3759#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3760#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3761#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3762#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3763 3764#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3765#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3766#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3767 3768#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3769 3770#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3771#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3772#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3773 3774#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3775#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3776#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3777 3778#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3779#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3780#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3781 3782#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3783#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3784#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3785 3786#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3787#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3788#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3789 3790#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3791#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3792#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3793 3794#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3795#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3796#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3797 3798#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3799#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3800#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3801 3802#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3803#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3804#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3805 3806#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3807 3808#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3809#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3810 3811//The size below is in Kb! 3812#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3813 3814#define ATOM_VRAM_RESERVE_V2_SIZE 32 3815 3816#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3817#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3818#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3819#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3820 3821/***********************************************************************************/ 3822// Structure used in VRAM_UsageByFirmwareTable 3823// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3824// at running time. 3825// note2: From RV770, the memory is more than 32bit addressable, so we will change 3826// ucTableFormatRevision=1,ucTableContentRevision=4, the structure remains 3827// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3828// (in offset to start of memory address) is KB aligned instead of byte aligned. 3829// Note3: 3830/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 3831for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3832 3833If (ulStartAddrUsedByFirmware!=0) 3834FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3835Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3836else //Non VGA case 3837 if (FB_Size<=2Gb) 3838 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3839 else 3840 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3841 3842CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3843 3844/***********************************************************************************/ 3845#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3846 3847typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3848{ 3849 ULONG ulStartAddrUsedByFirmware; 3850 USHORT usFirmwareUseInKb; 3851 USHORT usReserved; 3852}ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3853 3854typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3855{ 3856 ATOM_COMMON_TABLE_HEADER sHeader; 3857 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3858}ATOM_VRAM_USAGE_BY_FIRMWARE; 3859 3860// change version to 1.5, when allow driver to allocate the vram area for command table access. 3861typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3862{ 3863 ULONG ulStartAddrUsedByFirmware; 3864 USHORT usFirmwareUseInKb; 3865 USHORT usFBUsedByDrvInKb; 3866}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3867 3868typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3869{ 3870 ATOM_COMMON_TABLE_HEADER sHeader; 3871 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3872}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3873 3874/****************************************************************************/ 3875// Structure used in GPIO_Pin_LUTTable 3876/****************************************************************************/ 3877typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3878{ 3879 USHORT usGpioPin_AIndex; 3880 UCHAR ucGpioPinBitShift; 3881 UCHAR ucGPIO_ID; 3882}ATOM_GPIO_PIN_ASSIGNMENT; 3883 3884//ucGPIO_ID pre-define id for multiple usage 3885//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable 3886#define PP_AC_DC_SWITCH_GPIO_PINID 60 3887//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 3888#define VDDC_VRHOT_GPIO_PINID 61 3889//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 3890#define VDDC_PCC_GPIO_PINID 62 3891 3892typedef struct _ATOM_GPIO_PIN_LUT 3893{ 3894 ATOM_COMMON_TABLE_HEADER sHeader; 3895 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[]; 3896}ATOM_GPIO_PIN_LUT; 3897 3898/****************************************************************************/ 3899// Structure used in ComponentVideoInfoTable 3900/****************************************************************************/ 3901#define GPIO_PIN_ACTIVE_HIGH 0x1 3902 3903#define MAX_SUPPORTED_CV_STANDARDS 5 3904 3905// definitions for ATOM_D_INFO.ucSettings 3906#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 3907#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 3908#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3909 3910typedef struct _ATOM_GPIO_INFO 3911{ 3912 USHORT usAOffset; 3913 UCHAR ucSettings; 3914 UCHAR ucReserved; 3915}ATOM_GPIO_INFO; 3916 3917// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3918#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3919 3920// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3921#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3922#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3923 3924// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3925//Line 3 out put 5V. 3926#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3927#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3928#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3929 3930//Line 3 out put 2.2V 3931#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3932#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3933#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3934 3935//Line 3 out put 0V 3936#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3937#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3938#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3939 3940#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3941 3942#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3943 3944//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3945#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3946#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3947 3948 3949typedef struct _ATOM_COMPONENT_VIDEO_INFO 3950{ 3951 ATOM_COMMON_TABLE_HEADER sHeader; 3952 USHORT usMask_PinRegisterIndex; 3953 USHORT usEN_PinRegisterIndex; 3954 USHORT usY_PinRegisterIndex; 3955 USHORT usA_PinRegisterIndex; 3956 UCHAR ucBitShift; 3957 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3958 ATOM_DTD_FORMAT sReserved; // must be zeroed out 3959 UCHAR ucMiscInfo; 3960 UCHAR uc480i; 3961 UCHAR uc480p; 3962 UCHAR uc720p; 3963 UCHAR uc1080i; 3964 UCHAR ucLetterBoxMode; 3965 UCHAR ucReserved[3]; 3966 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3967 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3968 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3969}ATOM_COMPONENT_VIDEO_INFO; 3970 3971//ucTableFormatRevision=2 3972//ucTableContentRevision=1 3973typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3974{ 3975 ATOM_COMMON_TABLE_HEADER sHeader; 3976 UCHAR ucMiscInfo; 3977 UCHAR uc480i; 3978 UCHAR uc480p; 3979 UCHAR uc720p; 3980 UCHAR uc1080i; 3981 UCHAR ucReserved; 3982 UCHAR ucLetterBoxMode; 3983 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3984 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3985 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3986}ATOM_COMPONENT_VIDEO_INFO_V21; 3987 3988#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3989 3990/****************************************************************************/ 3991// Structure used in object_InfoTable 3992/****************************************************************************/ 3993typedef struct _ATOM_OBJECT_HEADER 3994{ 3995 ATOM_COMMON_TABLE_HEADER sHeader; 3996 USHORT usDeviceSupport; 3997 USHORT usConnectorObjectTableOffset; 3998 USHORT usRouterObjectTableOffset; 3999 USHORT usEncoderObjectTableOffset; 4000 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4001 USHORT usDisplayPathTableOffset; 4002}ATOM_OBJECT_HEADER; 4003 4004typedef struct _ATOM_OBJECT_HEADER_V3 4005{ 4006 ATOM_COMMON_TABLE_HEADER sHeader; 4007 USHORT usDeviceSupport; 4008 USHORT usConnectorObjectTableOffset; 4009 USHORT usRouterObjectTableOffset; 4010 USHORT usEncoderObjectTableOffset; 4011 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4012 USHORT usDisplayPathTableOffset; 4013 USHORT usMiscObjectTableOffset; 4014}ATOM_OBJECT_HEADER_V3; 4015 4016typedef struct _ATOM_DISPLAY_OBJECT_PATH 4017{ 4018 USHORT usDeviceTag; //supported device 4019 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4020 USHORT usConnObjectId; //Connector Object ID 4021 USHORT usGPUObjectId; //GPU ID 4022 USHORT usGraphicObjIds[]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4023}ATOM_DISPLAY_OBJECT_PATH; 4024 4025typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4026{ 4027 USHORT usDeviceTag; //supported device 4028 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4029 USHORT usConnObjectId; //Connector Object ID 4030 USHORT usGPUObjectId; //GPU ID 4031 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4032}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4033 4034typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4035{ 4036 UCHAR ucNumOfDispPath; 4037 UCHAR ucVersion; 4038 UCHAR ucPadding[2]; 4039 ATOM_DISPLAY_OBJECT_PATH asDispPath[]; 4040}ATOM_DISPLAY_OBJECT_PATH_TABLE; 4041 4042 4043typedef struct _ATOM_OBJECT //each object has this structure 4044{ 4045 USHORT usObjectID; 4046 USHORT usSrcDstTableOffset; 4047 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4048 USHORT usReserved; 4049}ATOM_OBJECT; 4050 4051typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4052{ 4053 UCHAR ucNumberOfObjects; 4054 UCHAR ucPadding[3]; 4055 ATOM_OBJECT asObjects[]; 4056}ATOM_OBJECT_TABLE; 4057 4058typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4059{ 4060 UCHAR ucNumberOfSrc; 4061 USHORT usSrcObjectID[1]; 4062 UCHAR ucNumberOfDst; 4063 USHORT usDstObjectID[]; 4064}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4065 4066 4067//Two definitions below are for OPM on MXM module designs 4068 4069#define EXT_HPDPIN_LUTINDEX_0 0 4070#define EXT_HPDPIN_LUTINDEX_1 1 4071#define EXT_HPDPIN_LUTINDEX_2 2 4072#define EXT_HPDPIN_LUTINDEX_3 3 4073#define EXT_HPDPIN_LUTINDEX_4 4 4074#define EXT_HPDPIN_LUTINDEX_5 5 4075#define EXT_HPDPIN_LUTINDEX_6 6 4076#define EXT_HPDPIN_LUTINDEX_7 7 4077#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4078 4079#define EXT_AUXDDC_LUTINDEX_0 0 4080#define EXT_AUXDDC_LUTINDEX_1 1 4081#define EXT_AUXDDC_LUTINDEX_2 2 4082#define EXT_AUXDDC_LUTINDEX_3 3 4083#define EXT_AUXDDC_LUTINDEX_4 4 4084#define EXT_AUXDDC_LUTINDEX_5 5 4085#define EXT_AUXDDC_LUTINDEX_6 6 4086#define EXT_AUXDDC_LUTINDEX_7 7 4087#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4088 4089//ucChannelMapping are defined as following 4090//for DP connector, eDP, DP to VGA/LVDS 4091//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4092//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4093//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4094//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4095typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4096{ 4097#if ATOM_BIG_ENDIAN 4098 UCHAR ucDP_Lane3_Source:2; 4099 UCHAR ucDP_Lane2_Source:2; 4100 UCHAR ucDP_Lane1_Source:2; 4101 UCHAR ucDP_Lane0_Source:2; 4102#else 4103 UCHAR ucDP_Lane0_Source:2; 4104 UCHAR ucDP_Lane1_Source:2; 4105 UCHAR ucDP_Lane2_Source:2; 4106 UCHAR ucDP_Lane3_Source:2; 4107#endif 4108}ATOM_DP_CONN_CHANNEL_MAPPING; 4109 4110//for DVI/HDMI, in dual link case, both links have to have same mapping. 4111//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4112//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4113//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4114//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4115typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4116{ 4117#if ATOM_BIG_ENDIAN 4118 UCHAR ucDVI_CLK_Source:2; 4119 UCHAR ucDVI_DATA0_Source:2; 4120 UCHAR ucDVI_DATA1_Source:2; 4121 UCHAR ucDVI_DATA2_Source:2; 4122#else 4123 UCHAR ucDVI_DATA2_Source:2; 4124 UCHAR ucDVI_DATA1_Source:2; 4125 UCHAR ucDVI_DATA0_Source:2; 4126 UCHAR ucDVI_CLK_Source:2; 4127#endif 4128}ATOM_DVI_CONN_CHANNEL_MAPPING; 4129 4130typedef struct _EXT_DISPLAY_PATH 4131{ 4132 USHORT usDeviceTag; //A bit vector to show what devices are supported 4133 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4134 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4135 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4136 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4137 USHORT usExtEncoderObjId; //external encoder object id 4138 union{ 4139 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4140 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4141 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4142 }; 4143 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4144 USHORT usCaps; 4145 USHORT usReserved; 4146}EXT_DISPLAY_PATH; 4147 4148#define NUMBER_OF_UCHAR_FOR_GUID 16 4149#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4150 4151//usCaps 4152#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4153#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 4154 4155typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4156{ 4157 ATOM_COMMON_TABLE_HEADER sHeader; 4158 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4159 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4160 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4161 UCHAR uc3DStereoPinId; // use for eDP panel 4162 UCHAR ucRemoteDisplayConfig; 4163 UCHAR uceDPToLVDSRxId; 4164 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4165 UCHAR Reserved[3]; // for potential expansion 4166}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4167 4168//Related definitions, all records are different but they have a commond header 4169typedef struct _ATOM_COMMON_RECORD_HEADER 4170{ 4171 UCHAR ucRecordType; //An emun to indicate the record type 4172 UCHAR ucRecordSize; //The size of the whole record in byte 4173}ATOM_COMMON_RECORD_HEADER; 4174 4175 4176#define ATOM_I2C_RECORD_TYPE 1 4177#define ATOM_HPD_INT_RECORD_TYPE 2 4178#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4179#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4180#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4181#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4182#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4183#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4184#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4185#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4186#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4187#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4188#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4189#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4190#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4191#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4192#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4193#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4194#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4195#define ATOM_ENCODER_CAP_RECORD_TYPE 20 4196#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4197 4198//Must be updated when new record type is added,equal to that record definition! 4199#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE 4200 4201typedef struct _ATOM_I2C_RECORD 4202{ 4203 ATOM_COMMON_RECORD_HEADER sheader; 4204 ATOM_I2C_ID_CONFIG sucI2cId; 4205 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4206}ATOM_I2C_RECORD; 4207 4208typedef struct _ATOM_HPD_INT_RECORD 4209{ 4210 ATOM_COMMON_RECORD_HEADER sheader; 4211 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4212 UCHAR ucPlugged_PinState; 4213}ATOM_HPD_INT_RECORD; 4214 4215 4216typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4217{ 4218 ATOM_COMMON_RECORD_HEADER sheader; 4219 UCHAR ucProtectionFlag; 4220 UCHAR ucReserved; 4221}ATOM_OUTPUT_PROTECTION_RECORD; 4222 4223typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4224{ 4225 ULONG ulACPIDeviceEnum; //Reserved for now 4226 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4227 USHORT usPadding; 4228}ATOM_CONNECTOR_DEVICE_TAG; 4229 4230typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4231{ 4232 ATOM_COMMON_RECORD_HEADER sheader; 4233 UCHAR ucNumberOfDevice; 4234 UCHAR ucReserved; 4235 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4236}ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4237 4238 4239typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4240{ 4241 ATOM_COMMON_RECORD_HEADER sheader; 4242 UCHAR ucConfigGPIOID; 4243 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4244 UCHAR ucFlowinGPIPID; 4245 UCHAR ucExtInGPIPID; 4246}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4247 4248typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4249{ 4250 ATOM_COMMON_RECORD_HEADER sheader; 4251 UCHAR ucCTL1GPIO_ID; 4252 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4253 UCHAR ucCTL2GPIO_ID; 4254 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4255 UCHAR ucCTL3GPIO_ID; 4256 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4257 UCHAR ucCTLFPGA_IN_ID; 4258 UCHAR ucPadding[3]; 4259}ATOM_ENCODER_FPGA_CONTROL_RECORD; 4260 4261typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4262{ 4263 ATOM_COMMON_RECORD_HEADER sheader; 4264 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4265 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4266}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4267 4268typedef struct _ATOM_JTAG_RECORD 4269{ 4270 ATOM_COMMON_RECORD_HEADER sheader; 4271 UCHAR ucTMSGPIO_ID; 4272 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4273 UCHAR ucTCKGPIO_ID; 4274 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4275 UCHAR ucTDOGPIO_ID; 4276 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4277 UCHAR ucTDIGPIO_ID; 4278 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4279 UCHAR ucPadding[2]; 4280}ATOM_JTAG_RECORD; 4281 4282 4283//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4284typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4285{ 4286 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4287 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4288}ATOM_GPIO_PIN_CONTROL_PAIR; 4289 4290typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4291{ 4292 ATOM_COMMON_RECORD_HEADER sheader; 4293 UCHAR ucFlags; // Future expnadibility 4294 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4295 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4296}ATOM_OBJECT_GPIO_CNTL_RECORD; 4297 4298//Definitions for GPIO pin state 4299#define GPIO_PIN_TYPE_INPUT 0x00 4300#define GPIO_PIN_TYPE_OUTPUT 0x10 4301#define GPIO_PIN_TYPE_HW_CONTROL 0x20 4302 4303//For GPIO_PIN_TYPE_OUTPUT the following is defined 4304#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4305#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4306#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4307#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4308 4309// Indexes to GPIO array in GLSync record 4310// GLSync record is for Frame Lock/Gen Lock feature. 4311#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4312#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4313#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4314#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4315#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4316#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4317#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4318#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4319#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4320#define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4321 4322typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4323{ 4324 ATOM_COMMON_RECORD_HEADER sheader; 4325 ULONG ulStrengthControl; // DVOA strength control for CF 4326 UCHAR ucPadding[2]; 4327}ATOM_ENCODER_DVO_CF_RECORD; 4328 4329// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4330#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4331#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4332 4333typedef struct _ATOM_ENCODER_CAP_RECORD 4334{ 4335 ATOM_COMMON_RECORD_HEADER sheader; 4336 union { 4337 USHORT usEncoderCap; 4338 struct { 4339#if ATOM_BIG_ENDIAN 4340 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4341 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4342 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4343#else 4344 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4345 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4346 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4347#endif 4348 }; 4349 }; 4350}ATOM_ENCODER_CAP_RECORD; 4351 4352// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4353#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4354#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4355 4356typedef struct _ATOM_CONNECTOR_CF_RECORD 4357{ 4358 ATOM_COMMON_RECORD_HEADER sheader; 4359 USHORT usMaxPixClk; 4360 UCHAR ucFlowCntlGpioId; 4361 UCHAR ucSwapCntlGpioId; 4362 UCHAR ucConnectedDvoBundle; 4363 UCHAR ucPadding; 4364}ATOM_CONNECTOR_CF_RECORD; 4365 4366typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4367{ 4368 ATOM_COMMON_RECORD_HEADER sheader; 4369 ATOM_DTD_FORMAT asTiming; 4370}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4371 4372typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4373{ 4374 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4375 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4376 UCHAR ucReserved; 4377}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4378 4379 4380typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4381{ 4382 ATOM_COMMON_RECORD_HEADER sheader; 4383 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4384 UCHAR ucMuxControlPin; 4385 UCHAR ucMuxState[2]; //for alligment purpose 4386}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4387 4388typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4389{ 4390 ATOM_COMMON_RECORD_HEADER sheader; 4391 UCHAR ucMuxType; 4392 UCHAR ucMuxControlPin; 4393 UCHAR ucMuxState[2]; //for alligment purpose 4394}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4395 4396// define ucMuxType 4397#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4398#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4399 4400typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4401{ 4402 ATOM_COMMON_RECORD_HEADER sheader; 4403 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4404}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4405 4406typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4407{ 4408 ATOM_COMMON_RECORD_HEADER sheader; 4409 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4410}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4411 4412typedef struct _ATOM_OBJECT_LINK_RECORD 4413{ 4414 ATOM_COMMON_RECORD_HEADER sheader; 4415 USHORT usObjectID; //could be connector, encorder or other object in object.h 4416}ATOM_OBJECT_LINK_RECORD; 4417 4418typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4419{ 4420 ATOM_COMMON_RECORD_HEADER sheader; 4421 USHORT usReserved; 4422}ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4423 4424typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4425{ 4426 USHORT usConnectorObjectId; 4427 UCHAR ucConnectorType; 4428 UCHAR ucPosition; 4429}ATOM_CONNECTOR_LAYOUT_INFO; 4430 4431// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4432#define CONNECTOR_TYPE_DVI_D 1 4433#define CONNECTOR_TYPE_DVI_I 2 4434#define CONNECTOR_TYPE_VGA 3 4435#define CONNECTOR_TYPE_HDMI 4 4436#define CONNECTOR_TYPE_DISPLAY_PORT 5 4437#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4438 4439typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4440{ 4441 ATOM_COMMON_RECORD_HEADER sheader; 4442 UCHAR ucLength; 4443 UCHAR ucWidth; 4444 UCHAR ucConnNum; 4445 UCHAR ucReserved; 4446 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[]; 4447}ATOM_BRACKET_LAYOUT_RECORD; 4448 4449/****************************************************************************/ 4450// ASIC voltage data table 4451/****************************************************************************/ 4452typedef struct _ATOM_VOLTAGE_INFO_HEADER 4453{ 4454 USHORT usVDDCBaseLevel; //In number of 50mv unit 4455 USHORT usReserved; //For possible extension table offset 4456 UCHAR ucNumOfVoltageEntries; 4457 UCHAR ucBytesPerVoltageEntry; 4458 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4459 UCHAR ucDefaultVoltageEntry; 4460 UCHAR ucVoltageControlI2cLine; 4461 UCHAR ucVoltageControlAddress; 4462 UCHAR ucVoltageControlOffset; 4463}ATOM_VOLTAGE_INFO_HEADER; 4464 4465typedef struct _ATOM_VOLTAGE_INFO 4466{ 4467 ATOM_COMMON_TABLE_HEADER sHeader; 4468 ATOM_VOLTAGE_INFO_HEADER viHeader; 4469 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4470}ATOM_VOLTAGE_INFO; 4471 4472 4473typedef struct _ATOM_VOLTAGE_FORMULA 4474{ 4475 USHORT usVoltageBaseLevel; // In number of 1mv unit 4476 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4477 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4478 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4479 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4480 UCHAR ucReserved; 4481 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4482}ATOM_VOLTAGE_FORMULA; 4483 4484typedef struct _VOLTAGE_LUT_ENTRY 4485{ 4486 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4487 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4488}VOLTAGE_LUT_ENTRY; 4489 4490typedef struct _ATOM_VOLTAGE_FORMULA_V2 4491{ 4492 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4493 UCHAR ucReserved[3]; 4494 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4495}ATOM_VOLTAGE_FORMULA_V2; 4496 4497typedef struct _ATOM_VOLTAGE_CONTROL 4498{ 4499 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4500 UCHAR ucVoltageControlI2cLine; 4501 UCHAR ucVoltageControlAddress; 4502 UCHAR ucVoltageControlOffset; 4503 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4504 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4505 UCHAR ucReserved; 4506}ATOM_VOLTAGE_CONTROL; 4507 4508// Define ucVoltageControlId 4509#define VOLTAGE_CONTROLLED_BY_HW 0x00 4510#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4511#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4512#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4513#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4514#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4515#define VOLTAGE_CONTROL_ID_DS4402 0x04 4516#define VOLTAGE_CONTROL_ID_UP6266 0x05 4517#define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4518#define VOLTAGE_CONTROL_ID_VT1556M 0x07 4519#define VOLTAGE_CONTROL_ID_CHL822x 0x08 4520#define VOLTAGE_CONTROL_ID_VT1586M 0x09 4521#define VOLTAGE_CONTROL_ID_UP1637 0x0A 4522#define VOLTAGE_CONTROL_ID_CHL8214 0x0B 4523#define VOLTAGE_CONTROL_ID_UP1801 0x0C 4524#define VOLTAGE_CONTROL_ID_ST6788A 0x0D 4525#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 4526#define VOLTAGE_CONTROL_ID_AD527x 0x0F 4527#define VOLTAGE_CONTROL_ID_NCP81022 0x10 4528#define VOLTAGE_CONTROL_ID_LTC2635 0x11 4529 4530typedef struct _ATOM_VOLTAGE_OBJECT 4531{ 4532 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4533 UCHAR ucSize; //Size of Object 4534 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4535 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4536}ATOM_VOLTAGE_OBJECT; 4537 4538typedef struct _ATOM_VOLTAGE_OBJECT_V2 4539{ 4540 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4541 UCHAR ucSize; //Size of Object 4542 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4543 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4544}ATOM_VOLTAGE_OBJECT_V2; 4545 4546typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4547{ 4548 ATOM_COMMON_TABLE_HEADER sHeader; 4549 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4550}ATOM_VOLTAGE_OBJECT_INFO; 4551 4552typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4553{ 4554 ATOM_COMMON_TABLE_HEADER sHeader; 4555 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4556}ATOM_VOLTAGE_OBJECT_INFO_V2; 4557 4558typedef struct _ATOM_LEAKID_VOLTAGE 4559{ 4560 UCHAR ucLeakageId; 4561 UCHAR ucReserved; 4562 USHORT usVoltage; 4563}ATOM_LEAKID_VOLTAGE; 4564 4565typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4566 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4567 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4568 USHORT usSize; //Size of Object 4569}ATOM_VOLTAGE_OBJECT_HEADER_V3; 4570 4571// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 4572#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4573#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 4574#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4575#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 4576#define VOLTAGE_OBJ_EVV 8 4577#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4578#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4579#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4580 4581typedef struct _VOLTAGE_LUT_ENTRY_V2 4582{ 4583 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4584 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4585}VOLTAGE_LUT_ENTRY_V2; 4586 4587typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4588{ 4589 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4590 USHORT usVoltageId; 4591 USHORT usLeakageId; // The corresponding Voltage Value, in mV 4592}LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4593 4594typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4595{ 4596 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 4597 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4598 UCHAR ucVoltageControlI2cLine; 4599 UCHAR ucVoltageControlAddress; 4600 UCHAR ucVoltageControlOffset; 4601 ULONG ulReserved; 4602 VOLTAGE_LUT_ENTRY asVolI2cLut[]; // end with 0xff 4603}ATOM_I2C_VOLTAGE_OBJECT_V3; 4604 4605// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 4606#define VOLTAGE_DATA_ONE_BYTE 0 4607#define VOLTAGE_DATA_TWO_BYTE 1 4608 4609typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4610{ 4611 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 4612 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4613 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4614 UCHAR ucPhaseDelay; // phase delay in unit of micro second 4615 UCHAR ucReserved; 4616 ULONG ulGpioMaskVal; // GPIO Mask value 4617 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[]; 4618}ATOM_GPIO_VOLTAGE_OBJECT_V3; 4619 4620typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4621{ 4622 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 4623 UCHAR ucLeakageCntlId; // default is 0 4624 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4625 UCHAR ucReserved[2]; 4626 ULONG ulMaxVoltageLevel; 4627 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[]; 4628}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4629 4630 4631typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 4632{ 4633 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 4634// 14:7 – PSI0_VID 4635// 6 – PSI0_EN 4636// 5 – PSI1 4637// 4:2 – load line slope trim. 4638// 1:0 – offset trim, 4639 USHORT usLoadLine_PSI; 4640// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 4641 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 4642 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 4643 ULONG ulReserved; 4644}ATOM_SVID2_VOLTAGE_OBJECT_V3; 4645 4646typedef union _ATOM_VOLTAGE_OBJECT_V3{ 4647 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4648 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4649 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4650 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 4651}ATOM_VOLTAGE_OBJECT_V3; 4652 4653typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4654{ 4655 ATOM_COMMON_TABLE_HEADER sHeader; 4656 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4657}ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4658 4659typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4660{ 4661 UCHAR ucProfileId; 4662 UCHAR ucReserved; 4663 USHORT usSize; 4664 USHORT usEfuseSpareStartAddr; 4665 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4666 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4667}ATOM_ASIC_PROFILE_VOLTAGE; 4668 4669//ucProfileId 4670#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4671#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4672#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4673 4674typedef struct _ATOM_ASIC_PROFILING_INFO 4675{ 4676 ATOM_COMMON_TABLE_HEADER asHeader; 4677 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4678}ATOM_ASIC_PROFILING_INFO; 4679 4680typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 4681{ 4682 ATOM_COMMON_TABLE_HEADER asHeader; 4683 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 4684 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 4685 4686 UCHAR ucElbVDDC_Num; 4687 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 4688 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4689 4690 UCHAR ucElbVDDCI_Num; 4691 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 4692 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4693}ATOM_ASIC_PROFILING_INFO_V2_1; 4694 4695typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 4696{ 4697 ATOM_COMMON_TABLE_HEADER asHeader; 4698 ULONG ulEvvDerateTdp; 4699 ULONG ulEvvDerateTdc; 4700 ULONG ulBoardCoreTemp; 4701 ULONG ulMaxVddc; 4702 ULONG ulMinVddc; 4703 ULONG ulLoadLineSlop; 4704 ULONG ulLeakageTemp; 4705 ULONG ulLeakageVoltage; 4706 ULONG ulCACmEncodeRange; 4707 ULONG ulCACmEncodeAverage; 4708 ULONG ulCACbEncodeRange; 4709 ULONG ulCACbEncodeAverage; 4710 ULONG ulKt_bEncodeRange; 4711 ULONG ulKt_bEncodeAverage; 4712 ULONG ulKv_mEncodeRange; 4713 ULONG ulKv_mEncodeAverage; 4714 ULONG ulKv_bEncodeRange; 4715 ULONG ulKv_bEncodeAverage; 4716 ULONG ulLkgEncodeLn_MaxDivMin; 4717 ULONG ulLkgEncodeMin; 4718 ULONG ulEfuseLogisticAlpha; 4719 USHORT usPowerDpm0; 4720 USHORT usCurrentDpm0; 4721 USHORT usPowerDpm1; 4722 USHORT usCurrentDpm1; 4723 USHORT usPowerDpm2; 4724 USHORT usCurrentDpm2; 4725 USHORT usPowerDpm3; 4726 USHORT usCurrentDpm3; 4727 USHORT usPowerDpm4; 4728 USHORT usCurrentDpm4; 4729 USHORT usPowerDpm5; 4730 USHORT usCurrentDpm5; 4731 USHORT usPowerDpm6; 4732 USHORT usCurrentDpm6; 4733 USHORT usPowerDpm7; 4734 USHORT usCurrentDpm7; 4735}ATOM_ASIC_PROFILING_INFO_V3_1; 4736 4737 4738typedef struct _ATOM_POWER_SOURCE_OBJECT 4739{ 4740 UCHAR ucPwrSrcId; // Power source 4741 UCHAR ucPwrSensorType; // GPIO, I2C or none 4742 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4743 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4744 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 4745 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 4746 UCHAR ucPwrSensActiveState; // high active or low active 4747 UCHAR ucReserve[3]; // reserve 4748 USHORT usSensPwr; // in unit of watt 4749}ATOM_POWER_SOURCE_OBJECT; 4750 4751typedef struct _ATOM_POWER_SOURCE_INFO 4752{ 4753 ATOM_COMMON_TABLE_HEADER asHeader; 4754 UCHAR asPwrbehave[16]; 4755 ATOM_POWER_SOURCE_OBJECT asPwrObj[]; 4756}ATOM_POWER_SOURCE_INFO; 4757 4758 4759//Define ucPwrSrcId 4760#define POWERSOURCE_PCIE_ID1 0x00 4761#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 4762#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 4763#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 4764#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 4765 4766//define ucPwrSensorId 4767#define POWER_SENSOR_ALWAYS 0x00 4768#define POWER_SENSOR_GPIO 0x01 4769#define POWER_SENSOR_I2C 0x02 4770 4771typedef struct _ATOM_CLK_VOLT_CAPABILITY 4772{ 4773 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 4774 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4775}ATOM_CLK_VOLT_CAPABILITY; 4776 4777typedef struct _ATOM_AVAILABLE_SCLK_LIST 4778{ 4779 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4780 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 4781 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 4782}ATOM_AVAILABLE_SCLK_LIST; 4783 4784// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 4785#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 4786 4787// this IntegrateSystemInfoTable is used for Liano/Ontario APU 4788typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4789{ 4790 ATOM_COMMON_TABLE_HEADER sHeader; 4791 ULONG ulBootUpEngineClock; 4792 ULONG ulDentistVCOFreq; 4793 ULONG ulBootUpUMAClock; 4794 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4795 ULONG ulBootUpReqDisplayVector; 4796 ULONG ulOtherDisplayMisc; 4797 ULONG ulGPUCapInfo; 4798 ULONG ulSB_MMIO_Base_Addr; 4799 USHORT usRequestedPWMFreqInHz; 4800 UCHAR ucHtcTmpLmt; 4801 UCHAR ucHtcHystLmt; 4802 ULONG ulMinEngineClock; 4803 ULONG ulSystemConfig; 4804 ULONG ulCPUCapInfo; 4805 USHORT usNBP0Voltage; 4806 USHORT usNBP1Voltage; 4807 USHORT usBootUpNBVoltage; 4808 USHORT usExtDispConnInfoOffset; 4809 USHORT usPanelRefreshRateRange; 4810 UCHAR ucMemoryType; 4811 UCHAR ucUMAChannelNumber; 4812 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4813 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4814 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4815 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4816 ULONG ulGMCRestoreResetTime; 4817 ULONG ulMinimumNClk; 4818 ULONG ulIdleNClk; 4819 ULONG ulDDR_DLL_PowerUpTime; 4820 ULONG ulDDR_PLL_PowerUpTime; 4821 USHORT usPCIEClkSSPercentage; 4822 USHORT usPCIEClkSSType; 4823 USHORT usLvdsSSPercentage; 4824 USHORT usLvdsSSpreadRateIn10Hz; 4825 USHORT usHDMISSPercentage; 4826 USHORT usHDMISSpreadRateIn10Hz; 4827 USHORT usDVISSPercentage; 4828 USHORT usDVISSpreadRateIn10Hz; 4829 ULONG SclkDpmBoostMargin; 4830 ULONG SclkDpmThrottleMargin; 4831 USHORT SclkDpmTdpLimitPG; 4832 USHORT SclkDpmTdpLimitBoost; 4833 ULONG ulBoostEngineCLock; 4834 UCHAR ulBoostVid_2bit; 4835 UCHAR EnableBoost; 4836 USHORT GnbTdpLimit; 4837 USHORT usMaxLVDSPclkFreqInSingleLink; 4838 UCHAR ucLvdsMisc; 4839 UCHAR ucLVDSReserved; 4840 ULONG ulReserved3[15]; 4841 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4842}ATOM_INTEGRATED_SYSTEM_INFO_V6; 4843 4844// ulGPUCapInfo 4845#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4846#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 4847 4848//ucLVDSMisc: 4849#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 4850#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 4851#define SYS_INFO_LVDSMISC__888_BPC 0x04 4852#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 4853#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 4854// new since Trinity 4855#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 4856 4857// not used any more 4858#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 4859#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 4860 4861/********************************************************************************************************************** 4862 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4863ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4864ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4865ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4866sDISPCLK_Voltage: Report Display clock voltage requirement. 4867 4868ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 4869 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4870 ATOM_DEVICE_CRT2_SUPPORT 0x0010 4871 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4872 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4873 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4874 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4875 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4876 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4877 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4878ulOtherDisplayMisc: Other display related flags, not defined yet. 4879ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4880 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4881 bit[3]=0: Enable HW AUX mode detection logic 4882 =1: Disable HW AUX mode dettion logic 4883ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4884 4885usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4886 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4887 4888 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4889 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4890 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4891 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4892 and enabling VariBri under the driver environment from PP table is optional. 4893 4894 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4895 that BL control from GPU is expected. 4896 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4897 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4898 it's per platform 4899 and enabling VariBri under the driver environment from PP table is optional. 4900 4901ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4902 Threshold on value to enter HTC_active state. 4903ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4904 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4905ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4906ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4907 =1: PCIE Power Gating Enabled 4908 Bit[1]=0: DDR-DLL shut-down feature disabled. 4909 1: DDR-DLL shut-down feature enabled. 4910 Bit[2]=0: DDR-PLL Power down feature disabled. 4911 1: DDR-PLL Power down feature enabled. 4912ulCPUCapInfo: TBD 4913usNBP0Voltage: VID for voltage on NB P0 State 4914usNBP1Voltage: VID for voltage on NB P1 State 4915usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4916usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4917usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4918 to indicate a range. 4919 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4920 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4921 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4922 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4923ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4924ucUMAChannelNumber: System memory channel numbers. 4925ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4926ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4927ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4928sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4929ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4930ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4931ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4932ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4933ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4934usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 4935usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4936usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4937usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4938usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4939usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4940usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4941usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4942usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4943ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4944 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4945 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4946 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4947 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4948**********************************************************************************************************************/ 4949 4950// this Table is used for Liano/Ontario APU 4951typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 4952{ 4953 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 4954 ULONG ulPowerplayTable[128]; 4955}ATOM_FUSION_SYSTEM_INFO_V1; 4956 4957 4958typedef struct _ATOM_TDP_CONFIG_BITS 4959{ 4960#if ATOM_BIG_ENDIAN 4961 ULONG uReserved:2; 4962 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 4963 ULONG uCTDP_Value:14; // Override value in tens of milli watts 4964 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 4965#else 4966 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 4967 ULONG uCTDP_Value:14; // Override value in tens of milli watts 4968 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 4969 ULONG uReserved:2; 4970#endif 4971}ATOM_TDP_CONFIG_BITS; 4972 4973typedef union _ATOM_TDP_CONFIG 4974{ 4975 ATOM_TDP_CONFIG_BITS TDP_config; 4976 ULONG TDP_config_all; 4977}ATOM_TDP_CONFIG; 4978 4979/********************************************************************************************************************** 4980 ATOM_FUSION_SYSTEM_INFO_V1 Description 4981sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 4982ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 4983**********************************************************************************************************************/ 4984 4985// this IntegrateSystemInfoTable is used for Trinity APU 4986typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 4987{ 4988 ATOM_COMMON_TABLE_HEADER sHeader; 4989 ULONG ulBootUpEngineClock; 4990 ULONG ulDentistVCOFreq; 4991 ULONG ulBootUpUMAClock; 4992 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4993 ULONG ulBootUpReqDisplayVector; 4994 ULONG ulOtherDisplayMisc; 4995 ULONG ulGPUCapInfo; 4996 ULONG ulSB_MMIO_Base_Addr; 4997 USHORT usRequestedPWMFreqInHz; 4998 UCHAR ucHtcTmpLmt; 4999 UCHAR ucHtcHystLmt; 5000 ULONG ulMinEngineClock; 5001 ULONG ulSystemConfig; 5002 ULONG ulCPUCapInfo; 5003 USHORT usNBP0Voltage; 5004 USHORT usNBP1Voltage; 5005 USHORT usBootUpNBVoltage; 5006 USHORT usExtDispConnInfoOffset; 5007 USHORT usPanelRefreshRateRange; 5008 UCHAR ucMemoryType; 5009 UCHAR ucUMAChannelNumber; 5010 UCHAR strVBIOSMsg[40]; 5011 ATOM_TDP_CONFIG asTdpConfig; 5012 ULONG ulReserved[19]; 5013 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5014 ULONG ulGMCRestoreResetTime; 5015 ULONG ulMinimumNClk; 5016 ULONG ulIdleNClk; 5017 ULONG ulDDR_DLL_PowerUpTime; 5018 ULONG ulDDR_PLL_PowerUpTime; 5019 USHORT usPCIEClkSSPercentage; 5020 USHORT usPCIEClkSSType; 5021 USHORT usLvdsSSPercentage; 5022 USHORT usLvdsSSpreadRateIn10Hz; 5023 USHORT usHDMISSPercentage; 5024 USHORT usHDMISSpreadRateIn10Hz; 5025 USHORT usDVISSPercentage; 5026 USHORT usDVISSpreadRateIn10Hz; 5027 ULONG SclkDpmBoostMargin; 5028 ULONG SclkDpmThrottleMargin; 5029 USHORT SclkDpmTdpLimitPG; 5030 USHORT SclkDpmTdpLimitBoost; 5031 ULONG ulBoostEngineCLock; 5032 UCHAR ulBoostVid_2bit; 5033 UCHAR EnableBoost; 5034 USHORT GnbTdpLimit; 5035 USHORT usMaxLVDSPclkFreqInSingleLink; 5036 UCHAR ucLvdsMisc; 5037 UCHAR ucTravisLVDSVolAdjust; 5038 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5039 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5040 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5041 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5042 UCHAR ucLVDSOffToOnDelay_in4Ms; 5043 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5044 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5045 UCHAR ucMinAllowedBL_Level; 5046 ULONG ulLCDBitDepthControlVal; 5047 ULONG ulNbpStateMemclkFreq[4]; 5048 USHORT usNBP2Voltage; 5049 USHORT usNBP3Voltage; 5050 ULONG ulNbpStateNClkFreq[4]; 5051 UCHAR ucNBDPMEnable; 5052 UCHAR ucReserved[3]; 5053 UCHAR ucDPMState0VclkFid; 5054 UCHAR ucDPMState0DclkFid; 5055 UCHAR ucDPMState1VclkFid; 5056 UCHAR ucDPMState1DclkFid; 5057 UCHAR ucDPMState2VclkFid; 5058 UCHAR ucDPMState2DclkFid; 5059 UCHAR ucDPMState3VclkFid; 5060 UCHAR ucDPMState3DclkFid; 5061 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5062}ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 5063 5064// ulOtherDisplayMisc 5065#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 5066#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 5067#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 5068#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 5069 5070// ulGPUCapInfo 5071#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5072#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 5073#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 5074#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS 0x10 5075 5076/********************************************************************************************************************** 5077 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 5078ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5079ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5080ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5081sDISPCLK_Voltage: Report Display clock voltage requirement. 5082 5083ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5084 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5085 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5086 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5087 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5088 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5089 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5090 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5091 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5092ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5093 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5094 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5095 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5096 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5097 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5098 bit[3]=0: VBIOS fast boot is disable 5099 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5100ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5101 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5102 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 5103 =1: DP mode use single PLL mode 5104 bit[3]=0: Enable AUX HW mode detection logic 5105 =1: Disable AUX HW mode detection logic 5106 5107ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5108 5109usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5110 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5111 5112 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5113 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5114 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5115 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5116 and enabling VariBri under the driver environment from PP table is optional. 5117 5118 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5119 that BL control from GPU is expected. 5120 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5121 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5122 it's per platform 5123 and enabling VariBri under the driver environment from PP table is optional. 5124 5125ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5126 Threshold on value to enter HTC_active state. 5127ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5128 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5129ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5130ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5131 =1: PCIE Power Gating Enabled 5132 Bit[1]=0: DDR-DLL shut-down feature disabled. 5133 1: DDR-DLL shut-down feature enabled. 5134 Bit[2]=0: DDR-PLL Power down feature disabled. 5135 1: DDR-PLL Power down feature enabled. 5136ulCPUCapInfo: TBD 5137usNBP0Voltage: VID for voltage on NB P0 State 5138usNBP1Voltage: VID for voltage on NB P1 State 5139usNBP2Voltage: VID for voltage on NB P2 State 5140usNBP3Voltage: VID for voltage on NB P3 State 5141usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5142usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5143usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5144 to indicate a range. 5145 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5146 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5147 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5148 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5149ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5150ucUMAChannelNumber: System memory channel numbers. 5151ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5152ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5153ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5154sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5155ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5156ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5157ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5158ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5159ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5160usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5161usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5162usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5163usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5164usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5165usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5166usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5167usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5168usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5169ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5170 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5171 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5172 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5173 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5174 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5175ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5176 value to program Travis register LVDS_CTRL_4 5177ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5178 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5179 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5180ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5181 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5182 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5183 5184ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5185 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5186 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5187 5188ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5189 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5190 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5191 5192ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5193 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5194 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5195 5196ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5197 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5198 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5199 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5200 5201ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5202 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5203 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5204 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5205 5206ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5207 5208ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 5209 5210**********************************************************************************************************************/ 5211 5212// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 5213typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 5214{ 5215 ATOM_COMMON_TABLE_HEADER sHeader; 5216 ULONG ulBootUpEngineClock; 5217 ULONG ulDentistVCOFreq; 5218 ULONG ulBootUpUMAClock; 5219 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5220 ULONG ulBootUpReqDisplayVector; 5221 ULONG ulVBIOSMisc; 5222 ULONG ulGPUCapInfo; 5223 ULONG ulDISP_CLK2Freq; 5224 USHORT usRequestedPWMFreqInHz; 5225 UCHAR ucHtcTmpLmt; 5226 UCHAR ucHtcHystLmt; 5227 ULONG ulReserved2; 5228 ULONG ulSystemConfig; 5229 ULONG ulCPUCapInfo; 5230 ULONG ulReserved3; 5231 USHORT usGPUReservedSysMemSize; 5232 USHORT usExtDispConnInfoOffset; 5233 USHORT usPanelRefreshRateRange; 5234 UCHAR ucMemoryType; 5235 UCHAR ucUMAChannelNumber; 5236 UCHAR strVBIOSMsg[40]; 5237 ATOM_TDP_CONFIG asTdpConfig; 5238 ULONG ulReserved[19]; 5239 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5240 ULONG ulGMCRestoreResetTime; 5241 ULONG ulReserved4; 5242 ULONG ulIdleNClk; 5243 ULONG ulDDR_DLL_PowerUpTime; 5244 ULONG ulDDR_PLL_PowerUpTime; 5245 USHORT usPCIEClkSSPercentage; 5246 USHORT usPCIEClkSSType; 5247 USHORT usLvdsSSPercentage; 5248 USHORT usLvdsSSpreadRateIn10Hz; 5249 USHORT usHDMISSPercentage; 5250 USHORT usHDMISSpreadRateIn10Hz; 5251 USHORT usDVISSPercentage; 5252 USHORT usDVISSpreadRateIn10Hz; 5253 ULONG ulGPUReservedSysMemBaseAddrLo; 5254 ULONG ulGPUReservedSysMemBaseAddrHi; 5255 ULONG ulReserved5[3]; 5256 USHORT usMaxLVDSPclkFreqInSingleLink; 5257 UCHAR ucLvdsMisc; 5258 UCHAR ucTravisLVDSVolAdjust; 5259 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5260 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5261 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5262 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5263 UCHAR ucLVDSOffToOnDelay_in4Ms; 5264 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5265 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5266 UCHAR ucMinAllowedBL_Level; 5267 ULONG ulLCDBitDepthControlVal; 5268 ULONG ulNbpStateMemclkFreq[4]; 5269 ULONG ulReserved6; 5270 ULONG ulNbpStateNClkFreq[4]; 5271 USHORT usNBPStateVoltage[4]; 5272 USHORT usBootUpNBVoltage; 5273 USHORT usReserved2; 5274 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5275}ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 5276 5277/********************************************************************************************************************** 5278 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 5279ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5280ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5281ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5282sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 5283 5284ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5285 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5286 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5287 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5288 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5289 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5290 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5291 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5292 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5293 5294ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 5295 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5296 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5297 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5298 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5299 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5300 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5301 bit[3]=0: VBIOS fast boot is disable 5302 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5303 5304ulGPUCapInfo: bit[0~2]= Reserved 5305 bit[3]=0: Enable AUX HW mode detection logic 5306 =1: Disable AUX HW mode detection logic 5307 bit[4]=0: Disable DFS bypass feature 5308 =1: Enable DFS bypass feature 5309 5310usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5311 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5312 5313 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5314 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5315 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5316 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5317 and enabling VariBri under the driver environment from PP table is optional. 5318 5319 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5320 that BL control from GPU is expected. 5321 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5322 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5323 it's per platform 5324 and enabling VariBri under the driver environment from PP table is optional. 5325 5326ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 5327ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5328 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5329 5330ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5331 =1: PCIE Power Gating Enabled 5332 Bit[1]=0: DDR-DLL shut-down feature disabled. 5333 1: DDR-DLL shut-down feature enabled. 5334 Bit[2]=0: DDR-PLL Power down feature disabled. 5335 1: DDR-PLL Power down feature enabled. 5336 Bit[3]=0: GNB DPM is disabled 5337 =1: GNB DPM is enabled 5338ulCPUCapInfo: TBD 5339 5340usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5341usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5342 to indicate a range. 5343 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5344 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5345 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5346 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5347 5348ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 5349ucUMAChannelNumber: System memory channel numbers. 5350 5351strVBIOSMsg[40]: VBIOS boot up customized message string 5352 5353sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5354 5355ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5356ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 5357ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5358ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5359 5360usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5361usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5362usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5363usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5364usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5365usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5366usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5367usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5368 5369usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 5370ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 5371ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 5372 5373usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5374ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5375 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5376 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5377 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5378 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5379 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5380ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5381 value to program Travis register LVDS_CTRL_4 5382ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 5383 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5384 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5385 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5386ucLVDSPwrOnDEtoVARY_BL_in4Ms: 5387 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5388 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5389 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5390ucLVDSPwrOffVARY_BLtoDE_in4Ms: 5391 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5392 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5393 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5394ucLVDSPwrOffDEtoDIGON_in4Ms: 5395 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5396 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5397 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5398ucLVDSOffToOnDelay_in4Ms: 5399 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5400 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5401 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5402ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5403 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5404 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5405 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5406 5407ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5408 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5409 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5410 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5411ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5412 5413ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 5414 5415ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 5416ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 5417usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 5418usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 5419sExtDispConnInfo: Display connector information table provided to VBIOS 5420 5421**********************************************************************************************************************/ 5422 5423// this Table is used for Kaveri/Kabini APU 5424typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 5425{ 5426 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 5427 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 5428}ATOM_FUSION_SYSTEM_INFO_V2; 5429 5430 5431/**************************************************************************/ 5432// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 5433//Memory SS Info Table 5434//Define Memory Clock SS chip ID 5435#define ICS91719 1 5436#define ICS91720 2 5437 5438//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 5439typedef struct _ATOM_I2C_DATA_RECORD 5440{ 5441 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 5442 UCHAR ucI2CData[]; //I2C data in bytes, should be less than 16 bytes usually 5443}ATOM_I2C_DATA_RECORD; 5444 5445 5446//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 5447typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 5448{ 5449 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 5450 UCHAR ucSSChipID; //SS chip being used 5451 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 5452 UCHAR ucNumOfI2CDataRecords; //number of data block 5453 ATOM_I2C_DATA_RECORD asI2CData[]; 5454}ATOM_I2C_DEVICE_SETUP_INFO; 5455 5456//========================================================================================== 5457typedef struct _ATOM_ASIC_MVDD_INFO 5458{ 5459 ATOM_COMMON_TABLE_HEADER sHeader; 5460 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[]; 5461}ATOM_ASIC_MVDD_INFO; 5462 5463//========================================================================================== 5464#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5465 5466//========================================================================================== 5467/**************************************************************************/ 5468 5469typedef struct _ATOM_ASIC_SS_ASSIGNMENT 5470{ 5471 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5472 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5473 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5474 UCHAR ucClockIndication; //Indicate which clock source needs SS 5475 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5476 UCHAR ucReserved[2]; 5477}ATOM_ASIC_SS_ASSIGNMENT; 5478 5479//Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 5480//SS is not required or enabled if a match is not found. 5481#define ASIC_INTERNAL_MEMORY_SS 1 5482#define ASIC_INTERNAL_ENGINE_SS 2 5483#define ASIC_INTERNAL_UVD_SS 3 5484#define ASIC_INTERNAL_SS_ON_TMDS 4 5485#define ASIC_INTERNAL_SS_ON_HDMI 5 5486#define ASIC_INTERNAL_SS_ON_LVDS 6 5487#define ASIC_INTERNAL_SS_ON_DP 7 5488#define ASIC_INTERNAL_SS_ON_DCPLL 8 5489#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5490#define ASIC_INTERNAL_VCE_SS 10 5491#define ASIC_INTERNAL_GPUPLL_SS 11 5492 5493 5494typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5495{ 5496 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5497 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5498 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 5499 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5500 UCHAR ucClockIndication; //Indicate which clock source needs SS 5501 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5502 UCHAR ucReserved[2]; 5503}ATOM_ASIC_SS_ASSIGNMENT_V2; 5504 5505//ucSpreadSpectrumMode 5506//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 5507//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 5508//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 5509//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 5510//#define ATOM_INTERNAL_SS_MASK 0x00000000 5511//#define ATOM_EXTERNAL_SS_MASK 0x00000002 5512 5513typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 5514{ 5515 ATOM_COMMON_TABLE_HEADER sHeader; 5516 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 5517}ATOM_ASIC_INTERNAL_SS_INFO; 5518 5519typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 5520{ 5521 ATOM_COMMON_TABLE_HEADER sHeader; 5522 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[]; //this is point only. 5523}ATOM_ASIC_INTERNAL_SS_INFO_V2; 5524 5525typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 5526{ 5527 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5528 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5529 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5530 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5531 UCHAR ucClockIndication; //Indicate which clock source needs SS 5532 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5533 UCHAR ucReserved[2]; 5534}ATOM_ASIC_SS_ASSIGNMENT_V3; 5535 5536//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 5537#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 5538#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 5539#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 5540 5541typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 5542{ 5543 ATOM_COMMON_TABLE_HEADER sHeader; 5544 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[]; //this is pointer only. 5545}ATOM_ASIC_INTERNAL_SS_INFO_V3; 5546 5547 5548//==============================Scratch Pad Definition Portion=============================== 5549#define ATOM_DEVICE_CONNECT_INFO_DEF 0 5550#define ATOM_ROM_LOCATION_DEF 1 5551#define ATOM_TV_STANDARD_DEF 2 5552#define ATOM_ACTIVE_INFO_DEF 3 5553#define ATOM_LCD_INFO_DEF 4 5554#define ATOM_DOS_REQ_INFO_DEF 5 5555#define ATOM_ACC_CHANGE_INFO_DEF 6 5556#define ATOM_DOS_MODE_INFO_DEF 7 5557#define ATOM_I2C_CHANNEL_STATUS_DEF 8 5558#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 5559#define ATOM_INTERNAL_TIMER_DEF 10 5560 5561// BIOS_0_SCRATCH Definition 5562#define ATOM_S0_CRT1_MONO 0x00000001L 5563#define ATOM_S0_CRT1_COLOR 0x00000002L 5564#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 5565 5566#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 5567#define ATOM_S0_TV1_SVIDEO_A 0x00000008L 5568#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 5569 5570#define ATOM_S0_CV_A 0x00000010L 5571#define ATOM_S0_CV_DIN_A 0x00000020L 5572#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 5573 5574 5575#define ATOM_S0_CRT2_MONO 0x00000100L 5576#define ATOM_S0_CRT2_COLOR 0x00000200L 5577#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 5578 5579#define ATOM_S0_TV1_COMPOSITE 0x00000400L 5580#define ATOM_S0_TV1_SVIDEO 0x00000800L 5581#define ATOM_S0_TV1_SCART 0x00004000L 5582#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 5583 5584#define ATOM_S0_CV 0x00001000L 5585#define ATOM_S0_CV_DIN 0x00002000L 5586#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 5587 5588#define ATOM_S0_DFP1 0x00010000L 5589#define ATOM_S0_DFP2 0x00020000L 5590#define ATOM_S0_LCD1 0x00040000L 5591#define ATOM_S0_LCD2 0x00080000L 5592#define ATOM_S0_DFP6 0x00100000L 5593#define ATOM_S0_DFP3 0x00200000L 5594#define ATOM_S0_DFP4 0x00400000L 5595#define ATOM_S0_DFP5 0x00800000L 5596 5597#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 5598 5599#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 5600 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 5601 5602#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 5603#define ATOM_S0_THERMAL_STATE_SHIFT 26 5604 5605#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 5606#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 5607 5608#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 5609#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 5610#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 5611#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 5612 5613//Byte aligned definition for BIOS usage 5614#define ATOM_S0_CRT1_MONOb0 0x01 5615#define ATOM_S0_CRT1_COLORb0 0x02 5616#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 5617 5618#define ATOM_S0_TV1_COMPOSITEb0 0x04 5619#define ATOM_S0_TV1_SVIDEOb0 0x08 5620#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 5621 5622#define ATOM_S0_CVb0 0x10 5623#define ATOM_S0_CV_DINb0 0x20 5624#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 5625 5626#define ATOM_S0_CRT2_MONOb1 0x01 5627#define ATOM_S0_CRT2_COLORb1 0x02 5628#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 5629 5630#define ATOM_S0_TV1_COMPOSITEb1 0x04 5631#define ATOM_S0_TV1_SVIDEOb1 0x08 5632#define ATOM_S0_TV1_SCARTb1 0x40 5633#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 5634 5635#define ATOM_S0_CVb1 0x10 5636#define ATOM_S0_CV_DINb1 0x20 5637#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 5638 5639#define ATOM_S0_DFP1b2 0x01 5640#define ATOM_S0_DFP2b2 0x02 5641#define ATOM_S0_LCD1b2 0x04 5642#define ATOM_S0_LCD2b2 0x08 5643#define ATOM_S0_DFP6b2 0x10 5644#define ATOM_S0_DFP3b2 0x20 5645#define ATOM_S0_DFP4b2 0x40 5646#define ATOM_S0_DFP5b2 0x80 5647 5648 5649#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 5650#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 5651 5652#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 5653#define ATOM_S0_LCD1_SHIFT 18 5654 5655// BIOS_1_SCRATCH Definition 5656#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 5657#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 5658 5659// BIOS_2_SCRATCH Definition 5660#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 5661#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 5662#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 5663 5664#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 5665#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 5666#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 5667 5668#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 5669#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 5670 5671#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 5672#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 5673#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 5674#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 5675#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 5676#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 5677 5678 5679//Byte aligned definition for BIOS usage 5680#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 5681#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 5682#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 5683 5684#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 5685#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 5686#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 5687#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 5688#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 5689#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 5690 5691 5692// BIOS_3_SCRATCH Definition 5693#define ATOM_S3_CRT1_ACTIVE 0x00000001L 5694#define ATOM_S3_LCD1_ACTIVE 0x00000002L 5695#define ATOM_S3_TV1_ACTIVE 0x00000004L 5696#define ATOM_S3_DFP1_ACTIVE 0x00000008L 5697#define ATOM_S3_CRT2_ACTIVE 0x00000010L 5698#define ATOM_S3_LCD2_ACTIVE 0x00000020L 5699#define ATOM_S3_DFP6_ACTIVE 0x00000040L 5700#define ATOM_S3_DFP2_ACTIVE 0x00000080L 5701#define ATOM_S3_CV_ACTIVE 0x00000100L 5702#define ATOM_S3_DFP3_ACTIVE 0x00000200L 5703#define ATOM_S3_DFP4_ACTIVE 0x00000400L 5704#define ATOM_S3_DFP5_ACTIVE 0x00000800L 5705 5706#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 5707 5708#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 5709#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 5710 5711#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 5712#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 5713#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 5714#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 5715#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 5716#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 5717#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 5718#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 5719#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 5720#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 5721#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 5722#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 5723 5724#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 5725#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 5726//Below two definitions are not supported in pplib, but in the old powerplay in DAL 5727#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 5728#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 5729 5730//Byte aligned definition for BIOS usage 5731#define ATOM_S3_CRT1_ACTIVEb0 0x01 5732#define ATOM_S3_LCD1_ACTIVEb0 0x02 5733#define ATOM_S3_TV1_ACTIVEb0 0x04 5734#define ATOM_S3_DFP1_ACTIVEb0 0x08 5735#define ATOM_S3_CRT2_ACTIVEb0 0x10 5736#define ATOM_S3_LCD2_ACTIVEb0 0x20 5737#define ATOM_S3_DFP6_ACTIVEb0 0x40 5738#define ATOM_S3_DFP2_ACTIVEb0 0x80 5739#define ATOM_S3_CV_ACTIVEb1 0x01 5740#define ATOM_S3_DFP3_ACTIVEb1 0x02 5741#define ATOM_S3_DFP4_ACTIVEb1 0x04 5742#define ATOM_S3_DFP5_ACTIVEb1 0x08 5743 5744#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 5745 5746#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 5747#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 5748#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 5749#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 5750#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 5751#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 5752#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 5753#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 5754#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 5755#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 5756#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 5757#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 5758 5759#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 5760 5761// BIOS_4_SCRATCH Definition 5762#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 5763#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 5764#define ATOM_S4_LCD1_REFRESH_SHIFT 8 5765 5766//Byte aligned definition for BIOS usage 5767#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 5768#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 5769#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 5770 5771// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 5772#define ATOM_S5_DOS_REQ_CRT1b0 0x01 5773#define ATOM_S5_DOS_REQ_LCD1b0 0x02 5774#define ATOM_S5_DOS_REQ_TV1b0 0x04 5775#define ATOM_S5_DOS_REQ_DFP1b0 0x08 5776#define ATOM_S5_DOS_REQ_CRT2b0 0x10 5777#define ATOM_S5_DOS_REQ_LCD2b0 0x20 5778#define ATOM_S5_DOS_REQ_DFP6b0 0x40 5779#define ATOM_S5_DOS_REQ_DFP2b0 0x80 5780#define ATOM_S5_DOS_REQ_CVb1 0x01 5781#define ATOM_S5_DOS_REQ_DFP3b1 0x02 5782#define ATOM_S5_DOS_REQ_DFP4b1 0x04 5783#define ATOM_S5_DOS_REQ_DFP5b1 0x08 5784 5785#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 5786 5787#define ATOM_S5_DOS_REQ_CRT1 0x0001 5788#define ATOM_S5_DOS_REQ_LCD1 0x0002 5789#define ATOM_S5_DOS_REQ_TV1 0x0004 5790#define ATOM_S5_DOS_REQ_DFP1 0x0008 5791#define ATOM_S5_DOS_REQ_CRT2 0x0010 5792#define ATOM_S5_DOS_REQ_LCD2 0x0020 5793#define ATOM_S5_DOS_REQ_DFP6 0x0040 5794#define ATOM_S5_DOS_REQ_DFP2 0x0080 5795#define ATOM_S5_DOS_REQ_CV 0x0100 5796#define ATOM_S5_DOS_REQ_DFP3 0x0200 5797#define ATOM_S5_DOS_REQ_DFP4 0x0400 5798#define ATOM_S5_DOS_REQ_DFP5 0x0800 5799 5800#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 5801#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 5802#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 5803#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 5804#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 5805 (ATOM_S5_DOS_FORCE_CVb3<<8)) 5806 5807// BIOS_6_SCRATCH Definition 5808#define ATOM_S6_DEVICE_CHANGE 0x00000001L 5809#define ATOM_S6_SCALER_CHANGE 0x00000002L 5810#define ATOM_S6_LID_CHANGE 0x00000004L 5811#define ATOM_S6_DOCKING_CHANGE 0x00000008L 5812#define ATOM_S6_ACC_MODE 0x00000010L 5813#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 5814#define ATOM_S6_LID_STATE 0x00000040L 5815#define ATOM_S6_DOCK_STATE 0x00000080L 5816#define ATOM_S6_CRITICAL_STATE 0x00000100L 5817#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 5818#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 5819#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 5820#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 5821#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 5822 5823#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 5824#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 5825 5826#define ATOM_S6_ACC_REQ_CRT1 0x00010000L 5827#define ATOM_S6_ACC_REQ_LCD1 0x00020000L 5828#define ATOM_S6_ACC_REQ_TV1 0x00040000L 5829#define ATOM_S6_ACC_REQ_DFP1 0x00080000L 5830#define ATOM_S6_ACC_REQ_CRT2 0x00100000L 5831#define ATOM_S6_ACC_REQ_LCD2 0x00200000L 5832#define ATOM_S6_ACC_REQ_DFP6 0x00400000L 5833#define ATOM_S6_ACC_REQ_DFP2 0x00800000L 5834#define ATOM_S6_ACC_REQ_CV 0x01000000L 5835#define ATOM_S6_ACC_REQ_DFP3 0x02000000L 5836#define ATOM_S6_ACC_REQ_DFP4 0x04000000L 5837#define ATOM_S6_ACC_REQ_DFP5 0x08000000L 5838 5839#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 5840#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 5841#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 5842#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 5843#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 5844 5845//Byte aligned definition for BIOS usage 5846#define ATOM_S6_DEVICE_CHANGEb0 0x01 5847#define ATOM_S6_SCALER_CHANGEb0 0x02 5848#define ATOM_S6_LID_CHANGEb0 0x04 5849#define ATOM_S6_DOCKING_CHANGEb0 0x08 5850#define ATOM_S6_ACC_MODEb0 0x10 5851#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 5852#define ATOM_S6_LID_STATEb0 0x40 5853#define ATOM_S6_DOCK_STATEb0 0x80 5854#define ATOM_S6_CRITICAL_STATEb1 0x01 5855#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 5856#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 5857#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 5858#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 5859#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 5860 5861#define ATOM_S6_ACC_REQ_CRT1b2 0x01 5862#define ATOM_S6_ACC_REQ_LCD1b2 0x02 5863#define ATOM_S6_ACC_REQ_TV1b2 0x04 5864#define ATOM_S6_ACC_REQ_DFP1b2 0x08 5865#define ATOM_S6_ACC_REQ_CRT2b2 0x10 5866#define ATOM_S6_ACC_REQ_LCD2b2 0x20 5867#define ATOM_S6_ACC_REQ_DFP6b2 0x40 5868#define ATOM_S6_ACC_REQ_DFP2b2 0x80 5869#define ATOM_S6_ACC_REQ_CVb3 0x01 5870#define ATOM_S6_ACC_REQ_DFP3b3 0x02 5871#define ATOM_S6_ACC_REQ_DFP4b3 0x04 5872#define ATOM_S6_ACC_REQ_DFP5b3 0x08 5873 5874#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 5875#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 5876#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 5877#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 5878#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 5879 5880#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 5881#define ATOM_S6_SCALER_CHANGE_SHIFT 1 5882#define ATOM_S6_LID_CHANGE_SHIFT 2 5883#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 5884#define ATOM_S6_ACC_MODE_SHIFT 4 5885#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 5886#define ATOM_S6_LID_STATE_SHIFT 6 5887#define ATOM_S6_DOCK_STATE_SHIFT 7 5888#define ATOM_S6_CRITICAL_STATE_SHIFT 8 5889#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 5890#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 5891#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 5892#define ATOM_S6_REQ_SCALER_SHIFT 12 5893#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 5894#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 5895#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 5896#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 5897#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 5898#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 5899#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 5900 5901// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 5902#define ATOM_S7_DOS_MODE_TYPEb0 0x03 5903#define ATOM_S7_DOS_MODE_VGAb0 0x00 5904#define ATOM_S7_DOS_MODE_VESAb0 0x01 5905#define ATOM_S7_DOS_MODE_EXTb0 0x02 5906#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5907#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5908#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5909#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 5910#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 5911#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5912 5913#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 5914 5915// BIOS_8_SCRATCH Definition 5916#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 5917#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 5918 5919#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 5920#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 5921 5922// BIOS_9_SCRATCH Definition 5923#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 5924#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 5925#endif 5926#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 5927#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 5928#endif 5929#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 5930#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 5931#endif 5932#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 5933#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 5934#endif 5935 5936 5937#define ATOM_FLAG_SET 0x20 5938#define ATOM_FLAG_CLEAR 0 5939#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 5940#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 5941#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 5942#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 5943#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 5944 5945#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 5946#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 5947 5948#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 5949#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 5950#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 5951 5952#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 5953#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 5954#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 5955 5956#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 5957#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 5958 5959#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 5960#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 5961 5962#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 5963#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 5964 5965#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5966 5967#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5968 5969#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 5970#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 5971#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 5972#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 5973 5974/****************************************************************************/ 5975//Portion II: Definitions only used in Driver 5976/****************************************************************************/ 5977 5978// Macros used by driver 5979#ifdef __cplusplus 5980#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 5981 5982#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 5983#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 5984#else // not __cplusplus 5985#define GetIndexIntoMasterTable(MasterOrData, FieldName) (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName)/sizeof(USHORT)) 5986 5987#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 5988#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 5989#endif // __cplusplus 5990 5991#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 5992#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 5993 5994/****************************************************************************/ 5995//Portion III: Definitinos only used in VBIOS 5996/****************************************************************************/ 5997#define ATOM_DAC_SRC 0x80 5998#define ATOM_SRC_DAC1 0 5999#define ATOM_SRC_DAC2 0x80 6000 6001typedef struct _MEMORY_PLLINIT_PARAMETERS 6002{ 6003 ULONG ulTargetMemoryClock; //In 10Khz unit 6004 UCHAR ucAction; //not define yet 6005 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 6006 UCHAR ucFbDiv; //FB value 6007 UCHAR ucPostDiv; //Post div 6008}MEMORY_PLLINIT_PARAMETERS; 6009 6010#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 6011 6012 6013#define GPIO_PIN_WRITE 0x01 6014#define GPIO_PIN_READ 0x00 6015 6016typedef struct _GPIO_PIN_CONTROL_PARAMETERS 6017{ 6018 UCHAR ucGPIO_ID; //return value, read from GPIO pins 6019 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 6020 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 6021 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 6022}GPIO_PIN_CONTROL_PARAMETERS; 6023 6024typedef struct _ENABLE_SCALER_PARAMETERS 6025{ 6026 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 6027 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 6028 UCHAR ucTVStandard; // 6029 UCHAR ucPadding[1]; 6030}ENABLE_SCALER_PARAMETERS; 6031#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 6032 6033//ucEnable: 6034#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 6035#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 6036#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 6037#define SCALER_ENABLE_MULTITAP_MODE 3 6038 6039typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 6040{ 6041 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 6042 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 6043 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 6044 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 6045 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6046}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 6047 6048typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 6049{ 6050 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 6051 ENABLE_CRTC_PARAMETERS sReserved; 6052}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 6053 6054typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 6055{ 6056 USHORT usHight; // Image Hight 6057 USHORT usWidth; // Image Width 6058 UCHAR ucSurface; // Surface 1 or 2 6059 UCHAR ucPadding[3]; 6060}ENABLE_GRAPH_SURFACE_PARAMETERS; 6061 6062typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 6063{ 6064 USHORT usHight; // Image Hight 6065 USHORT usWidth; // Image Width 6066 UCHAR ucSurface; // Surface 1 or 2 6067 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6068 UCHAR ucPadding[2]; 6069}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 6070 6071typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 6072{ 6073 USHORT usHight; // Image Hight 6074 USHORT usWidth; // Image Width 6075 UCHAR ucSurface; // Surface 1 or 2 6076 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6077 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 6078}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 6079 6080typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 6081{ 6082 USHORT usHight; // Image Hight 6083 USHORT usWidth; // Image Width 6084 USHORT usGraphPitch; 6085 UCHAR ucColorDepth; 6086 UCHAR ucPixelFormat; 6087 UCHAR ucSurface; // Surface 1 or 2 6088 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6089 UCHAR ucModeType; 6090 UCHAR ucReserved; 6091}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 6092 6093// ucEnable 6094#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 6095#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 6096 6097typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 6098{ 6099 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 6100 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 6101}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 6102 6103typedef struct _MEMORY_CLEAN_UP_PARAMETERS 6104{ 6105 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address 6106 USHORT usMemorySize; //8Kb blocks aligned 6107}MEMORY_CLEAN_UP_PARAMETERS; 6108#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 6109 6110typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 6111{ 6112 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6113 USHORT usY_Size; 6114}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 6115 6116typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 6117{ 6118 union{ 6119 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6120 USHORT usSurface; 6121 }; 6122 USHORT usY_Size; 6123 USHORT usDispXStart; 6124 USHORT usDispYStart; 6125}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 6126 6127 6128typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 6129{ 6130 UCHAR ucLutId; 6131 UCHAR ucAction; 6132 USHORT usLutStartIndex; 6133 USHORT usLutLength; 6134 USHORT usLutOffsetInVram; 6135}PALETTE_DATA_CONTROL_PARAMETERS_V3; 6136 6137// ucAction: 6138#define PALETTE_DATA_AUTO_FILL 1 6139#define PALETTE_DATA_READ 2 6140#define PALETTE_DATA_WRITE 3 6141 6142 6143typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 6144{ 6145 UCHAR ucInterruptId; 6146 UCHAR ucServiceId; 6147 UCHAR ucStatus; 6148 UCHAR ucReserved; 6149}INTERRUPT_SERVICE_PARAMETER_V2; 6150 6151// ucInterruptId 6152#define HDP1_INTERRUPT_ID 1 6153#define HDP2_INTERRUPT_ID 2 6154#define HDP3_INTERRUPT_ID 3 6155#define HDP4_INTERRUPT_ID 4 6156#define HDP5_INTERRUPT_ID 5 6157#define HDP6_INTERRUPT_ID 6 6158#define SW_INTERRUPT_ID 11 6159 6160// ucAction 6161#define INTERRUPT_SERVICE_GEN_SW_INT 1 6162#define INTERRUPT_SERVICE_GET_STATUS 2 6163 6164 // ucStatus 6165#define INTERRUPT_STATUS__INT_TRIGGER 1 6166#define INTERRUPT_STATUS__HPD_HIGH 2 6167 6168typedef struct _INDIRECT_IO_ACCESS 6169{ 6170 ATOM_COMMON_TABLE_HEADER sHeader; 6171 UCHAR IOAccessSequence[256]; 6172} INDIRECT_IO_ACCESS; 6173 6174#define INDIRECT_READ 0x00 6175#define INDIRECT_WRITE 0x80 6176 6177#define INDIRECT_IO_MM 0 6178#define INDIRECT_IO_PLL 1 6179#define INDIRECT_IO_MC 2 6180#define INDIRECT_IO_PCIE 3 6181#define INDIRECT_IO_PCIEP 4 6182#define INDIRECT_IO_NBMISC 5 6183#define INDIRECT_IO_SMU 5 6184 6185#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 6186#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 6187#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 6188#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 6189#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 6190#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 6191#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 6192#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 6193#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 6194#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 6195#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 6196#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 6197 6198typedef struct _ATOM_OEM_INFO 6199{ 6200 ATOM_COMMON_TABLE_HEADER sHeader; 6201 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6202}ATOM_OEM_INFO; 6203 6204typedef struct _ATOM_TV_MODE 6205{ 6206 UCHAR ucVMode_Num; //Video mode number 6207 UCHAR ucTV_Mode_Num; //Internal TV mode number 6208}ATOM_TV_MODE; 6209 6210typedef struct _ATOM_BIOS_INT_TVSTD_MODE 6211{ 6212 ATOM_COMMON_TABLE_HEADER sHeader; 6213 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 6214 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 6215 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 6216 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6217 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6218}ATOM_BIOS_INT_TVSTD_MODE; 6219 6220 6221typedef struct _ATOM_TV_MODE_SCALER_PTR 6222{ 6223 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 6224 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 6225 UCHAR ucTV_Mode_Num; 6226}ATOM_TV_MODE_SCALER_PTR; 6227 6228typedef struct _ATOM_STANDARD_VESA_TIMING 6229{ 6230 ATOM_COMMON_TABLE_HEADER sHeader; 6231 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 6232}ATOM_STANDARD_VESA_TIMING; 6233 6234 6235typedef struct _ATOM_STD_FORMAT 6236{ 6237 USHORT usSTD_HDisp; 6238 USHORT usSTD_VDisp; 6239 USHORT usSTD_RefreshRate; 6240 USHORT usReserved; 6241}ATOM_STD_FORMAT; 6242 6243typedef struct _ATOM_VESA_TO_EXTENDED_MODE 6244{ 6245 USHORT usVESA_ModeNumber; 6246 USHORT usExtendedModeNumber; 6247}ATOM_VESA_TO_EXTENDED_MODE; 6248 6249typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 6250{ 6251 ATOM_COMMON_TABLE_HEADER sHeader; 6252 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 6253}ATOM_VESA_TO_INTENAL_MODE_LUT; 6254 6255/*************** ATOM Memory Related Data Structure ***********************/ 6256typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 6257 UCHAR ucMemoryType; 6258 UCHAR ucMemoryVendor; 6259 UCHAR ucAdjMCId; 6260 UCHAR ucDynClkId; 6261 ULONG ulDllResetClkRange; 6262}ATOM_MEMORY_VENDOR_BLOCK; 6263 6264 6265typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 6266#if ATOM_BIG_ENDIAN 6267 ULONG ucMemBlkId:8; 6268 ULONG ulMemClockRange:24; 6269#else 6270 ULONG ulMemClockRange:24; 6271 ULONG ucMemBlkId:8; 6272#endif 6273}ATOM_MEMORY_SETTING_ID_CONFIG; 6274 6275typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 6276{ 6277 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 6278 ULONG ulAccess; 6279}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 6280 6281 6282typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 6283 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 6284 ULONG aulMemData[]; 6285}ATOM_MEMORY_SETTING_DATA_BLOCK; 6286 6287 6288typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 6289 USHORT usRegIndex; // MC register index 6290 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 6291}ATOM_INIT_REG_INDEX_FORMAT; 6292 6293 6294typedef struct _ATOM_INIT_REG_BLOCK{ 6295 USHORT usRegIndexTblSize; //size of asRegIndexBuf 6296 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 6297 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 6298 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 6299}ATOM_INIT_REG_BLOCK; 6300 6301#define END_OF_REG_INDEX_BLOCK 0x0ffff 6302#define END_OF_REG_DATA_BLOCK 0x00000000 6303#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 6304#define CLOCK_RANGE_HIGHEST 0x00ffffff 6305 6306#define VALUE_DWORD SIZEOF ULONG 6307#define VALUE_SAME_AS_ABOVE 0 6308#define VALUE_MASK_DWORD 0x84 6309 6310#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 6311#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 6312#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 6313//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 6314#define ACCESS_PLACEHOLDER 0x80 6315 6316typedef struct _ATOM_MC_INIT_PARAM_TABLE 6317{ 6318 ATOM_COMMON_TABLE_HEADER sHeader; 6319 USHORT usAdjustARB_SEQDataOffset; 6320 USHORT usMCInitMemTypeTblOffset; 6321 USHORT usMCInitCommonTblOffset; 6322 USHORT usMCInitPowerDownTblOffset; 6323 ULONG ulARB_SEQDataBuf[32]; 6324 ATOM_INIT_REG_BLOCK asMCInitMemType; 6325 ATOM_INIT_REG_BLOCK asMCInitCommon; 6326}ATOM_MC_INIT_PARAM_TABLE; 6327 6328 6329#define _4Mx16 0x2 6330#define _4Mx32 0x3 6331#define _8Mx16 0x12 6332#define _8Mx32 0x13 6333#define _16Mx16 0x22 6334#define _16Mx32 0x23 6335#define _32Mx16 0x32 6336#define _32Mx32 0x33 6337#define _64Mx8 0x41 6338#define _64Mx16 0x42 6339#define _64Mx32 0x43 6340#define _128Mx8 0x51 6341#define _128Mx16 0x52 6342#define _128Mx32 0x53 6343#define _256Mx8 0x61 6344#define _256Mx16 0x62 6345#define _512Mx8 0x71 6346 6347#define SAMSUNG 0x1 6348#define INFINEON 0x2 6349#define ELPIDA 0x3 6350#define ETRON 0x4 6351#define NANYA 0x5 6352#define HYNIX 0x6 6353#define MOSEL 0x7 6354#define WINBOND 0x8 6355#define ESMT 0x9 6356#define MICRON 0xF 6357 6358#define QIMONDA INFINEON 6359#define PROMOS MOSEL 6360#define KRETON INFINEON 6361#define ELIXIR NANYA 6362#define MEZZA ELPIDA 6363 6364 6365/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 6366 6367#define UCODE_ROM_START_ADDRESS 0x1b800 6368#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 6369 6370//uCode block header for reference 6371 6372typedef struct _MCuCodeHeader 6373{ 6374 ULONG ulSignature; 6375 UCHAR ucRevision; 6376 UCHAR ucChecksum; 6377 UCHAR ucReserved1; 6378 UCHAR ucReserved2; 6379 USHORT usParametersLength; 6380 USHORT usUCodeLength; 6381 USHORT usReserved1; 6382 USHORT usReserved2; 6383} MCuCodeHeader; 6384 6385////////////////////////////////////////////////////////////////////////////////// 6386 6387#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 6388 6389#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 6390typedef struct _ATOM_VRAM_MODULE_V1 6391{ 6392 ULONG ulReserved; 6393 USHORT usEMRSValue; 6394 USHORT usMRSValue; 6395 USHORT usReserved; 6396 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6397 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 6398 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 6399 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6400 UCHAR ucRow; // Number of Row,in power of 2; 6401 UCHAR ucColumn; // Number of Column,in power of 2; 6402 UCHAR ucBank; // Nunber of Bank; 6403 UCHAR ucRank; // Number of Rank, in power of 2 6404 UCHAR ucChannelNum; // Number of channel; 6405 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6406 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6407 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6408 UCHAR ucReserved[2]; 6409}ATOM_VRAM_MODULE_V1; 6410 6411 6412typedef struct _ATOM_VRAM_MODULE_V2 6413{ 6414 ULONG ulReserved; 6415 ULONG ulFlags; // To enable/disable functionalities based on memory type 6416 ULONG ulEngineClock; // Override of default engine clock for particular memory type 6417 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 6418 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6419 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6420 USHORT usEMRSValue; 6421 USHORT usMRSValue; 6422 USHORT usReserved; 6423 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6424 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6425 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6426 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6427 UCHAR ucRow; // Number of Row,in power of 2; 6428 UCHAR ucColumn; // Number of Column,in power of 2; 6429 UCHAR ucBank; // Nunber of Bank; 6430 UCHAR ucRank; // Number of Rank, in power of 2 6431 UCHAR ucChannelNum; // Number of channel; 6432 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6433 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6434 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6435 UCHAR ucRefreshRateFactor; 6436 UCHAR ucReserved[3]; 6437}ATOM_VRAM_MODULE_V2; 6438 6439 6440typedef struct _ATOM_MEMORY_TIMING_FORMAT 6441{ 6442 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6443 union{ 6444 USHORT usMRS; // mode register 6445 USHORT usDDR3_MR0; 6446 }; 6447 union{ 6448 USHORT usEMRS; // extended mode register 6449 USHORT usDDR3_MR1; 6450 }; 6451 UCHAR ucCL; // CAS latency 6452 UCHAR ucWL; // WRITE Latency 6453 UCHAR uctRAS; // tRAS 6454 UCHAR uctRC; // tRC 6455 UCHAR uctRFC; // tRFC 6456 UCHAR uctRCDR; // tRCDR 6457 UCHAR uctRCDW; // tRCDW 6458 UCHAR uctRP; // tRP 6459 UCHAR uctRRD; // tRRD 6460 UCHAR uctWR; // tWR 6461 UCHAR uctWTR; // tWTR 6462 UCHAR uctPDIX; // tPDIX 6463 UCHAR uctFAW; // tFAW 6464 UCHAR uctAOND; // tAOND 6465 union 6466 { 6467 struct { 6468 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6469 UCHAR ucReserved; 6470 }; 6471 USHORT usDDR3_MR2; 6472 }; 6473}ATOM_MEMORY_TIMING_FORMAT; 6474 6475 6476typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 6477{ 6478 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6479 USHORT usMRS; // mode register 6480 USHORT usEMRS; // extended mode register 6481 UCHAR ucCL; // CAS latency 6482 UCHAR ucWL; // WRITE Latency 6483 UCHAR uctRAS; // tRAS 6484 UCHAR uctRC; // tRC 6485 UCHAR uctRFC; // tRFC 6486 UCHAR uctRCDR; // tRCDR 6487 UCHAR uctRCDW; // tRCDW 6488 UCHAR uctRP; // tRP 6489 UCHAR uctRRD; // tRRD 6490 UCHAR uctWR; // tWR 6491 UCHAR uctWTR; // tWTR 6492 UCHAR uctPDIX; // tPDIX 6493 UCHAR uctFAW; // tFAW 6494 UCHAR uctAOND; // tAOND 6495 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6496////////////////////////////////////GDDR parameters/////////////////////////////////// 6497 UCHAR uctCCDL; // 6498 UCHAR uctCRCRL; // 6499 UCHAR uctCRCWL; // 6500 UCHAR uctCKE; // 6501 UCHAR uctCKRSE; // 6502 UCHAR uctCKRSX; // 6503 UCHAR uctFAW32; // 6504 UCHAR ucMR5lo; // 6505 UCHAR ucMR5hi; // 6506 UCHAR ucTerminator; 6507}ATOM_MEMORY_TIMING_FORMAT_V1; 6508 6509typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 6510{ 6511 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6512 USHORT usMRS; // mode register 6513 USHORT usEMRS; // extended mode register 6514 UCHAR ucCL; // CAS latency 6515 UCHAR ucWL; // WRITE Latency 6516 UCHAR uctRAS; // tRAS 6517 UCHAR uctRC; // tRC 6518 UCHAR uctRFC; // tRFC 6519 UCHAR uctRCDR; // tRCDR 6520 UCHAR uctRCDW; // tRCDW 6521 UCHAR uctRP; // tRP 6522 UCHAR uctRRD; // tRRD 6523 UCHAR uctWR; // tWR 6524 UCHAR uctWTR; // tWTR 6525 UCHAR uctPDIX; // tPDIX 6526 UCHAR uctFAW; // tFAW 6527 UCHAR uctAOND; // tAOND 6528 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6529////////////////////////////////////GDDR parameters/////////////////////////////////// 6530 UCHAR uctCCDL; // 6531 UCHAR uctCRCRL; // 6532 UCHAR uctCRCWL; // 6533 UCHAR uctCKE; // 6534 UCHAR uctCKRSE; // 6535 UCHAR uctCKRSX; // 6536 UCHAR uctFAW32; // 6537 UCHAR ucMR4lo; // 6538 UCHAR ucMR4hi; // 6539 UCHAR ucMR5lo; // 6540 UCHAR ucMR5hi; // 6541 UCHAR ucTerminator; 6542 UCHAR ucReserved; 6543}ATOM_MEMORY_TIMING_FORMAT_V2; 6544 6545typedef struct _ATOM_MEMORY_FORMAT 6546{ 6547 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 6548 union{ 6549 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6550 USHORT usDDR3_Reserved; // Not used for DDR3 memory 6551 }; 6552 union{ 6553 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6554 USHORT usDDR3_MR3; // Used for DDR3 memory 6555 }; 6556 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6557 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6558 UCHAR ucRow; // Number of Row,in power of 2; 6559 UCHAR ucColumn; // Number of Column,in power of 2; 6560 UCHAR ucBank; // Nunber of Bank; 6561 UCHAR ucRank; // Number of Rank, in power of 2 6562 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 6563 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 6564 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 6565 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6566 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 6567 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 6568 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 6569}ATOM_MEMORY_FORMAT; 6570 6571 6572typedef struct _ATOM_VRAM_MODULE_V3 6573{ 6574 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 6575 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 6576 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 6577 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 6578 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6579 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 6580 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 6581 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 6582 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6583 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6584 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 6585}ATOM_VRAM_MODULE_V3; 6586 6587 6588//ATOM_VRAM_MODULE_V3.ucNPL_RT 6589#define NPL_RT_MASK 0x0f 6590#define BATTERY_ODT_MASK 0xc0 6591 6592#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 6593 6594typedef struct _ATOM_VRAM_MODULE_V4 6595{ 6596 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6597 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6598 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6599 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6600 USHORT usReserved; 6601 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6602 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6603 UCHAR ucChannelNum; // Number of channels present in this module config 6604 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6605 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6606 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6607 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6608 UCHAR ucVREFI; // board dependent parameter 6609 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6610 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6611 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6612 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6613 UCHAR ucReserved[3]; 6614 6615//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6616 union{ 6617 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6618 USHORT usDDR3_Reserved; 6619 }; 6620 union{ 6621 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6622 USHORT usDDR3_MR3; // Used for DDR3 memory 6623 }; 6624 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6625 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6626 UCHAR ucReserved2[2]; 6627 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6628}ATOM_VRAM_MODULE_V4; 6629 6630#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 6631#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 6632#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 6633#define VRAM_MODULE_V4_MISC_BL8 0x4 6634#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 6635 6636typedef struct _ATOM_VRAM_MODULE_V5 6637{ 6638 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6639 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6640 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6641 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6642 USHORT usReserved; 6643 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6644 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6645 UCHAR ucChannelNum; // Number of channels present in this module config 6646 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6647 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6648 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6649 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6650 UCHAR ucVREFI; // board dependent parameter 6651 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6652 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6653 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6654 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6655 UCHAR ucReserved[3]; 6656 6657//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6658 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6659 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6660 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6661 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6662 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6663 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6664 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6665}ATOM_VRAM_MODULE_V5; 6666 6667typedef struct _ATOM_VRAM_MODULE_V6 6668{ 6669 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6670 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6671 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6672 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6673 USHORT usReserved; 6674 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6675 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6676 UCHAR ucChannelNum; // Number of channels present in this module config 6677 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6678 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6679 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6680 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6681 UCHAR ucVREFI; // board dependent parameter 6682 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6683 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6684 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6685 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6686 UCHAR ucReserved[3]; 6687 6688//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6689 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6690 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6691 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6692 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6693 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6694 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6695 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6696}ATOM_VRAM_MODULE_V6; 6697 6698typedef struct _ATOM_VRAM_MODULE_V7 6699{ 6700// Design Specific Values 6701 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 6702 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 6703 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6704 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 6705 UCHAR ucExtMemoryID; // Current memory module ID 6706 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 6707 UCHAR ucChannelNum; // Number of mem. channels supported in this module 6708 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 6709 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6710 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. 6711 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 6712 UCHAR ucVREFI; // Not used. 6713 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 6714 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6715 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6716 USHORT usSEQSettingOffset; 6717 UCHAR ucReserved; 6718// Memory Module specific values 6719 USHORT usEMRS2Value; // EMRS2/MR2 Value. 6720 USHORT usEMRS3Value; // EMRS3/MR3 Value. 6721 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 6722 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6723 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 6724 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6725 char strMemPNString[20]; // part number end with '0'. 6726}ATOM_VRAM_MODULE_V7; 6727 6728typedef struct _ATOM_VRAM_INFO_V2 6729{ 6730 ATOM_COMMON_TABLE_HEADER sHeader; 6731 UCHAR ucNumOfVRAMModule; 6732 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6733}ATOM_VRAM_INFO_V2; 6734 6735typedef struct _ATOM_VRAM_INFO_V3 6736{ 6737 ATOM_COMMON_TABLE_HEADER sHeader; 6738 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6739 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6740 USHORT usRerseved; 6741 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 6742 UCHAR ucNumOfVRAMModule; 6743 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6744 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6745 // ATOM_INIT_REG_BLOCK aMemAdjust; 6746}ATOM_VRAM_INFO_V3; 6747 6748#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 6749 6750typedef struct _ATOM_VRAM_INFO_V4 6751{ 6752 ATOM_COMMON_TABLE_HEADER sHeader; 6753 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6754 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6755 USHORT usRerseved; 6756 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 6757 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 6758 UCHAR ucReservde[4]; 6759 UCHAR ucNumOfVRAMModule; 6760 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6761 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6762 // ATOM_INIT_REG_BLOCK aMemAdjust; 6763}ATOM_VRAM_INFO_V4; 6764 6765typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 6766{ 6767 ATOM_COMMON_TABLE_HEADER sHeader; 6768 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6769 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6770 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 6771 USHORT usReserved[3]; 6772 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 6773 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 6774 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 6775 UCHAR ucReserved; 6776 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6777}ATOM_VRAM_INFO_HEADER_V2_1; 6778 6779 6780typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 6781{ 6782 ATOM_COMMON_TABLE_HEADER sHeader; 6783 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 6784}ATOM_VRAM_GPIO_DETECTION_INFO; 6785 6786 6787typedef struct _ATOM_MEMORY_TRAINING_INFO 6788{ 6789 ATOM_COMMON_TABLE_HEADER sHeader; 6790 UCHAR ucTrainingLoop; 6791 UCHAR ucReserved[3]; 6792 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 6793}ATOM_MEMORY_TRAINING_INFO; 6794 6795 6796typedef struct SW_I2C_CNTL_DATA_PARAMETERS 6797{ 6798 UCHAR ucControl; 6799 UCHAR ucData; 6800 UCHAR ucSatus; 6801 UCHAR ucTemp; 6802} SW_I2C_CNTL_DATA_PARAMETERS; 6803 6804#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 6805 6806typedef struct _SW_I2C_IO_DATA_PARAMETERS 6807{ 6808 USHORT GPIO_Info; 6809 UCHAR ucAct; 6810 UCHAR ucData; 6811 } SW_I2C_IO_DATA_PARAMETERS; 6812 6813#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 6814 6815/****************************SW I2C CNTL DEFINITIONS**********************/ 6816#define SW_I2C_IO_RESET 0 6817#define SW_I2C_IO_GET 1 6818#define SW_I2C_IO_DRIVE 2 6819#define SW_I2C_IO_SET 3 6820#define SW_I2C_IO_START 4 6821 6822#define SW_I2C_IO_CLOCK 0 6823#define SW_I2C_IO_DATA 0x80 6824 6825#define SW_I2C_IO_ZERO 0 6826#define SW_I2C_IO_ONE 0x100 6827 6828#define SW_I2C_CNTL_READ 0 6829#define SW_I2C_CNTL_WRITE 1 6830#define SW_I2C_CNTL_START 2 6831#define SW_I2C_CNTL_STOP 3 6832#define SW_I2C_CNTL_OPEN 4 6833#define SW_I2C_CNTL_CLOSE 5 6834#define SW_I2C_CNTL_WRITE1BIT 6 6835 6836//==============================VESA definition Portion=============================== 6837#define VESA_OEM_PRODUCT_REV "01.00" 6838#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 6839#define VESA_MODE_WIN_ATTRIBUTE 7 6840#define VESA_WIN_SIZE 64 6841 6842typedef struct _PTR_32_BIT_STRUCTURE 6843{ 6844 USHORT Offset16; 6845 USHORT Segment16; 6846} PTR_32_BIT_STRUCTURE; 6847 6848typedef union _PTR_32_BIT_UNION 6849{ 6850 PTR_32_BIT_STRUCTURE SegmentOffset; 6851 ULONG Ptr32_Bit; 6852} PTR_32_BIT_UNION; 6853 6854typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 6855{ 6856 UCHAR VbeSignature[4]; 6857 USHORT VbeVersion; 6858 PTR_32_BIT_UNION OemStringPtr; 6859 UCHAR Capabilities[4]; 6860 PTR_32_BIT_UNION VideoModePtr; 6861 USHORT TotalMemory; 6862} VBE_1_2_INFO_BLOCK_UPDATABLE; 6863 6864 6865typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 6866{ 6867 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 6868 USHORT OemSoftRev; 6869 PTR_32_BIT_UNION OemVendorNamePtr; 6870 PTR_32_BIT_UNION OemProductNamePtr; 6871 PTR_32_BIT_UNION OemProductRevPtr; 6872} VBE_2_0_INFO_BLOCK_UPDATABLE; 6873 6874typedef union _VBE_VERSION_UNION 6875{ 6876 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 6877 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 6878} VBE_VERSION_UNION; 6879 6880typedef struct _VBE_INFO_BLOCK 6881{ 6882 VBE_VERSION_UNION UpdatableVBE_Info; 6883 UCHAR Reserved[222]; 6884 UCHAR OemData[256]; 6885} VBE_INFO_BLOCK; 6886 6887typedef struct _VBE_FP_INFO 6888{ 6889 USHORT HSize; 6890 USHORT VSize; 6891 USHORT FPType; 6892 UCHAR RedBPP; 6893 UCHAR GreenBPP; 6894 UCHAR BlueBPP; 6895 UCHAR ReservedBPP; 6896 ULONG RsvdOffScrnMemSize; 6897 ULONG RsvdOffScrnMEmPtr; 6898 UCHAR Reserved[14]; 6899} VBE_FP_INFO; 6900 6901typedef struct _VESA_MODE_INFO_BLOCK 6902{ 6903// Mandatory information for all VBE revisions 6904 USHORT ModeAttributes; // dw ? ; mode attributes 6905 UCHAR WinAAttributes; // db ? ; window A attributes 6906 UCHAR WinBAttributes; // db ? ; window B attributes 6907 USHORT WinGranularity; // dw ? ; window granularity 6908 USHORT WinSize; // dw ? ; window size 6909 USHORT WinASegment; // dw ? ; window A start segment 6910 USHORT WinBSegment; // dw ? ; window B start segment 6911 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 6912 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 6913 6914//; Mandatory information for VBE 1.2 and above 6915 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 6916 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 6917 UCHAR XCharSize; // db ? ; character cell width in pixels 6918 UCHAR YCharSize; // db ? ; character cell height in pixels 6919 UCHAR NumberOfPlanes; // db ? ; number of memory planes 6920 UCHAR BitsPerPixel; // db ? ; bits per pixel 6921 UCHAR NumberOfBanks; // db ? ; number of banks 6922 UCHAR MemoryModel; // db ? ; memory model type 6923 UCHAR BankSize; // db ? ; bank size in KB 6924 UCHAR NumberOfImagePages;// db ? ; number of images 6925 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 6926 6927//; Direct Color fields(required for direct/6 and YUV/7 memory models) 6928 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 6929 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 6930 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 6931 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 6932 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 6933 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 6934 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 6935 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 6936 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 6937 6938//; Mandatory information for VBE 2.0 and above 6939 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 6940 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 6941 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 6942 6943//; Mandatory information for VBE 3.0 and above 6944 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 6945 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 6946 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 6947 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 6948 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 6949 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 6950 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 6951 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 6952 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 6953 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 6954 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 6955 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 6956 UCHAR Reserved; // db 190 dup (0) 6957} VESA_MODE_INFO_BLOCK; 6958 6959// BIOS function CALLS 6960#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 6961#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 6962#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 6963#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 6964#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 6965#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 6966#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 6967#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 6968#define ATOM_BIOS_FUNCTION_STV_STD 0x16 6969#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 6970#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 6971 6972#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 6973#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 6974#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 6975#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 6976#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 6977#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 6978#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 6979 6980#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 6981#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 6982#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 6983#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 6984#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 6985#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 6986#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 6987#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 6988#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 6989#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 6990 6991 6992#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 6993#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 6994#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 6995#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 6996#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 6997#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 6998#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 6999#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 7000 7001#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 7002#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 7003#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 7004 7005// structure used for VBIOS only 7006 7007//DispOutInfoTable 7008typedef struct _ASIC_TRANSMITTER_INFO 7009{ 7010 USHORT usTransmitterObjId; 7011 USHORT usSupportDevice; 7012 UCHAR ucTransmitterCmdTblId; 7013 UCHAR ucConfig; 7014 UCHAR ucEncoderID; //available 1st encoder ( default ) 7015 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 7016 UCHAR uc2ndEncoderID; 7017 UCHAR ucReserved; 7018}ASIC_TRANSMITTER_INFO; 7019 7020#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 7021#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 7022#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 7023#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 7024#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 7025#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 7026#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 7027#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 7028#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 7029 7030typedef struct _ASIC_ENCODER_INFO 7031{ 7032 UCHAR ucEncoderID; 7033 UCHAR ucEncoderConfig; 7034 USHORT usEncoderCmdTblId; 7035}ASIC_ENCODER_INFO; 7036 7037typedef struct _ATOM_DISP_OUT_INFO 7038{ 7039 ATOM_COMMON_TABLE_HEADER sHeader; 7040 USHORT ptrTransmitterInfo; 7041 USHORT ptrEncoderInfo; 7042 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7043 ASIC_ENCODER_INFO asEncoderInfo[1]; 7044}ATOM_DISP_OUT_INFO; 7045 7046typedef struct _ATOM_DISP_OUT_INFO_V2 7047{ 7048 ATOM_COMMON_TABLE_HEADER sHeader; 7049 USHORT ptrTransmitterInfo; 7050 USHORT ptrEncoderInfo; 7051 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7052 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7053 ASIC_ENCODER_INFO asEncoderInfo[1]; 7054}ATOM_DISP_OUT_INFO_V2; 7055 7056 7057typedef struct _ATOM_DISP_CLOCK_ID { 7058 UCHAR ucPpllId; 7059 UCHAR ucPpllAttribute; 7060}ATOM_DISP_CLOCK_ID; 7061 7062// ucPpllAttribute 7063#define CLOCK_SOURCE_SHAREABLE 0x01 7064#define CLOCK_SOURCE_DP_MODE 0x02 7065#define CLOCK_SOURCE_NONE_DP_MODE 0x04 7066 7067//DispOutInfoTable 7068typedef struct _ASIC_TRANSMITTER_INFO_V2 7069{ 7070 USHORT usTransmitterObjId; 7071 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 7072 UCHAR ucTransmitterCmdTblId; 7073 UCHAR ucConfig; 7074 UCHAR ucEncoderID; // available 1st encoder ( default ) 7075 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 7076 UCHAR uc2ndEncoderID; 7077 UCHAR ucReserved; 7078}ASIC_TRANSMITTER_INFO_V2; 7079 7080typedef struct _ATOM_DISP_OUT_INFO_V3 7081{ 7082 ATOM_COMMON_TABLE_HEADER sHeader; 7083 USHORT ptrTransmitterInfo; 7084 USHORT ptrEncoderInfo; 7085 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7086 USHORT usReserved; 7087 UCHAR ucDCERevision; 7088 UCHAR ucMaxDispEngineNum; 7089 UCHAR ucMaxActiveDispEngineNum; 7090 UCHAR ucMaxPPLLNum; 7091 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 7092 UCHAR ucDispCaps; 7093 UCHAR ucReserved[2]; 7094 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[]; // for alligment only 7095}ATOM_DISP_OUT_INFO_V3; 7096 7097//ucDispCaps 7098#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 7099#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 7100 7101typedef enum CORE_REF_CLK_SOURCE{ 7102 CLOCK_SRC_XTALIN=0, 7103 CLOCK_SRC_XO_IN=1, 7104 CLOCK_SRC_XO_IN2=2, 7105}CORE_REF_CLK_SOURCE; 7106 7107// DispDevicePriorityInfo 7108typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 7109{ 7110 ATOM_COMMON_TABLE_HEADER sHeader; 7111 USHORT asDevicePriority[16]; 7112}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 7113 7114//ProcessAuxChannelTransactionTable 7115typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7116{ 7117 USHORT lpAuxRequest; 7118 USHORT lpDataOut; 7119 UCHAR ucChannelID; 7120 union 7121 { 7122 UCHAR ucReplyStatus; 7123 UCHAR ucDelay; 7124 }; 7125 UCHAR ucDataOutLen; 7126 UCHAR ucReserved; 7127}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 7128 7129//ProcessAuxChannelTransactionTable 7130typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 7131{ 7132 USHORT lpAuxRequest; 7133 USHORT lpDataOut; 7134 UCHAR ucChannelID; 7135 union 7136 { 7137 UCHAR ucReplyStatus; 7138 UCHAR ucDelay; 7139 }; 7140 UCHAR ucDataOutLen; 7141 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 7142}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 7143 7144#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7145 7146//GetSinkType 7147 7148typedef struct _DP_ENCODER_SERVICE_PARAMETERS 7149{ 7150 USHORT ucLinkClock; 7151 union 7152 { 7153 UCHAR ucConfig; // for DP training command 7154 UCHAR ucI2cId; // use for GET_SINK_TYPE command 7155 }; 7156 UCHAR ucAction; 7157 UCHAR ucStatus; 7158 UCHAR ucLaneNum; 7159 UCHAR ucReserved[2]; 7160}DP_ENCODER_SERVICE_PARAMETERS; 7161 7162// ucAction 7163#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 7164/* obsolete */ 7165#define ATOM_DP_ACTION_TRAINING_START 0x02 7166#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 7167#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 7168#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 7169#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 7170#define ATOM_DP_ACTION_BLANKING 0x07 7171 7172// ucConfig 7173#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 7174#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 7175#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 7176#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 7177#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 7178#define ATOM_DP_CONFIG_LINK_A 0x00 7179#define ATOM_DP_CONFIG_LINK_B 0x04 7180/* /obselete */ 7181#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 7182 7183 7184typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 7185{ 7186 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7187 UCHAR ucAuxId; 7188 UCHAR ucAction; 7189 UCHAR ucSinkType; // Iput and Output parameters. 7190 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7191 UCHAR ucReserved[2]; 7192}DP_ENCODER_SERVICE_PARAMETERS_V2; 7193 7194typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 7195{ 7196 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 7197 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 7198}DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 7199 7200// ucAction 7201#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 7202#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 7203 7204 7205// DP_TRAINING_TABLE 7206#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 7207#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 7208#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 7209#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 7210#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 7211#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 7212#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 7213#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 7214#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 7215#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 7216#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 7217#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 7218#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 7219 7220typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7221{ 7222 UCHAR ucI2CSpeed; 7223 union 7224 { 7225 UCHAR ucRegIndex; 7226 UCHAR ucStatus; 7227 }; 7228 USHORT lpI2CDataOut; 7229 UCHAR ucFlag; 7230 UCHAR ucTransBytes; 7231 UCHAR ucSlaveAddr; 7232 UCHAR ucLineNumber; 7233}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 7234 7235#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7236 7237//ucFlag 7238#define HW_I2C_WRITE 1 7239#define HW_I2C_READ 0 7240#define I2C_2BYTE_ADDR 0x02 7241 7242/****************************************************************************/ 7243// Structures used by HW_Misc_OperationTable 7244/****************************************************************************/ 7245typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 7246{ 7247 UCHAR ucCmd; // Input: To tell which action to take 7248 UCHAR ucReserved[3]; 7249 ULONG ulReserved; 7250}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 7251 7252typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 7253{ 7254 UCHAR ucReturnCode; // Output: Return value base on action was taken 7255 UCHAR ucReserved[3]; 7256 ULONG ulReserved; 7257}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 7258 7259// Actions code 7260#define ATOM_GET_SDI_SUPPORT 0xF0 7261 7262// Return code 7263#define ATOM_UNKNOWN_CMD 0 7264#define ATOM_FEATURE_NOT_SUPPORTED 1 7265#define ATOM_FEATURE_SUPPORTED 2 7266 7267typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 7268{ 7269 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 7270 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 7271}ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 7272 7273/****************************************************************************/ 7274 7275typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 7276{ 7277 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 7278 UCHAR ucReserved[3]; 7279}SET_HWBLOCK_INSTANCE_PARAMETER_V2; 7280 7281#define HWBLKINST_INSTANCE_MASK 0x07 7282#define HWBLKINST_HWBLK_MASK 0xF0 7283#define HWBLKINST_HWBLK_SHIFT 0x04 7284 7285//ucHWBlock 7286#define SELECT_DISP_ENGINE 0 7287#define SELECT_DISP_PLL 1 7288#define SELECT_DCIO_UNIPHY_LINK0 2 7289#define SELECT_DCIO_UNIPHY_LINK1 3 7290#define SELECT_DCIO_IMPCAL 4 7291#define SELECT_DCIO_DIG 6 7292#define SELECT_CRTC_PIXEL_RATE 7 7293#define SELECT_VGA_BLK 8 7294 7295// DIGTransmitterInfoTable structure used to program UNIPHY settings 7296typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 7297 ATOM_COMMON_TABLE_HEADER sHeader; 7298 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7299 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7300 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7301 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7302 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7303}DIG_TRANSMITTER_INFO_HEADER_V3_1; 7304 7305typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 7306 ATOM_COMMON_TABLE_HEADER sHeader; 7307 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7308 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7309 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7310 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7311 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7312 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7313 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 7314}DIG_TRANSMITTER_INFO_HEADER_V3_2; 7315 7316typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 7317 USHORT usRegisterIndex; 7318 UCHAR ucStartBit; 7319 UCHAR ucEndBit; 7320}CLOCK_CONDITION_REGESTER_INFO; 7321 7322typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 7323 USHORT usMaxClockFreq; 7324 UCHAR ucEncodeMode; 7325 UCHAR ucPhySel; 7326 ULONG ulAnalogSetting[]; 7327}CLOCK_CONDITION_SETTING_ENTRY; 7328 7329typedef struct _CLOCK_CONDITION_SETTING_INFO{ 7330 USHORT usEntrySize; 7331 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[]; 7332}CLOCK_CONDITION_SETTING_INFO; 7333 7334typedef struct _PHY_CONDITION_REG_VAL{ 7335 ULONG ulCondition; 7336 ULONG ulRegVal; 7337}PHY_CONDITION_REG_VAL; 7338 7339typedef struct _PHY_CONDITION_REG_VAL_V2{ 7340 ULONG ulCondition; 7341 UCHAR ucCondition2; 7342 ULONG ulRegVal; 7343}PHY_CONDITION_REG_VAL_V2; 7344 7345typedef struct _PHY_CONDITION_REG_INFO{ 7346 USHORT usRegIndex; 7347 USHORT usSize; 7348 PHY_CONDITION_REG_VAL asRegVal[]; 7349}PHY_CONDITION_REG_INFO; 7350 7351typedef struct _PHY_CONDITION_REG_INFO_V2{ 7352 USHORT usRegIndex; 7353 USHORT usSize; 7354 PHY_CONDITION_REG_VAL_V2 asRegVal[]; 7355}PHY_CONDITION_REG_INFO_V2; 7356 7357typedef struct _PHY_ANALOG_SETTING_INFO{ 7358 UCHAR ucEncodeMode; 7359 UCHAR ucPhySel; 7360 USHORT usSize; 7361 PHY_CONDITION_REG_INFO asAnalogSetting[]; 7362}PHY_ANALOG_SETTING_INFO; 7363 7364typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 7365 UCHAR ucEncodeMode; 7366 UCHAR ucPhySel; 7367 USHORT usSize; 7368 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[]; 7369}PHY_ANALOG_SETTING_INFO_V2; 7370 7371typedef struct _GFX_HAVESTING_PARAMETERS { 7372 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 7373 UCHAR ucReserved; //reserved 7374 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 7375 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 7376} GFX_HAVESTING_PARAMETERS; 7377 7378//ucGfxBlkId 7379#define GFX_HARVESTING_CU_ID 0 7380#define GFX_HARVESTING_RB_ID 1 7381#define GFX_HARVESTING_PRIM_ID 2 7382 7383/****************************************************************************/ 7384//Portion VI: Definitinos for vbios MC scratch registers that driver used 7385/****************************************************************************/ 7386 7387#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 7388#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 7389#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 7390#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 7391#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 7392#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 7393#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 7394#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 7395 7396#define ATOM_MEM_TYPE_DDR_STRING "DDR" 7397#define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 7398#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 7399#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 7400#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 7401#define ATOM_MEM_TYPE_HBM_STRING "HBM" 7402#define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 7403 7404/****************************************************************************/ 7405//Portion VI: Definitinos being oboselete 7406/****************************************************************************/ 7407 7408//========================================================================================== 7409//Remove the definitions below when driver is ready! 7410typedef struct _ATOM_DAC_INFO 7411{ 7412 ATOM_COMMON_TABLE_HEADER sHeader; 7413 USHORT usMaxFrequency; // in 10kHz unit 7414 USHORT usReserved; 7415}ATOM_DAC_INFO; 7416 7417 7418typedef struct _COMPASSIONATE_DATA 7419{ 7420 ATOM_COMMON_TABLE_HEADER sHeader; 7421 7422 //============================== DAC1 portion 7423 UCHAR ucDAC1_BG_Adjustment; 7424 UCHAR ucDAC1_DAC_Adjustment; 7425 USHORT usDAC1_FORCE_Data; 7426 //============================== DAC2 portion 7427 UCHAR ucDAC2_CRT2_BG_Adjustment; 7428 UCHAR ucDAC2_CRT2_DAC_Adjustment; 7429 USHORT usDAC2_CRT2_FORCE_Data; 7430 USHORT usDAC2_CRT2_MUX_RegisterIndex; 7431 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7432 UCHAR ucDAC2_NTSC_BG_Adjustment; 7433 UCHAR ucDAC2_NTSC_DAC_Adjustment; 7434 USHORT usDAC2_TV1_FORCE_Data; 7435 USHORT usDAC2_TV1_MUX_RegisterIndex; 7436 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7437 UCHAR ucDAC2_CV_BG_Adjustment; 7438 UCHAR ucDAC2_CV_DAC_Adjustment; 7439 USHORT usDAC2_CV_FORCE_Data; 7440 USHORT usDAC2_CV_MUX_RegisterIndex; 7441 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7442 UCHAR ucDAC2_PAL_BG_Adjustment; 7443 UCHAR ucDAC2_PAL_DAC_Adjustment; 7444 USHORT usDAC2_TV2_FORCE_Data; 7445}COMPASSIONATE_DATA; 7446 7447/****************************Supported Device Info Table Definitions**********************/ 7448// ucConnectInfo: 7449// [7:4] - connector type 7450// = 1 - VGA connector 7451// = 2 - DVI-I 7452// = 3 - DVI-D 7453// = 4 - DVI-A 7454// = 5 - SVIDEO 7455// = 6 - COMPOSITE 7456// = 7 - LVDS 7457// = 8 - DIGITAL LINK 7458// = 9 - SCART 7459// = 0xA - HDMI_type A 7460// = 0xB - HDMI_type B 7461// = 0xE - Special case1 (DVI+DIN) 7462// Others=TBD 7463// [3:0] - DAC Associated 7464// = 0 - no DAC 7465// = 1 - DACA 7466// = 2 - DACB 7467// = 3 - External DAC 7468// Others=TBD 7469// 7470 7471typedef struct _ATOM_CONNECTOR_INFO 7472{ 7473#if ATOM_BIG_ENDIAN 7474 UCHAR bfConnectorType:4; 7475 UCHAR bfAssociatedDAC:4; 7476#else 7477 UCHAR bfAssociatedDAC:4; 7478 UCHAR bfConnectorType:4; 7479#endif 7480}ATOM_CONNECTOR_INFO; 7481 7482typedef union _ATOM_CONNECTOR_INFO_ACCESS 7483{ 7484 ATOM_CONNECTOR_INFO sbfAccess; 7485 UCHAR ucAccess; 7486}ATOM_CONNECTOR_INFO_ACCESS; 7487 7488typedef struct _ATOM_CONNECTOR_INFO_I2C 7489{ 7490 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 7491 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 7492}ATOM_CONNECTOR_INFO_I2C; 7493 7494 7495typedef struct _ATOM_SUPPORTED_DEVICES_INFO 7496{ 7497 ATOM_COMMON_TABLE_HEADER sHeader; 7498 USHORT usDeviceSupport; 7499 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 7500}ATOM_SUPPORTED_DEVICES_INFO; 7501 7502#define NO_INT_SRC_MAPPED 0xFF 7503 7504typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 7505{ 7506 UCHAR ucIntSrcBitmap; 7507}ATOM_CONNECTOR_INC_SRC_BITMAP; 7508 7509typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 7510{ 7511 ATOM_COMMON_TABLE_HEADER sHeader; 7512 USHORT usDeviceSupport; 7513 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 7514 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 7515}ATOM_SUPPORTED_DEVICES_INFO_2; 7516 7517typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 7518{ 7519 ATOM_COMMON_TABLE_HEADER sHeader; 7520 USHORT usDeviceSupport; 7521 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 7522 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 7523}ATOM_SUPPORTED_DEVICES_INFO_2d1; 7524 7525#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 7526 7527 7528 7529typedef struct _ATOM_MISC_CONTROL_INFO 7530{ 7531 USHORT usFrequency; 7532 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 7533 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 7534 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 7535 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 7536}ATOM_MISC_CONTROL_INFO; 7537 7538 7539#define ATOM_MAX_MISC_INFO 4 7540 7541typedef struct _ATOM_TMDS_INFO 7542{ 7543 ATOM_COMMON_TABLE_HEADER sHeader; 7544 USHORT usMaxFrequency; // in 10Khz 7545 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 7546}ATOM_TMDS_INFO; 7547 7548 7549typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 7550{ 7551 UCHAR ucTVStandard; //Same as TV standards defined above, 7552 UCHAR ucPadding[1]; 7553}ATOM_ENCODER_ANALOG_ATTRIBUTE; 7554 7555typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 7556{ 7557 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 7558 UCHAR ucPadding[1]; 7559}ATOM_ENCODER_DIGITAL_ATTRIBUTE; 7560 7561typedef union _ATOM_ENCODER_ATTRIBUTE 7562{ 7563 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 7564 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 7565}ATOM_ENCODER_ATTRIBUTE; 7566 7567 7568typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 7569{ 7570 USHORT usPixelClock; 7571 USHORT usEncoderID; 7572 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 7573 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 7574 ATOM_ENCODER_ATTRIBUTE usDevAttr; 7575}DVO_ENCODER_CONTROL_PARAMETERS; 7576 7577typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 7578{ 7579 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 7580 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 7581}DVO_ENCODER_CONTROL_PS_ALLOCATION; 7582 7583 7584#define ATOM_XTMDS_ASIC_SI164_ID 1 7585#define ATOM_XTMDS_ASIC_SI178_ID 2 7586#define ATOM_XTMDS_ASIC_TFP513_ID 3 7587#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 7588#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 7589#define ATOM_XTMDS_MVPU_FPGA 0x00000004 7590 7591 7592typedef struct _ATOM_XTMDS_INFO 7593{ 7594 ATOM_COMMON_TABLE_HEADER sHeader; 7595 USHORT usSingleLinkMaxFrequency; 7596 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 7597 UCHAR ucXtransimitterID; 7598 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 7599 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 7600 // due to design. This ID is used to alert driver that the sequence is not "standard"! 7601 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 7602 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 7603}ATOM_XTMDS_INFO; 7604 7605typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 7606{ 7607 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 7608 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 7609 UCHAR ucPadding[2]; 7610}DFP_DPMS_STATUS_CHANGE_PARAMETERS; 7611 7612/****************************Legacy Power Play Table Definitions **********************/ 7613 7614//Definitions for ulPowerPlayMiscInfo 7615#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 7616#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 7617#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 7618 7619#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 7620#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 7621 7622#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 7623 7624#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 7625#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 7626#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 7627 7628#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 7629#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 7630#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 7631#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 7632#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 7633#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 7634#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 7635 7636#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 7637#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 7638#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 7639#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 7640#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 7641 7642#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 7643#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 7644 7645#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 7646#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 7647#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 7648#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 7649#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 7650#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 7651 7652#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 7653#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 7654#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 7655 7656#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 7657#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 7658#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 7659#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 7660#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 7661#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 7662#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 7663 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 7664#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 7665#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 7666#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 7667 7668//ucTableFormatRevision=1 7669//ucTableContentRevision=1 7670typedef struct _ATOM_POWERMODE_INFO 7671{ 7672 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7673 ULONG ulReserved1; // must set to 0 7674 ULONG ulReserved2; // must set to 0 7675 USHORT usEngineClock; 7676 USHORT usMemoryClock; 7677 UCHAR ucVoltageDropIndex; // index to GPIO table 7678 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7679 UCHAR ucMinTemperature; 7680 UCHAR ucMaxTemperature; 7681 UCHAR ucNumPciELanes; // number of PCIE lanes 7682}ATOM_POWERMODE_INFO; 7683 7684//ucTableFormatRevision=2 7685//ucTableContentRevision=1 7686typedef struct _ATOM_POWERMODE_INFO_V2 7687{ 7688 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7689 ULONG ulMiscInfo2; 7690 ULONG ulEngineClock; 7691 ULONG ulMemoryClock; 7692 UCHAR ucVoltageDropIndex; // index to GPIO table 7693 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7694 UCHAR ucMinTemperature; 7695 UCHAR ucMaxTemperature; 7696 UCHAR ucNumPciELanes; // number of PCIE lanes 7697}ATOM_POWERMODE_INFO_V2; 7698 7699//ucTableFormatRevision=2 7700//ucTableContentRevision=2 7701typedef struct _ATOM_POWERMODE_INFO_V3 7702{ 7703 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7704 ULONG ulMiscInfo2; 7705 ULONG ulEngineClock; 7706 ULONG ulMemoryClock; 7707 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 7708 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7709 UCHAR ucMinTemperature; 7710 UCHAR ucMaxTemperature; 7711 UCHAR ucNumPciELanes; // number of PCIE lanes 7712 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 7713}ATOM_POWERMODE_INFO_V3; 7714 7715 7716#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 7717 7718#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 7719#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 7720 7721#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 7722#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 7723#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 7724#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 7725#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 7726#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 7727#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 7728 7729 7730typedef struct _ATOM_POWERPLAY_INFO 7731{ 7732 ATOM_COMMON_TABLE_HEADER sHeader; 7733 UCHAR ucOverdriveThermalController; 7734 UCHAR ucOverdriveI2cLine; 7735 UCHAR ucOverdriveIntBitmap; 7736 UCHAR ucOverdriveControllerAddress; 7737 UCHAR ucSizeOfPowerModeEntry; 7738 UCHAR ucNumOfPowerModeEntries; 7739 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7740}ATOM_POWERPLAY_INFO; 7741 7742typedef struct _ATOM_POWERPLAY_INFO_V2 7743{ 7744 ATOM_COMMON_TABLE_HEADER sHeader; 7745 UCHAR ucOverdriveThermalController; 7746 UCHAR ucOverdriveI2cLine; 7747 UCHAR ucOverdriveIntBitmap; 7748 UCHAR ucOverdriveControllerAddress; 7749 UCHAR ucSizeOfPowerModeEntry; 7750 UCHAR ucNumOfPowerModeEntries; 7751 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7752}ATOM_POWERPLAY_INFO_V2; 7753 7754typedef struct _ATOM_POWERPLAY_INFO_V3 7755{ 7756 ATOM_COMMON_TABLE_HEADER sHeader; 7757 UCHAR ucOverdriveThermalController; 7758 UCHAR ucOverdriveI2cLine; 7759 UCHAR ucOverdriveIntBitmap; 7760 UCHAR ucOverdriveControllerAddress; 7761 UCHAR ucSizeOfPowerModeEntry; 7762 UCHAR ucNumOfPowerModeEntries; 7763 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7764}ATOM_POWERPLAY_INFO_V3; 7765 7766 7767// Following definitions are for compatibility issue in different SW components. 7768#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 7769#define Object_Info Object_Header 7770#define AdjustARB_SEQ MC_InitParameter 7771#define VRAM_GPIO_DetectionInfo VoltageObjectInfo 7772#define ASIC_VDDCI_Info ASIC_ProfilingInfo 7773#define ASIC_MVDDQ_Info MemoryTrainingInfo 7774#define SS_Info PPLL_SS_Info 7775#define ASIC_MVDDC_Info ASIC_InternalSS_Info 7776#define DispDevicePriorityInfo SaveRestoreInfo 7777#define DispOutInfo TV_VideoMode 7778 7779 7780#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 7781#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 7782 7783//New device naming, remove them when both DAL/VBIOS is ready 7784#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7785#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 7786 7787#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7788#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 7789 7790#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 7791#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 7792 7793#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 7794#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 7795 7796#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 7797#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 7798 7799#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 7800#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 7801 7802#define ATOM_S0_DFP1I ATOM_S0_DFP1 7803#define ATOM_S0_DFP1X ATOM_S0_DFP2 7804 7805#define ATOM_S0_DFP2I 0x00200000L 7806#define ATOM_S0_DFP2Ib2 0x20 7807 7808#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 7809#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 7810 7811#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 7812#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 7813 7814#define ATOM_S3_DFP2I_ACTIVEb1 0x02 7815 7816#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 7817#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 7818 7819#define ATOM_S3_DFP2I_ACTIVE 0x00000200L 7820 7821#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 7822#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 7823#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 7824 7825#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 7826#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 7827 7828#define ATOM_S5_DOS_REQ_DFP2I 0x0200 7829#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 7830#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 7831 7832#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 7833#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 7834 7835#define TMDS1XEncoderControl DVOEncoderControl 7836#define DFP1XOutputControl DVOOutputControl 7837 7838#define ExternalDFPOutputControl DFP1XOutputControl 7839#define EnableExternalTMDS_Encoder TMDS1XEncoderControl 7840 7841#define DFP1IOutputControl TMDSAOutputControl 7842#define DFP2IOutputControl LVTMAOutputControl 7843 7844#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7845#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7846 7847#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7848#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7849 7850#define ucDac1Standard ucDacStandard 7851#define ucDac2Standard ucDacStandard 7852 7853#define TMDS1EncoderControl TMDSAEncoderControl 7854#define TMDS2EncoderControl LVTMAEncoderControl 7855 7856#define DFP1OutputControl TMDSAOutputControl 7857#define DFP2OutputControl LVTMAOutputControl 7858#define CRT1OutputControl DAC1OutputControl 7859#define CRT2OutputControl DAC2OutputControl 7860 7861//These two lines will be removed for sure in a few days, will follow up with Michael V. 7862#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 7863#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 7864 7865//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7866//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7867//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7868//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7869//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7870 7871#define ATOM_S6_ACC_REQ_TV2 0x00400000L 7872#define ATOM_DEVICE_TV2_INDEX 0x00000006 7873#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 7874#define ATOM_S0_TV2 0x00100000L 7875#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 7876#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 7877 7878// 7879#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7880#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 7881#define ATOM_S2_TV1_DPMS_STATE 0x00040000L 7882#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 7883#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 7884#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 7885#define ATOM_S2_TV2_DPMS_STATE 0x00400000L 7886#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 7887#define ATOM_S2_CV_DPMS_STATE 0x01000000L 7888#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 7889#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 7890#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 7891 7892#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 7893#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 7894#define ATOM_S2_TV1_DPMS_STATEb2 0x04 7895#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 7896#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 7897#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 7898#define ATOM_S2_TV2_DPMS_STATEb2 0x40 7899#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 7900#define ATOM_S2_CV_DPMS_STATEb3 0x01 7901#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 7902#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 7903#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 7904 7905#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 7906#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 7907#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 7908 7909/*********************************************************************************/ 7910 7911#pragma pack() // BIOS data must use byte alignment 7912 7913// 7914// AMD ACPI Table 7915// 7916#pragma pack(1) 7917 7918typedef struct { 7919 ULONG Signature; 7920 ULONG TableLength; //Length 7921 UCHAR Revision; 7922 UCHAR Checksum; 7923 UCHAR OemId[6]; 7924 UCHAR OemTableId[8]; //UINT64 OemTableId; 7925 ULONG OemRevision; 7926 ULONG CreatorId; 7927 ULONG CreatorRevision; 7928} AMD_ACPI_DESCRIPTION_HEADER; 7929/* 7930//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 7931typedef struct { 7932 UINT32 Signature; //0x0 7933 UINT32 Length; //0x4 7934 UINT8 Revision; //0x8 7935 UINT8 Checksum; //0x9 7936 UINT8 OemId[6]; //0xA 7937 UINT64 OemTableId; //0x10 7938 UINT32 OemRevision; //0x18 7939 UINT32 CreatorId; //0x1C 7940 UINT32 CreatorRevision; //0x20 7941}EFI_ACPI_DESCRIPTION_HEADER; 7942*/ 7943typedef struct { 7944 AMD_ACPI_DESCRIPTION_HEADER SHeader; 7945 UCHAR TableUUID[16]; //0x24 7946 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure. 7947 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure. 7948 ULONG Reserved[4]; //0x3C 7949}UEFI_ACPI_VFCT; 7950 7951typedef struct { 7952 ULONG PCIBus; //0x4C 7953 ULONG PCIDevice; //0x50 7954 ULONG PCIFunction; //0x54 7955 USHORT VendorID; //0x58 7956 USHORT DeviceID; //0x5A 7957 USHORT SSVID; //0x5C 7958 USHORT SSID; //0x5E 7959 ULONG Revision; //0x60 7960 ULONG ImageLength; //0x64 7961}VFCT_IMAGE_HEADER; 7962 7963 7964typedef struct { 7965 VFCT_IMAGE_HEADER VbiosHeader; 7966 UCHAR VbiosContent[]; 7967}GOP_VBIOS_CONTENT; 7968 7969typedef struct { 7970 VFCT_IMAGE_HEADER Lib1Header; 7971 UCHAR Lib1Content[1]; 7972}GOP_LIB1_CONTENT; 7973 7974#pragma pack() 7975 7976 7977#endif /* _ATOMBIOS_H */ 7978 7979#include "pptable.h" 7980
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