pl111_display.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
  4 *
  5 * Parts of this file were based on sources as follows:
  6 *
  7 * Copyright (c) 2006-2008 Intel Corporation
  8 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
  9 * Copyright (C) 2011 Texas Instruments
 10 */
 11
 12#include <linux/clk.h>
 13#include <linux/delay.h>
 14#include <linux/dma-buf.h>
 15#include <linux/media-bus-format.h>
 16#include <linux/of_graph.h>
 17
 18#include <drm/drm_fb_dma_helper.h>
 19#include <drm/drm_fourcc.h>
 20#include <drm/drm_framebuffer.h>
 21#include <drm/drm_gem_atomic_helper.h>
 22#include <drm/drm_gem_dma_helper.h>
 23#include <drm/drm_print.h>
 24#include <drm/drm_vblank.h>
 25
 26#include "pl111_drm.h"
 27
 28irqreturn_t pl111_irq(int irq, void *data)
 29{
 30	struct pl111_drm_dev_private *priv = data;
 31	u32 irq_stat;
 32	irqreturn_t status = IRQ_NONE;
 33
 34	irq_stat = readl(priv->regs + CLCD_PL111_MIS);
 35
 36	if (!irq_stat)
 37		return IRQ_NONE;
 38
 39	if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) {
 40		drm_crtc_handle_vblank(&priv->pipe.crtc);
 41
 42		status = IRQ_HANDLED;
 43	}
 44
 45	/* Clear the interrupt once done */
 46	writel(irq_stat, priv->regs + CLCD_PL111_ICR);
 47
 48	return status;
 49}
 50
 51static enum drm_mode_status
 52pl111_mode_valid(struct drm_simple_display_pipe *pipe,
 53		 const struct drm_display_mode *mode)
 54{
 55	struct drm_device *drm = pipe->crtc.dev;
 56	struct pl111_drm_dev_private *priv = drm->dev_private;
 57	u32 cpp = DIV_ROUND_UP(priv->variant->fb_depth, 8);
 58	u64 bw;
 59
 60	/*
 61	 * We use the pixelclock to also account for interlaced modes, the
 62	 * resulting bandwidth is in bytes per second.
 63	 */
 64	bw = mode->clock * 1000ULL; /* In Hz */
 65	bw = bw * mode->hdisplay * mode->vdisplay * cpp;
 66	bw = div_u64(bw, mode->htotal * mode->vtotal);
 67
 68	/*
 69	 * If no bandwidth constraints, anything goes, else
 70	 * check if we are too fast.
 71	 */
 72	if (priv->memory_bw && (bw > priv->memory_bw)) {
 73		DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n",
 74			      mode->hdisplay, mode->vdisplay,
 75			      mode->clock * 1000, cpp, bw);
 76
 77		return MODE_BAD;
 78	}
 79	DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n",
 80		      mode->hdisplay, mode->vdisplay,
 81		      mode->clock * 1000, cpp, bw);
 82
 83	return MODE_OK;
 84}
 85
 86static int pl111_display_check(struct drm_simple_display_pipe *pipe,
 87			       struct drm_plane_state *pstate,
 88			       struct drm_crtc_state *cstate)
 89{
 90	const struct drm_display_mode *mode = &cstate->mode;
 91	struct drm_framebuffer *old_fb = pipe->plane.state->fb;
 92	struct drm_framebuffer *fb = pstate->fb;
 93
 94	if (mode->hdisplay % 16)
 95		return -EINVAL;
 96
 97	if (fb) {
 98		u32 offset = drm_fb_dma_get_gem_addr(fb, pstate, 0);
 99
100		/* FB base address must be dword aligned. */
101		if (offset & 3)
102			return -EINVAL;
103
104		/* There's no pitch register -- the mode's hdisplay
105		 * controls it.
106		 */
107		if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0])
108			return -EINVAL;
109
110		/* We can't change the FB format in a flicker-free
111		 * manner (and only update it during CRTC enable).
112		 */
113		if (old_fb && old_fb->format != fb->format)
114			cstate->mode_changed = true;
115	}
116
117	return 0;
118}
119
120static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
121				 struct drm_crtc_state *cstate,
122				 struct drm_plane_state *plane_state)
123{
124	struct drm_crtc *crtc = &pipe->crtc;
125	struct drm_plane *plane = &pipe->plane;
126	struct drm_device *drm = crtc->dev;
127	struct pl111_drm_dev_private *priv = drm->dev_private;
128	const struct drm_display_mode *mode = &cstate->mode;
129	struct drm_framebuffer *fb = plane->state->fb;
130	struct drm_connector *connector = priv->connector;
131	struct drm_bridge *bridge = priv->bridge;
132	bool grayscale = false;
133	u32 cntl;
134	u32 ppl, hsw, hfp, hbp;
135	u32 lpp, vsw, vfp, vbp;
136	u32 cpl, tim2;
137	int ret;
138
139	ret = clk_set_rate(priv->clk, mode->clock * 1000);
140	if (ret) {
141		dev_err(drm->dev,
142			"Failed to set pixel clock rate to %d: %d\n",
143			mode->clock * 1000, ret);
144	}
145
146	clk_prepare_enable(priv->clk);
147
148	ppl = (mode->hdisplay / 16) - 1;
149	hsw = mode->hsync_end - mode->hsync_start - 1;
150	hfp = mode->hsync_start - mode->hdisplay - 1;
151	hbp = mode->htotal - mode->hsync_end - 1;
152
153	lpp = mode->vdisplay - 1;
154	vsw = mode->vsync_end - mode->vsync_start - 1;
155	vfp = mode->vsync_start - mode->vdisplay;
156	vbp = mode->vtotal - mode->vsync_end;
157
158	cpl = mode->hdisplay - 1;
159
160	writel((ppl << 2) |
161	       (hsw << 8) |
162	       (hfp << 16) |
163	       (hbp << 24),
164	       priv->regs + CLCD_TIM0);
165	writel(lpp |
166	       (vsw << 10) |
167	       (vfp << 16) |
168	       (vbp << 24),
169	       priv->regs + CLCD_TIM1);
170
171	spin_lock(&priv->tim2_lock);
172
173	tim2 = readl(priv->regs + CLCD_TIM2);
174	tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
175
176	if (priv->variant->broken_clockdivider)
177		tim2 |= TIM2_BCD;
178
179	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
180		tim2 |= TIM2_IHS;
181
182	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
183		tim2 |= TIM2_IVS;
184
185	if (connector) {
186		if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
187			tim2 |= TIM2_IOE;
188
189		if (connector->display_info.bus_flags &
190		    DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
191			tim2 |= TIM2_IPC;
192
193		if (connector->display_info.num_bus_formats == 1 &&
194		    connector->display_info.bus_formats[0] ==
195		    MEDIA_BUS_FMT_Y8_1X8)
196			grayscale = true;
197
198		/*
199		 * The AC pin bias frequency is set to max count when using
200		 * grayscale so at least once in a while we will reverse
201		 * polarity and get rid of any DC built up that could
202		 * damage the display.
203		 */
204		if (grayscale)
205			tim2 |= TIM2_ACB_MASK;
206	}
207
208	if (bridge) {
209		const struct drm_bridge_timings *btimings = bridge->timings;
210
211		/*
212		 * Here is when things get really fun. Sometimes the bridge
213		 * timings are such that the signal out from PL11x is not
214		 * stable before the receiving bridge (such as a dumb VGA DAC
215		 * or similar) samples it. If that happens, we compensate by
216		 * the only method we have: output the data on the opposite
217		 * edge of the clock so it is for sure stable when it gets
218		 * sampled.
219		 *
220		 * The PL111 manual does not contain proper timining diagrams
221		 * or data for these details, but we know from experiments
222		 * that the setup time is more than 3000 picoseconds (3 ns).
223		 * If we have a bridge that requires the signal to be stable
224		 * earlier than 3000 ps before the clock pulse, we have to
225		 * output the data on the opposite edge to avoid flicker.
226		 */
227		if (btimings && btimings->setup_time_ps >= 3000)
228			tim2 ^= TIM2_IPC;
229	}
230
231	tim2 |= cpl << 16;
232	writel(tim2, priv->regs + CLCD_TIM2);
233	spin_unlock(&priv->tim2_lock);
234
235	writel(0, priv->regs + CLCD_TIM3);
236
237	/*
238	 * Detect grayscale bus format. We do not support a grayscale mode
239	 * toward userspace, instead we expose an RGB24 buffer and then the
240	 * hardware will activate its grayscaler to convert to the grayscale
241	 * format.
242	 */
243	if (grayscale)
244		cntl = CNTL_LCDEN | CNTL_LCDMONO8;
245	else
246		/* Else we assume TFT display */
247		cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
248
249	/* On the ST Micro variant, assume all 24 bits are connected */
250	if (priv->variant->st_bitmux_control)
251		cntl |= CNTL_ST_CDWID_24;
252
253	/*
254	 * Note that the ARM hardware's format reader takes 'r' from
255	 * the low bit, while DRM formats list channels from high bit
256	 * to low bit as you read left to right. The ST Micro version of
257	 * the PL110 (LCDC) however uses the standard DRM format.
258	 */
259	switch (fb->format->format) {
260	case DRM_FORMAT_BGR888:
261		/* Only supported on the ST Micro variant */
262		if (priv->variant->st_bitmux_control)
263			cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR;
264		break;
265	case DRM_FORMAT_RGB888:
266		/* Only supported on the ST Micro variant */
267		if (priv->variant->st_bitmux_control)
268			cntl |= CNTL_ST_LCDBPP24_PACKED;
269		break;
270	case DRM_FORMAT_ABGR8888:
271	case DRM_FORMAT_XBGR8888:
272		if (priv->variant->st_bitmux_control)
273			cntl |= CNTL_LCDBPP24 | CNTL_BGR;
274		else
275			cntl |= CNTL_LCDBPP24;
276		break;
277	case DRM_FORMAT_ARGB8888:
278	case DRM_FORMAT_XRGB8888:
279		if (priv->variant->st_bitmux_control)
280			cntl |= CNTL_LCDBPP24;
281		else
282			cntl |= CNTL_LCDBPP24 | CNTL_BGR;
283		break;
284	case DRM_FORMAT_BGR565:
285		if (priv->variant->is_pl110)
286			cntl |= CNTL_LCDBPP16;
287		else if (priv->variant->st_bitmux_control)
288			cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR;
289		else
290			cntl |= CNTL_LCDBPP16_565;
291		break;
292	case DRM_FORMAT_RGB565:
293		if (priv->variant->is_pl110)
294			cntl |= CNTL_LCDBPP16 | CNTL_BGR;
295		else if (priv->variant->st_bitmux_control)
296			cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565;
297		else
298			cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
299		break;
300	case DRM_FORMAT_ABGR1555:
301	case DRM_FORMAT_XBGR1555:
302		cntl |= CNTL_LCDBPP16;
303		if (priv->variant->st_bitmux_control)
304			cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR;
305		break;
306	case DRM_FORMAT_ARGB1555:
307	case DRM_FORMAT_XRGB1555:
308		cntl |= CNTL_LCDBPP16;
309		if (priv->variant->st_bitmux_control)
310			cntl |= CNTL_ST_1XBPP_5551;
311		else
312			cntl |= CNTL_BGR;
313		break;
314	case DRM_FORMAT_ABGR4444:
315	case DRM_FORMAT_XBGR4444:
316		cntl |= CNTL_LCDBPP16_444;
317		if (priv->variant->st_bitmux_control)
318			cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR;
319		break;
320	case DRM_FORMAT_ARGB4444:
321	case DRM_FORMAT_XRGB4444:
322		cntl |= CNTL_LCDBPP16_444;
323		if (priv->variant->st_bitmux_control)
324			cntl |= CNTL_ST_1XBPP_444;
325		else
326			cntl |= CNTL_BGR;
327		break;
328	default:
329		WARN_ONCE(true, "Unknown FB format 0x%08x\n",
330			  fb->format->format);
331		break;
332	}
333
334	/* The PL110 in Integrator/Versatile does the BGR routing externally */
335	if (priv->variant->external_bgr)
336		cntl &= ~CNTL_BGR;
337
338	/* Power sequence: first enable and chill */
339	writel(cntl, priv->regs + priv->ctrl);
340
341	/*
342	 * We expect this delay to stabilize the contrast
343	 * voltage Vee as stipulated by the manual
344	 */
345	msleep(20);
346
347	if (priv->variant_display_enable)
348		priv->variant_display_enable(drm, fb->format->format);
349
350	/* Power Up */
351	cntl |= CNTL_LCDPWR;
352	writel(cntl, priv->regs + priv->ctrl);
353
354	if (!priv->variant->broken_vblank)
355		drm_crtc_vblank_on(crtc);
356}
357
358static void pl111_display_disable(struct drm_simple_display_pipe *pipe)
359{
360	struct drm_crtc *crtc = &pipe->crtc;
361	struct drm_device *drm = crtc->dev;
362	struct pl111_drm_dev_private *priv = drm->dev_private;
363	u32 cntl;
364
365	if (!priv->variant->broken_vblank)
366		drm_crtc_vblank_off(crtc);
367
368	/* Power Down */
369	cntl = readl(priv->regs + priv->ctrl);
370	if (cntl & CNTL_LCDPWR) {
371		cntl &= ~CNTL_LCDPWR;
372		writel(cntl, priv->regs + priv->ctrl);
373	}
374
375	/*
376	 * We expect this delay to stabilize the contrast voltage Vee as
377	 * stipulated by the manual
378	 */
379	msleep(20);
380
381	if (priv->variant_display_disable)
382		priv->variant_display_disable(drm);
383
384	/* Disable */
385	writel(0, priv->regs + priv->ctrl);
386
387	clk_disable_unprepare(priv->clk);
388}
389
390static void pl111_display_update(struct drm_simple_display_pipe *pipe,
391				 struct drm_plane_state *old_pstate)
392{
393	struct drm_crtc *crtc = &pipe->crtc;
394	struct drm_device *drm = crtc->dev;
395	struct pl111_drm_dev_private *priv = drm->dev_private;
396	struct drm_pending_vblank_event *event = crtc->state->event;
397	struct drm_plane *plane = &pipe->plane;
398	struct drm_plane_state *pstate = plane->state;
399	struct drm_framebuffer *fb = pstate->fb;
400
401	if (fb) {
402		u32 addr = drm_fb_dma_get_gem_addr(fb, pstate, 0);
403
404		writel(addr, priv->regs + CLCD_UBAS);
405	}
406
407	if (event) {
408		crtc->state->event = NULL;
409
410		spin_lock_irq(&crtc->dev->event_lock);
411		if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
412			drm_crtc_arm_vblank_event(crtc, event);
413		else
414			drm_crtc_send_vblank_event(crtc, event);
415		spin_unlock_irq(&crtc->dev->event_lock);
416	}
417}
418
419static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe)
420{
421	struct drm_crtc *crtc = &pipe->crtc;
422	struct drm_device *drm = crtc->dev;
423	struct pl111_drm_dev_private *priv = drm->dev_private;
424
425	writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
426
427	return 0;
428}
429
430static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe)
431{
432	struct drm_crtc *crtc = &pipe->crtc;
433	struct drm_device *drm = crtc->dev;
434	struct pl111_drm_dev_private *priv = drm->dev_private;
435
436	writel(0, priv->regs + priv->ienb);
437}
438
439static struct drm_simple_display_pipe_funcs pl111_display_funcs = {
440	.mode_valid = pl111_mode_valid,
441	.check = pl111_display_check,
442	.enable = pl111_display_enable,
443	.disable = pl111_display_disable,
444	.update = pl111_display_update,
445};
446
447static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate,
448				    unsigned long *prate, bool set_parent)
449{
450	int best_div = 1, div;
451	struct clk_hw *parent = clk_hw_get_parent(hw);
452	unsigned long best_prate = 0;
453	unsigned long best_diff = ~0ul;
454	int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1;
455
456	for (div = 1; div < max_div; div++) {
457		unsigned long this_prate, div_rate, diff;
458
459		if (set_parent)
460			this_prate = clk_hw_round_rate(parent, rate * div);
461		else
462			this_prate = *prate;
463		div_rate = DIV_ROUND_UP_ULL(this_prate, div);
464		diff = abs(rate - div_rate);
465
466		if (diff < best_diff) {
467			best_div = div;
468			best_diff = diff;
469			best_prate = this_prate;
470		}
471	}
472
473	*prate = best_prate;
474	return best_div;
475}
476
477static int pl111_clk_div_determine_rate(struct clk_hw *hw,
478					struct clk_rate_request *req)
479{
480	int div = pl111_clk_div_choose_div(hw, req->rate,
481					   &req->best_parent_rate, true);
482
483	req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div);
484
485	return 0;
486}
487
488static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw,
489					       unsigned long prate)
490{
491	struct pl111_drm_dev_private *priv =
492		container_of(hw, struct pl111_drm_dev_private, clk_div);
493	u32 tim2 = readl(priv->regs + CLCD_TIM2);
494	int div;
495
496	if (tim2 & TIM2_BCD)
497		return prate;
498
499	div = tim2 & TIM2_PCD_LO_MASK;
500	div |= (tim2 & TIM2_PCD_HI_MASK) >>
501		(TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS);
502	div += 2;
503
504	return DIV_ROUND_UP_ULL(prate, div);
505}
506
507static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
508				  unsigned long prate)
509{
510	struct pl111_drm_dev_private *priv =
511		container_of(hw, struct pl111_drm_dev_private, clk_div);
512	int div = pl111_clk_div_choose_div(hw, rate, &prate, false);
513	u32 tim2;
514
515	spin_lock(&priv->tim2_lock);
516	tim2 = readl(priv->regs + CLCD_TIM2);
517	tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
518
519	if (div == 1) {
520		tim2 |= TIM2_BCD;
521	} else {
522		div -= 2;
523		tim2 |= div & TIM2_PCD_LO_MASK;
524		tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT;
525	}
526
527	writel(tim2, priv->regs + CLCD_TIM2);
528	spin_unlock(&priv->tim2_lock);
529
530	return 0;
531}
532
533static const struct clk_ops pl111_clk_div_ops = {
534	.recalc_rate = pl111_clk_div_recalc_rate,
535	.determine_rate = pl111_clk_div_determine_rate,
536	.set_rate = pl111_clk_div_set_rate,
537};
538
539static int
540pl111_init_clock_divider(struct drm_device *drm)
541{
542	struct pl111_drm_dev_private *priv = drm->dev_private;
543	struct clk *parent = devm_clk_get(drm->dev, "clcdclk");
544	struct clk_hw *div = &priv->clk_div;
545	const char *parent_name;
546	struct clk_init_data init = {
547		.name = "pl111_div",
548		.ops = &pl111_clk_div_ops,
549		.parent_names = &parent_name,
550		.num_parents = 1,
551		.flags = CLK_SET_RATE_PARENT,
552	};
553	int ret;
554
555	if (IS_ERR(parent)) {
556		dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");
557		return PTR_ERR(parent);
558	}
559
560	spin_lock_init(&priv->tim2_lock);
561
562	/* If the clock divider is broken, use the parent directly */
563	if (priv->variant->broken_clockdivider) {
564		priv->clk = parent;
565		return 0;
566	}
567	parent_name = __clk_get_name(parent);
568	div->init = &init;
569
570	ret = devm_clk_hw_register(drm->dev, div);
571
572	priv->clk = div->clk;
573	return ret;
574}
575
576int pl111_display_init(struct drm_device *drm)
577{
578	struct pl111_drm_dev_private *priv = drm->dev_private;
579	int ret;
580
581	ret = pl111_init_clock_divider(drm);
582	if (ret)
583		return ret;
584
585	if (!priv->variant->broken_vblank) {
586		pl111_display_funcs.enable_vblank = pl111_display_enable_vblank;
587		pl111_display_funcs.disable_vblank = pl111_display_disable_vblank;
588	}
589
590	ret = drm_simple_display_pipe_init(drm, &priv->pipe,
591					   &pl111_display_funcs,
592					   priv->variant->formats,
593					   priv->variant->nformats,
594					   NULL,
595					   priv->connector);
596	if (ret)
597		return ret;
598
599	return 0;
600}