panthor_regs.h

  1/* SPDX-License-Identifier: GPL-2.0 or MIT */
  2/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
  3/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
  4/* Copyright 2023 Collabora ltd. */
  5/*
  6 * Register definitions based on mali_kbase_gpu_regmap.h and
  7 * mali_kbase_gpu_regmap_csf.h
  8 * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
  9 */
 10#ifndef __PANTHOR_REGS_H__
 11#define __PANTHOR_REGS_H__
 12
 13#define GPU_ID						0x0
 14#define   GPU_ARCH_MAJOR(x)				((x) >> 28)
 15#define   GPU_ARCH_MINOR(x)				(((x) & GENMASK(27, 24)) >> 24)
 16#define   GPU_ARCH_REV(x)				(((x) & GENMASK(23, 20)) >> 20)
 17#define   GPU_PROD_MAJOR(x)				(((x) & GENMASK(19, 16)) >> 16)
 18#define   GPU_VER_MAJOR(x)				(((x) & GENMASK(15, 12)) >> 12)
 19#define   GPU_VER_MINOR(x)				(((x) & GENMASK(11, 4)) >> 4)
 20#define   GPU_VER_STATUS(x)				((x) & GENMASK(3, 0))
 21
 22#define GPU_L2_FEATURES					0x4
 23#define  GPU_L2_FEATURES_LINE_SIZE(x)			(1 << ((x) & GENMASK(7, 0)))
 24
 25#define GPU_CORE_FEATURES				0x8
 26
 27#define GPU_TILER_FEATURES				0xC
 28#define GPU_MEM_FEATURES				0x10
 29#define   GROUPS_L2_COHERENT				BIT(0)
 30
 31#define GPU_MMU_FEATURES				0x14
 32#define  GPU_MMU_FEATURES_VA_BITS(x)			((x) & GENMASK(7, 0))
 33#define  GPU_MMU_FEATURES_PA_BITS(x)			(((x) >> 8) & GENMASK(7, 0))
 34#define GPU_AS_PRESENT					0x18
 35#define GPU_CSF_ID					0x1C
 36
 37#define GPU_INT_RAWSTAT					0x20
 38#define GPU_INT_CLEAR					0x24
 39#define GPU_INT_MASK					0x28
 40#define GPU_INT_STAT					0x2c
 41#define   GPU_IRQ_FAULT					BIT(0)
 42#define   GPU_IRQ_PROTM_FAULT				BIT(1)
 43#define   GPU_IRQ_RESET_COMPLETED			BIT(8)
 44#define   GPU_IRQ_POWER_CHANGED				BIT(9)
 45#define   GPU_IRQ_POWER_CHANGED_ALL			BIT(10)
 46#define   GPU_IRQ_CLEAN_CACHES_COMPLETED		BIT(17)
 47#define   GPU_IRQ_DOORBELL_MIRROR			BIT(18)
 48#define   GPU_IRQ_MCU_STATUS_CHANGED			BIT(19)
 49#define GPU_CMD						0x30
 50#define   GPU_CMD_DEF(type, payload)			((type) | ((payload) << 8))
 51#define   GPU_SOFT_RESET				GPU_CMD_DEF(1, 1)
 52#define   GPU_HARD_RESET				GPU_CMD_DEF(1, 2)
 53#define   CACHE_CLEAN					BIT(0)
 54#define   CACHE_INV					BIT(1)
 55#define   GPU_FLUSH_CACHES(l2, lsc, oth)		\
 56	  GPU_CMD_DEF(4, ((l2) << 0) | ((lsc) << 4) | ((oth) << 8))
 57
 58#define GPU_STATUS					0x34
 59#define   GPU_STATUS_ACTIVE				BIT(0)
 60#define   GPU_STATUS_PWR_ACTIVE				BIT(1)
 61#define   GPU_STATUS_PAGE_FAULT				BIT(4)
 62#define   GPU_STATUS_PROTM_ACTIVE			BIT(7)
 63#define   GPU_STATUS_DBG_ENABLED			BIT(8)
 64
 65#define GPU_FAULT_STATUS				0x3C
 66#define GPU_FAULT_ADDR					0x40
 67#define GPU_L2_CONFIG					0x48
 68#define   GPU_L2_CONFIG_ASN_HASH_ENABLE			BIT(24)
 69
 70#define GPU_PWR_KEY					0x50
 71#define  GPU_PWR_KEY_UNLOCK				0x2968A819
 72#define GPU_PWR_OVERRIDE0				0x54
 73#define GPU_PWR_OVERRIDE1				0x58
 74
 75#define GPU_FEATURES					0x60
 76#define   GPU_FEATURES_RAY_INTERSECTION			BIT(2)
 77#define   GPU_FEATURES_RAY_TRAVERSAL			BIT(5)
 78
 79#define GPU_TIMESTAMP_OFFSET				0x88
 80#define GPU_CYCLE_COUNT					0x90
 81#define GPU_TIMESTAMP					0x98
 82
 83#define GPU_THREAD_MAX_THREADS				0xA0
 84#define GPU_THREAD_MAX_WORKGROUP_SIZE			0xA4
 85#define GPU_THREAD_MAX_BARRIER_SIZE			0xA8
 86#define GPU_THREAD_FEATURES				0xAC
 87
 88#define GPU_TEXTURE_FEATURES(n)				(0xB0 + ((n) * 4))
 89
 90#define GPU_SHADER_PRESENT				0x100
 91#define GPU_TILER_PRESENT				0x110
 92#define GPU_L2_PRESENT					0x120
 93
 94#define SHADER_READY					0x140
 95#define TILER_READY					0x150
 96#define L2_READY					0x160
 97
 98#define SHADER_PWRON					0x180
 99#define TILER_PWRON					0x190
100#define L2_PWRON					0x1A0
101
102#define SHADER_PWROFF					0x1C0
103#define TILER_PWROFF					0x1D0
104#define L2_PWROFF					0x1E0
105
106#define SHADER_PWRTRANS					0x200
107#define TILER_PWRTRANS					0x210
108#define L2_PWRTRANS					0x220
109
110#define SHADER_PWRACTIVE				0x240
111#define TILER_PWRACTIVE					0x250
112#define L2_PWRACTIVE					0x260
113
114#define GPU_REVID					0x280
115
116#define GPU_ASN_HASH(n)					(0x2C0 + ((n) * 4))
117
118#define GPU_COHERENCY_FEATURES				0x300
119#define GPU_COHERENCY_PROT_BIT(name)			BIT(GPU_COHERENCY_  ## name)
120
121#define GPU_COHERENCY_PROTOCOL				0x304
122#define   GPU_COHERENCY_ACE_LITE			0
123#define   GPU_COHERENCY_ACE				1
124#define   GPU_COHERENCY_NONE				31
125
126#define MCU_CONTROL					0x700
127#define MCU_CONTROL_ENABLE				1
128#define MCU_CONTROL_AUTO				2
129#define MCU_CONTROL_DISABLE				0
130
131#define MCU_STATUS					0x704
132#define MCU_STATUS_DISABLED				0
133#define MCU_STATUS_ENABLED				1
134#define MCU_STATUS_HALT					2
135#define MCU_STATUS_FATAL				3
136
137/* Job Control regs */
138#define JOB_INT_RAWSTAT					0x1000
139#define JOB_INT_CLEAR					0x1004
140#define JOB_INT_MASK					0x1008
141#define JOB_INT_STAT					0x100c
142#define   JOB_INT_GLOBAL_IF				BIT(31)
143#define   JOB_INT_CSG_IF(x)				BIT(x)
144
145/* MMU regs */
146#define MMU_INT_RAWSTAT					0x2000
147#define MMU_INT_CLEAR					0x2004
148#define MMU_INT_MASK					0x2008
149#define MMU_INT_STAT					0x200c
150
151/* AS_COMMAND register commands */
152
153#define MMU_BASE					0x2400
154#define MMU_AS_SHIFT					6
155#define MMU_AS(as)					(MMU_BASE + ((as) << MMU_AS_SHIFT))
156
157#define AS_TRANSTAB(as)					(MMU_AS(as) + 0x0)
158#define AS_MEMATTR(as)					(MMU_AS(as) + 0x8)
159#define   AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL		(2 << 2)
160#define   AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r)	((3 << 2) | \
161							 ((w) ? BIT(0) : 0) | \
162							 ((r) ? BIT(1) : 0))
163#define   AS_MEMATTR_AARCH64_SH_MIDGARD_INNER		(0 << 4)
164#define   AS_MEMATTR_AARCH64_SH_CPU_INNER		(1 << 4)
165#define   AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH	(2 << 4)
166#define   AS_MEMATTR_AARCH64_SHARED			(0 << 6)
167#define   AS_MEMATTR_AARCH64_INNER_OUTER_NC		(1 << 6)
168#define   AS_MEMATTR_AARCH64_INNER_OUTER_WB		(2 << 6)
169#define   AS_MEMATTR_AARCH64_FAULT			(3 << 6)
170#define AS_LOCKADDR(as)					(MMU_AS(as) + 0x10)
171#define AS_COMMAND(as)					(MMU_AS(as) + 0x18)
172#define   AS_COMMAND_NOP				0
173#define   AS_COMMAND_UPDATE				1
174#define   AS_COMMAND_LOCK				2
175#define   AS_COMMAND_UNLOCK				3
176#define   AS_COMMAND_FLUSH_PT				4
177#define   AS_COMMAND_FLUSH_MEM				5
178#define   AS_LOCK_REGION_MIN_SIZE			(1ULL << 15)
179#define AS_FAULTSTATUS(as)				(MMU_AS(as) + 0x1C)
180#define  AS_FAULTSTATUS_ACCESS_TYPE_MASK		(0x3 << 8)
181#define  AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC		(0x0 << 8)
182#define  AS_FAULTSTATUS_ACCESS_TYPE_EX			(0x1 << 8)
183#define  AS_FAULTSTATUS_ACCESS_TYPE_READ		(0x2 << 8)
184#define  AS_FAULTSTATUS_ACCESS_TYPE_WRITE		(0x3 << 8)
185#define AS_FAULTADDRESS(as)				(MMU_AS(as) + 0x20)
186#define AS_STATUS(as)					(MMU_AS(as) + 0x28)
187#define   AS_STATUS_AS_ACTIVE				BIT(0)
188#define AS_TRANSCFG(as)					(MMU_AS(as) + 0x30)
189#define   AS_TRANSCFG_ADRMODE_UNMAPPED			(1 << 0)
190#define   AS_TRANSCFG_ADRMODE_IDENTITY			(2 << 0)
191#define   AS_TRANSCFG_ADRMODE_AARCH64_4K		(6 << 0)
192#define   AS_TRANSCFG_ADRMODE_AARCH64_64K		(8 << 0)
193#define   AS_TRANSCFG_INA_BITS(x)			((x) << 6)
194#define   AS_TRANSCFG_OUTA_BITS(x)			((x) << 14)
195#define   AS_TRANSCFG_SL_CONCAT				BIT(22)
196#define   AS_TRANSCFG_PTW_MEMATTR_NC			(1 << 24)
197#define   AS_TRANSCFG_PTW_MEMATTR_WB			(2 << 24)
198#define   AS_TRANSCFG_PTW_SH_NS				(0 << 28)
199#define   AS_TRANSCFG_PTW_SH_OS				(2 << 28)
200#define   AS_TRANSCFG_PTW_SH_IS				(3 << 28)
201#define   AS_TRANSCFG_PTW_RA				BIT(30)
202#define   AS_TRANSCFG_DISABLE_HIER_AP			BIT(33)
203#define   AS_TRANSCFG_DISABLE_AF_FAULT			BIT(34)
204#define   AS_TRANSCFG_WXN				BIT(35)
205#define   AS_TRANSCFG_XREADABLE				BIT(36)
206#define AS_FAULTEXTRA(as)				(MMU_AS(as) + 0x38)
207
208#define CSF_GPU_LATEST_FLUSH_ID				0x10000
209
210#define CSF_DOORBELL(i)					(0x80000 + ((i) * 0x10000))
211#define CSF_GLB_DOORBELL_ID				0
212
213/* PWR Control registers */
214
215#define PWR_CONTROL_BASE				0x800
216#define PWR_CTRL_REG(x)					(PWR_CONTROL_BASE + (x))
217
218#define PWR_INT_RAWSTAT					PWR_CTRL_REG(0x0)
219#define PWR_INT_CLEAR					PWR_CTRL_REG(0x4)
220#define PWR_INT_MASK					PWR_CTRL_REG(0x8)
221#define PWR_INT_STAT					PWR_CTRL_REG(0xc)
222#define   PWR_IRQ_POWER_CHANGED_SINGLE			BIT(0)
223#define   PWR_IRQ_POWER_CHANGED_ALL			BIT(1)
224#define   PWR_IRQ_DELEGATION_CHANGED			BIT(2)
225#define   PWR_IRQ_RESET_COMPLETED			BIT(3)
226#define   PWR_IRQ_RETRACT_COMPLETED			BIT(4)
227#define   PWR_IRQ_INSPECT_COMPLETED			BIT(5)
228#define   PWR_IRQ_COMMAND_NOT_ALLOWED			BIT(30)
229#define   PWR_IRQ_COMMAND_INVALID			BIT(31)
230
231#define PWR_STATUS					PWR_CTRL_REG(0x20)
232#define   PWR_STATUS_ALLOW_L2				BIT_U64(0)
233#define   PWR_STATUS_ALLOW_TILER			BIT_U64(1)
234#define   PWR_STATUS_ALLOW_SHADER			BIT_U64(8)
235#define   PWR_STATUS_ALLOW_BASE				BIT_U64(14)
236#define   PWR_STATUS_ALLOW_STACK			BIT_U64(15)
237#define   PWR_STATUS_DOMAIN_ALLOWED(x)			BIT_U64(x)
238#define   PWR_STATUS_DELEGATED_L2			BIT_U64(16)
239#define   PWR_STATUS_DELEGATED_TILER			BIT_U64(17)
240#define   PWR_STATUS_DELEGATED_SHADER			BIT_U64(24)
241#define   PWR_STATUS_DELEGATED_BASE			BIT_U64(30)
242#define   PWR_STATUS_DELEGATED_STACK			BIT_U64(31)
243#define   PWR_STATUS_DELEGATED_SHIFT			16
244#define   PWR_STATUS_DOMAIN_DELEGATED(x)		BIT_U64((x) + PWR_STATUS_DELEGATED_SHIFT)
245#define   PWR_STATUS_ALLOW_SOFT_RESET			BIT_U64(33)
246#define   PWR_STATUS_ALLOW_FAST_RESET			BIT_U64(34)
247#define   PWR_STATUS_POWER_PENDING			BIT_U64(41)
248#define   PWR_STATUS_RESET_PENDING			BIT_U64(42)
249#define   PWR_STATUS_RETRACT_PENDING			BIT_U64(43)
250#define   PWR_STATUS_INSPECT_PENDING			BIT_U64(44)
251
252#define PWR_COMMAND					PWR_CTRL_REG(0x28)
253#define   PWR_COMMAND_POWER_UP				0x10
254#define   PWR_COMMAND_POWER_DOWN			0x11
255#define   PWR_COMMAND_DELEGATE				0x20
256#define   PWR_COMMAND_RETRACT				0x21
257#define   PWR_COMMAND_RESET_SOFT			0x31
258#define   PWR_COMMAND_RESET_FAST			0x32
259#define   PWR_COMMAND_INSPECT				0xF0
260#define   PWR_COMMAND_DOMAIN_L2				0
261#define   PWR_COMMAND_DOMAIN_TILER			1
262#define   PWR_COMMAND_DOMAIN_SHADER			8
263#define   PWR_COMMAND_DOMAIN_BASE			14
264#define   PWR_COMMAND_DOMAIN_STACK			15
265#define   PWR_COMMAND_SUBDOMAIN_RTU			BIT(0)
266#define   PWR_COMMAND_DEF(cmd, domain, subdomain)	\
267	(((subdomain) << 16) | ((domain) << 8) | (cmd))
268
269#define PWR_CMDARG					PWR_CTRL_REG(0x30)
270
271#define PWR_L2_PRESENT					PWR_CTRL_REG(0x100)
272#define PWR_L2_READY					PWR_CTRL_REG(0x108)
273#define PWR_L2_PWRTRANS					PWR_CTRL_REG(0x110)
274#define PWR_L2_PWRACTIVE				PWR_CTRL_REG(0x118)
275#define PWR_TILER_PRESENT				PWR_CTRL_REG(0x140)
276#define PWR_TILER_READY					PWR_CTRL_REG(0x148)
277#define PWR_TILER_PWRTRANS				PWR_CTRL_REG(0x150)
278#define PWR_TILER_PWRACTIVE				PWR_CTRL_REG(0x158)
279#define PWR_SHADER_PRESENT				PWR_CTRL_REG(0x200)
280#define PWR_SHADER_READY				PWR_CTRL_REG(0x208)
281#define PWR_SHADER_PWRTRANS				PWR_CTRL_REG(0x210)
282#define PWR_SHADER_PWRACTIVE				PWR_CTRL_REG(0x218)
283#define PWR_BASE_PRESENT				PWR_CTRL_REG(0x380)
284#define PWR_BASE_READY					PWR_CTRL_REG(0x388)
285#define PWR_BASE_PWRTRANS				PWR_CTRL_REG(0x390)
286#define PWR_BASE_PWRACTIVE				PWR_CTRL_REG(0x398)
287#define PWR_STACK_PRESENT				PWR_CTRL_REG(0x3c0)
288#define PWR_STACK_READY					PWR_CTRL_REG(0x3c8)
289#define PWR_STACK_PWRTRANS				PWR_CTRL_REG(0x3d0)
290
291#endif