panfrost_device.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
  3/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
  4
  5#ifndef __PANFROST_DEVICE_H__
  6#define __PANFROST_DEVICE_H__
  7
  8#include <linux/atomic.h>
  9#include <linux/io-pgtable.h>
 10#include <linux/pm.h>
 11#include <linux/regulator/consumer.h>
 12#include <linux/spinlock.h>
 13#include <drm/drm_auth.h>
 14#include <drm/drm_device.h>
 15#include <drm/drm_mm.h>
 16#include <drm/gpu_scheduler.h>
 17
 18#include "panfrost_devfreq.h"
 19#include "panfrost_job.h"
 20
 21struct panfrost_device;
 22struct panfrost_mmu;
 23struct panfrost_job_slot;
 24struct panfrost_job;
 25struct panfrost_perfcnt;
 26
 27#define MAX_PM_DOMAINS 5
 28
 29#define ALL_JS_INT_MASK					\
 30	(GENMASK(16 + NUM_JOB_SLOTS - 1, 16) |		\
 31	 GENMASK(NUM_JOB_SLOTS - 1, 0))
 32
 33enum panfrost_drv_comp_bits {
 34	PANFROST_COMP_BIT_GPU,
 35	PANFROST_COMP_BIT_JOB,
 36	PANFROST_COMP_BIT_MMU,
 37	PANFROST_COMP_BIT_MAX
 38};
 39
 40/**
 41 * enum panfrost_gpu_pm - Supported kernel power management features
 42 * @GPU_PM_CLK_DIS:  Allow disabling clocks during system suspend
 43 * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend
 44 * @GPU_PM_RT: Allow disabling clocks and asserting the reset control during
 45 *  system runtime suspend
 46 */
 47enum panfrost_gpu_pm {
 48	GPU_PM_CLK_DIS,
 49	GPU_PM_VREG_OFF,
 50	GPU_PM_RT
 51};
 52
 53/**
 54 * enum panfrost_gpu_quirks - GPU optional quirks
 55 * @GPU_QUIRK_FORCE_AARCH64_PGTABLE: Use AARCH64_4K page table format
 56 */
 57enum panfrost_gpu_quirks {
 58	GPU_QUIRK_FORCE_AARCH64_PGTABLE,
 59};
 60
 61struct panfrost_features {
 62	u16 id;
 63	u16 revision;
 64
 65	u64 shader_present;
 66	u64 tiler_present;
 67	u64 l2_present;
 68	u64 stack_present;
 69	u32 as_present;
 70	u32 js_present;
 71
 72	u32 l2_features;
 73	u32 core_features;
 74	u32 tiler_features;
 75	u32 mem_features;
 76	u32 mmu_features;
 77	u32 thread_features;
 78	u32 max_threads;
 79	u32 thread_max_workgroup_sz;
 80	u32 thread_max_barrier_sz;
 81	u32 coherency_features;
 82	u32 afbc_features;
 83	u32 texture_features[4];
 84	u32 js_features[16];
 85
 86	u32 nr_core_groups;
 87	u32 thread_tls_alloc;
 88
 89	unsigned long hw_features[64 / BITS_PER_LONG];
 90	unsigned long hw_issues[64 / BITS_PER_LONG];
 91};
 92
 93/*
 94 * Features that cannot be automatically detected and need matching using the
 95 * compatible string, typically SoC-specific.
 96 */
 97struct panfrost_compatible {
 98	/* Supplies count and names. */
 99	int num_supplies;
100	const char * const *supply_names;
101	/*
102	 * Number of power domains required, note that values 0 and 1 are
103	 * handled identically, as only values > 1 need special handling.
104	 */
105	int num_pm_domains;
106	/* Only required if num_pm_domains > 1. */
107	const char * const *pm_domain_names;
108
109	/* Vendor implementation quirks callback */
110	void (*vendor_quirk)(struct panfrost_device *pfdev);
111
112	/* Allowed PM features */
113	u8 pm_features;
114
115	/* GPU configuration quirks */
116	u8 gpu_quirks;
117};
118
119/**
120 * struct panfrost_device_debugfs - Device-wide DebugFS tracking structures
121 */
122struct panfrost_device_debugfs {
123	/** @gems_list: Device-wide list of GEM objects owned by at least one file. */
124	struct list_head gems_list;
125
126	/** @gems_lock: Serializes access to the device-wide list of GEM objects. */
127	struct mutex gems_lock;
128};
129
130struct panfrost_device {
131	struct drm_device base;
132	int gpu_irq;
133	int mmu_irq;
134
135	void __iomem *iomem;
136	struct clk *clock;
137	struct clk *bus_clock;
138	struct regulator_bulk_data *regulators;
139	struct reset_control *rstc;
140	/* pm_domains for devices with more than one. */
141	struct device *pm_domain_devs[MAX_PM_DOMAINS];
142	struct device_link *pm_domain_links[MAX_PM_DOMAINS];
143	bool coherent;
144
145	struct panfrost_features features;
146	const struct panfrost_compatible *comp;
147	DECLARE_BITMAP(is_suspended, PANFROST_COMP_BIT_MAX);
148
149	spinlock_t as_lock;
150	unsigned long as_alloc_mask;
151	unsigned long as_faulty_mask;
152	struct list_head as_lru_list;
153
154	struct panfrost_job_slot *js;
155
156	struct panfrost_job *jobs[NUM_JOB_SLOTS][2];
157	struct list_head scheduled_jobs;
158
159	struct panfrost_perfcnt *perfcnt;
160	bool profile_mode;
161
162	struct mutex sched_lock;
163
164	struct {
165		struct workqueue_struct *wq;
166		struct work_struct work;
167		atomic_t pending;
168	} reset;
169
170	struct mutex shrinker_lock;
171	struct list_head shrinker_list;
172	struct shrinker *shrinker;
173
174	struct panfrost_devfreq pfdevfreq;
175
176	struct {
177		atomic_t use_count;
178		spinlock_t lock;
179	} cycle_counter;
180
181#ifdef CONFIG_DEBUG_FS
182	struct panfrost_device_debugfs debugfs;
183#endif
184};
185
186struct panfrost_mmu {
187	struct panfrost_device *pfdev;
188	struct kref refcount;
189	struct io_pgtable_cfg pgtbl_cfg;
190	struct io_pgtable_ops *pgtbl_ops;
191	struct drm_mm mm;
192	spinlock_t mm_lock;
193	int as;
194	atomic_t as_count;
195	struct list_head list;
196	struct {
197		u64 transtab;
198		u64 memattr;
199		u64 transcfg;
200	} cfg;
201};
202
203struct panfrost_engine_usage {
204	unsigned long long elapsed_ns[NUM_JOB_SLOTS];
205	unsigned long long cycles[NUM_JOB_SLOTS];
206};
207
208struct panfrost_file_priv {
209	struct panfrost_device *pfdev;
210
211	struct xarray jm_ctxs;
212
213	struct panfrost_mmu *mmu;
214
215	struct panfrost_engine_usage engine_usage;
216};
217
218static inline bool panfrost_high_prio_allowed(struct drm_file *file)
219{
220	/* Higher priorities require CAP_SYS_NICE or DRM_MASTER */
221	return (capable(CAP_SYS_NICE) || drm_is_current_master(file));
222}
223
224static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev)
225{
226	return container_of(ddev, struct panfrost_device, base);
227}
228
229static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id)
230{
231	s32 match_id = pfdev->features.id;
232
233	if (match_id & 0xf000)
234		match_id &= 0xf00f;
235	return match_id - id;
236}
237
238static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev)
239{
240	return panfrost_model_cmp(pfdev, 0x1000) >= 0;
241}
242
243static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id)
244{
245	return !panfrost_model_cmp(pfdev, id);
246}
247
248int panfrost_unstable_ioctl_check(void);
249
250int panfrost_device_init(struct panfrost_device *pfdev);
251void panfrost_device_fini(struct panfrost_device *pfdev);
252void panfrost_device_reset(struct panfrost_device *pfdev, bool enable_job_int);
253
254extern const struct dev_pm_ops panfrost_pm_ops;
255
256enum drm_panfrost_exception_type {
257	DRM_PANFROST_EXCEPTION_OK = 0x00,
258	DRM_PANFROST_EXCEPTION_DONE = 0x01,
259	DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02,
260	DRM_PANFROST_EXCEPTION_STOPPED = 0x03,
261	DRM_PANFROST_EXCEPTION_TERMINATED = 0x04,
262	DRM_PANFROST_EXCEPTION_KABOOM = 0x05,
263	DRM_PANFROST_EXCEPTION_EUREKA = 0x06,
264	DRM_PANFROST_EXCEPTION_ACTIVE = 0x08,
265	DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f,
266	DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40,
267	DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41,
268	DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42,
269	DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43,
270	DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44,
271	DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48,
272	DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50,
273	DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51,
274	DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52,
275	DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53,
276	DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54,
277	DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55,
278	DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56,
279	DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58,
280	DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59,
281	DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a,
282	DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b,
283	DRM_PANFROST_EXCEPTION_OOM = 0x60,
284	DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61,
285	DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f,
286	DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80,
287	DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88,
288	DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89,
289	DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a,
290	DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0,
291	DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1,
292	DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2,
293	DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3,
294	DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4,
295	DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7,
296	DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8,
297	DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9,
298	DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca,
299	DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb,
300	DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0,
301	DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1,
302	DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2,
303	DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3,
304	DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8,
305	DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9,
306	DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda,
307	DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb,
308	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0,
309	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1,
310	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2,
311	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3,
312	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4,
313	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5,
314	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6,
315	DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7,
316	DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8,
317	DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9,
318	DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea,
319	DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb,
320	DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec,
321	DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed,
322	DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee,
323	DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef,
324};
325
326static inline bool
327panfrost_exception_is_fault(u32 exception_code)
328{
329	return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT;
330}
331
332const char *panfrost_exception_name(u32 exception_code);
333bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
334				    u32 exception_code);
335
336static inline void
337panfrost_device_schedule_reset(struct panfrost_device *pfdev)
338{
339	atomic_set(&pfdev->reset.pending, 1);
340	queue_work(pfdev->reset.wq, &pfdev->reset.work);
341}
342
343#endif