panel-tpo-td028ttec1.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Toppoly TD028TTEC1 Panel Driver
  4 *
  5 * Copyright (C) 2019 Texas Instruments Incorporated
  6 *
  7 * Based on the omapdrm-specific panel-tpo-td028ttec1 driver
  8 *
  9 * Copyright (C) 2008 Nokia Corporation
 10 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
 11 *
 12 * Neo 1973 code (jbt6k74.c):
 13 * Copyright (C) 2006-2007 OpenMoko, Inc.
 14 * Author: Harald Welte <laforge@openmoko.org>
 15 *
 16 * Ported and adapted from Neo 1973 U-Boot by:
 17 * H. Nikolaus Schaller <hns@goldelico.com>
 18 */
 19
 20#include <linux/delay.h>
 21#include <linux/module.h>
 22#include <linux/spi/spi.h>
 23
 24#include <drm/drm_connector.h>
 25#include <drm/drm_modes.h>
 26#include <drm/drm_panel.h>
 27
 28#define JBT_COMMAND			0x000
 29#define JBT_DATA			0x100
 30
 31#define JBT_REG_SLEEP_IN		0x10
 32#define JBT_REG_SLEEP_OUT		0x11
 33
 34#define JBT_REG_DISPLAY_OFF		0x28
 35#define JBT_REG_DISPLAY_ON		0x29
 36
 37#define JBT_REG_RGB_FORMAT		0x3a
 38#define JBT_REG_QUAD_RATE		0x3b
 39
 40#define JBT_REG_POWER_ON_OFF		0xb0
 41#define JBT_REG_BOOSTER_OP		0xb1
 42#define JBT_REG_BOOSTER_MODE		0xb2
 43#define JBT_REG_BOOSTER_FREQ		0xb3
 44#define JBT_REG_OPAMP_SYSCLK		0xb4
 45#define JBT_REG_VSC_VOLTAGE		0xb5
 46#define JBT_REG_VCOM_VOLTAGE		0xb6
 47#define JBT_REG_EXT_DISPL		0xb7
 48#define JBT_REG_OUTPUT_CONTROL		0xb8
 49#define JBT_REG_DCCLK_DCEV		0xb9
 50#define JBT_REG_DISPLAY_MODE1		0xba
 51#define JBT_REG_DISPLAY_MODE2		0xbb
 52#define JBT_REG_DISPLAY_MODE		0xbc
 53#define JBT_REG_ASW_SLEW		0xbd
 54#define JBT_REG_DUMMY_DISPLAY		0xbe
 55#define JBT_REG_DRIVE_SYSTEM		0xbf
 56
 57#define JBT_REG_SLEEP_OUT_FR_A		0xc0
 58#define JBT_REG_SLEEP_OUT_FR_B		0xc1
 59#define JBT_REG_SLEEP_OUT_FR_C		0xc2
 60#define JBT_REG_SLEEP_IN_LCCNT_D	0xc3
 61#define JBT_REG_SLEEP_IN_LCCNT_E	0xc4
 62#define JBT_REG_SLEEP_IN_LCCNT_F	0xc5
 63#define JBT_REG_SLEEP_IN_LCCNT_G	0xc6
 64
 65#define JBT_REG_GAMMA1_FINE_1		0xc7
 66#define JBT_REG_GAMMA1_FINE_2		0xc8
 67#define JBT_REG_GAMMA1_INCLINATION	0xc9
 68#define JBT_REG_GAMMA1_BLUE_OFFSET	0xca
 69
 70#define JBT_REG_BLANK_CONTROL		0xcf
 71#define JBT_REG_BLANK_TH_TV		0xd0
 72#define JBT_REG_CKV_ON_OFF		0xd1
 73#define JBT_REG_CKV_1_2			0xd2
 74#define JBT_REG_OEV_TIMING		0xd3
 75#define JBT_REG_ASW_TIMING_1		0xd4
 76#define JBT_REG_ASW_TIMING_2		0xd5
 77
 78#define JBT_REG_HCLOCK_VGA		0xec
 79#define JBT_REG_HCLOCK_QVGA		0xed
 80
 81struct td028ttec1_panel {
 82	struct drm_panel panel;
 83
 84	struct spi_device *spi;
 85};
 86
 87#define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel)
 88
 89static int
 90jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err)
 91{
 92	struct spi_device *spi = lcd->spi;
 93	u16 tx_buf = JBT_COMMAND | reg;
 94	int ret;
 95
 96	if (err && *err)
 97		return *err;
 98
 99	ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
100	if (ret < 0) {
101		dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
102		if (err)
103			*err = ret;
104	}
105
106	return ret;
107}
108
109static int noinline_for_stack
110jbt_reg_write_1(struct td028ttec1_panel *lcd,
111		u8 reg, u8 data, int *err)
112{
113	struct spi_device *spi = lcd->spi;
114	u16 tx_buf[2];
115	int ret;
116
117	if (err && *err)
118		return *err;
119
120	tx_buf[0] = JBT_COMMAND | reg;
121	tx_buf[1] = JBT_DATA | data;
122
123	ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
124	if (ret < 0) {
125		dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
126		if (err)
127			*err = ret;
128	}
129
130	return ret;
131}
132
133static int noinline_for_stack
134jbt_reg_write_2(struct td028ttec1_panel *lcd,
135		u8 reg, u16 data, int *err)
136{
137	struct spi_device *spi = lcd->spi;
138	u16 tx_buf[3];
139	int ret;
140
141	if (err && *err)
142		return *err;
143
144	tx_buf[0] = JBT_COMMAND | reg;
145	tx_buf[1] = JBT_DATA | (data >> 8);
146	tx_buf[2] = JBT_DATA | (data & 0xff);
147
148	ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
149	if (ret < 0) {
150		dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
151		if (err)
152			*err = ret;
153	}
154
155	return ret;
156}
157
158static int td028ttec1_prepare(struct drm_panel *panel)
159{
160	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
161	unsigned int i;
162	int ret = 0;
163
164	/* Three times command zero */
165	for (i = 0; i < 3; ++i) {
166		jbt_ret_write_0(lcd, 0x00, &ret);
167		usleep_range(1000, 2000);
168	}
169
170	/* deep standby out */
171	jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x17, &ret);
172
173	/* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
174	jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE, 0x80, &ret);
175
176	/* Quad mode off */
177	jbt_reg_write_1(lcd, JBT_REG_QUAD_RATE, 0x00, &ret);
178
179	/* AVDD on, XVDD on */
180	jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x16, &ret);
181
182	/* Output control */
183	jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
184
185	/* Sleep mode off */
186	jbt_ret_write_0(lcd, JBT_REG_SLEEP_OUT, &ret);
187
188	/* at this point we have like 50% grey */
189
190	/* initialize register set */
191	jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE1, 0x01, &ret);
192	jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE2, 0x00, &ret);
193	jbt_reg_write_1(lcd, JBT_REG_RGB_FORMAT, 0x60, &ret);
194	jbt_reg_write_1(lcd, JBT_REG_DRIVE_SYSTEM, 0x10, &ret);
195	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_OP, 0x56, &ret);
196	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_MODE, 0x33, &ret);
197	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
198	jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
199	jbt_reg_write_1(lcd, JBT_REG_OPAMP_SYSCLK, 0x02, &ret);
200	jbt_reg_write_1(lcd, JBT_REG_VSC_VOLTAGE, 0x2b, &ret);
201	jbt_reg_write_1(lcd, JBT_REG_VCOM_VOLTAGE, 0x40, &ret);
202	jbt_reg_write_1(lcd, JBT_REG_EXT_DISPL, 0x03, &ret);
203	jbt_reg_write_1(lcd, JBT_REG_DCCLK_DCEV, 0x04, &ret);
204	/*
205	 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
206	 * to avoid red / blue flicker
207	 */
208	jbt_reg_write_1(lcd, JBT_REG_ASW_SLEW, 0x04, &ret);
209	jbt_reg_write_1(lcd, JBT_REG_DUMMY_DISPLAY, 0x00, &ret);
210
211	jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_A, 0x11, &ret);
212	jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_B, 0x11, &ret);
213	jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_C, 0x11, &ret);
214	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
215	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
216	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
217	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
218
219	jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
220	jbt_reg_write_1(lcd, JBT_REG_GAMMA1_FINE_2, 0x00, &ret);
221	jbt_reg_write_1(lcd, JBT_REG_GAMMA1_INCLINATION, 0x00, &ret);
222	jbt_reg_write_1(lcd, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00, &ret);
223
224	jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
225	jbt_reg_write_1(lcd, JBT_REG_BLANK_CONTROL, 0x02, &ret);
226	jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
227
228	jbt_reg_write_1(lcd, JBT_REG_CKV_ON_OFF, 0x01, &ret);
229	jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
230
231	jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
232	jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
233	jbt_reg_write_1(lcd, JBT_REG_ASW_TIMING_2, 0x0e, &ret);
234
235	return ret;
236}
237
238static int td028ttec1_enable(struct drm_panel *panel)
239{
240	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
241
242	return jbt_ret_write_0(lcd, JBT_REG_DISPLAY_ON, NULL);
243}
244
245static int td028ttec1_disable(struct drm_panel *panel)
246{
247	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
248
249	jbt_ret_write_0(lcd, JBT_REG_DISPLAY_OFF, NULL);
250
251	return 0;
252}
253
254static int td028ttec1_unprepare(struct drm_panel *panel)
255{
256	struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
257
258	jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL);
259	jbt_ret_write_0(lcd, JBT_REG_SLEEP_IN, NULL);
260	jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x00, NULL);
261
262	return 0;
263}
264
265static const struct drm_display_mode td028ttec1_mode = {
266	.clock = 22153,
267	.hdisplay = 480,
268	.hsync_start = 480 + 24,
269	.hsync_end = 480 + 24 + 8,
270	.htotal = 480 + 24 + 8 + 8,
271	.vdisplay = 640,
272	.vsync_start = 640 + 4,
273	.vsync_end = 640 + 4 + 2,
274	.vtotal = 640 + 4 + 2 + 2,
275	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
276	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
277	.width_mm = 43,
278	.height_mm = 58,
279};
280
281static int td028ttec1_get_modes(struct drm_panel *panel,
282				struct drm_connector *connector)
283{
284	struct drm_display_mode *mode;
285
286	mode = drm_mode_duplicate(connector->dev, &td028ttec1_mode);
287	if (!mode)
288		return -ENOMEM;
289
290	drm_mode_set_name(mode);
291	drm_mode_probed_add(connector, mode);
292
293	connector->display_info.width_mm = td028ttec1_mode.width_mm;
294	connector->display_info.height_mm = td028ttec1_mode.height_mm;
295	/*
296	 * FIXME: According to the datasheet sync signals are sampled on the
297	 * rising edge of the clock, but the code running on the OpenMoko Neo
298	 * FreeRunner and Neo 1973 indicates sampling on the falling edge. This
299	 * should be tested on a real device.
300	 */
301	connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
302					  | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
303					  | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE;
304
305	return 1;
306}
307
308static const struct drm_panel_funcs td028ttec1_funcs = {
309	.prepare = td028ttec1_prepare,
310	.enable = td028ttec1_enable,
311	.disable = td028ttec1_disable,
312	.unprepare = td028ttec1_unprepare,
313	.get_modes = td028ttec1_get_modes,
314};
315
316static int td028ttec1_probe(struct spi_device *spi)
317{
318	struct td028ttec1_panel *lcd;
319	int ret;
320
321	lcd = devm_drm_panel_alloc(&spi->dev, struct td028ttec1_panel, panel,
322				   &td028ttec1_funcs,
323				   DRM_MODE_CONNECTOR_DPI);
324	if (IS_ERR(lcd))
325		return PTR_ERR(lcd);
326
327	spi_set_drvdata(spi, lcd);
328	lcd->spi = spi;
329
330	spi->mode = SPI_MODE_3;
331	spi->bits_per_word = 9;
332
333	ret = spi_setup(spi);
334	if (ret < 0) {
335		dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
336		return ret;
337	}
338
339	ret = drm_panel_of_backlight(&lcd->panel);
340	if (ret)
341		return ret;
342
343	drm_panel_add(&lcd->panel);
344
345	return 0;
346}
347
348static void td028ttec1_remove(struct spi_device *spi)
349{
350	struct td028ttec1_panel *lcd = spi_get_drvdata(spi);
351
352	drm_panel_remove(&lcd->panel);
353	drm_panel_disable(&lcd->panel);
354	drm_panel_unprepare(&lcd->panel);
355}
356
357static const struct of_device_id td028ttec1_of_match[] = {
358	{ .compatible = "tpo,td028ttec1", },
359	/* DT backward compatibility. */
360	{ .compatible = "toppoly,td028ttec1", },
361	{ /* sentinel */ },
362};
363
364MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
365
366static const struct spi_device_id td028ttec1_ids[] = {
367	{ "td028ttec1", 0 },
368	{ /* sentinel */ }
369};
370
371MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
372
373static struct spi_driver td028ttec1_driver = {
374	.probe		= td028ttec1_probe,
375	.remove		= td028ttec1_remove,
376	.id_table	= td028ttec1_ids,
377	.driver		= {
378		.name   = "panel-tpo-td028ttec1",
379		.of_match_table = td028ttec1_of_match,
380	},
381};
382
383module_spi_driver(td028ttec1_driver);
384
385MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
386MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
387MODULE_LICENSE("GPL");