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panel-simple.c
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linux-6.19.14/drivers/gpu/drm/panel/panel-simple.c
1/* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24#include <linux/delay.h> 25#include <linux/gpio/consumer.h> 26#include <linux/i2c.h> 27#include <linux/media-bus-format.h> 28#include <linux/module.h> 29#include <linux/of_device.h> 30#include <linux/of_platform.h> 31#include <linux/platform_device.h> 32#include <linux/pm_runtime.h> 33#include <linux/regulator/consumer.h> 34 35#include <video/display_timing.h> 36#include <video/of_display_timing.h> 37#include <video/videomode.h> 38 39#include <drm/drm_crtc.h> 40#include <drm/drm_device.h> 41#include <drm/drm_edid.h> 42#include <drm/drm_mipi_dsi.h> 43#include <drm/drm_panel.h> 44#include <drm/drm_of.h> 45 46/** 47 * struct panel_desc - Describes a simple panel. 48 */ 49struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138}; 139 140struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146}; 147 148struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165}; 166 167static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168{ 169 return container_of(panel, struct panel_simple, base); 170} 171 172static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174{ 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202} 203 204static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206{ 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233} 234 235static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237{ 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279} 280 281static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282{ 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293} 294 295static int panel_simple_disable(struct drm_panel *panel) 296{ 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303} 304 305static int panel_simple_suspend(struct device *dev) 306{ 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317} 318 319static int panel_simple_unprepare(struct drm_panel *panel) 320{ 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329} 330 331static int panel_simple_resume(struct device *dev) 332{ 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350} 351 352static int panel_simple_prepare(struct drm_panel *panel) 353{ 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363} 364 365static int panel_simple_enable(struct drm_panel *panel) 366{ 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373} 374 375static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377{ 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406} 407 408static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411{ 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423} 424 425static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426{ 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430} 431 432static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440}; 441 442static struct panel_desc *panel_dpi_probe(struct device *dev) 443{ 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483} 484 485#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491{ 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530} 531 532static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534{ 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575} 576 577static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578{ 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610} 611 612static struct panel_simple *panel_simple_probe(struct device *dev) 613{ 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752} 753 754static void panel_simple_shutdown(struct device *dev) 755{ 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782} 783 784static void panel_simple_remove(struct device *dev) 785{ 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795} 796 797static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808}; 809 810static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821}; 822 823static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 824 .clock = 9000, 825 .hdisplay = 480, 826 .hsync_start = 480 + 2, 827 .hsync_end = 480 + 2 + 41, 828 .htotal = 480 + 2 + 41 + 2, 829 .vdisplay = 272, 830 .vsync_start = 272 + 2, 831 .vsync_end = 272 + 2 + 10, 832 .vtotal = 272 + 2 + 10 + 2, 833 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 834}; 835 836static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 837 .modes = &ire_am_480272h3tmqw_t01h_mode, 838 .num_modes = 1, 839 .bpc = 8, 840 .size = { 841 .width = 99, 842 .height = 58, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 845}; 846 847static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 848 .clock = 33333, 849 .hdisplay = 800, 850 .hsync_start = 800 + 0, 851 .hsync_end = 800 + 0 + 255, 852 .htotal = 800 + 0 + 255 + 0, 853 .vdisplay = 480, 854 .vsync_start = 480 + 2, 855 .vsync_end = 480 + 2 + 45, 856 .vtotal = 480 + 2 + 45 + 0, 857 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 858}; 859 860static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 861 .pixelclock = { 29930000, 33260000, 36590000 }, 862 .hactive = { 800, 800, 800 }, 863 .hfront_porch = { 1, 40, 168 }, 864 .hback_porch = { 88, 88, 88 }, 865 .hsync_len = { 1, 128, 128 }, 866 .vactive = { 480, 480, 480 }, 867 .vfront_porch = { 1, 35, 37 }, 868 .vback_porch = { 8, 8, 8 }, 869 .vsync_len = { 1, 2, 2 }, 870 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 871 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 872 DISPLAY_FLAGS_SYNC_POSEDGE, 873}; 874 875static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 876 .timings = &ire_am_800480l1tmqw_t00h_timing, 877 .num_timings = 1, 878 .bpc = 8, 879 .size = { 880 .width = 111, 881 .height = 67, 882 }, 883 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 884 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 885 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 886 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 887 .connector_type = DRM_MODE_CONNECTOR_DPI, 888}; 889 890static const struct panel_desc ampire_am800480r3tmqwa1h = { 891 .modes = &ire_am800480r3tmqwa1h_mode, 892 .num_modes = 1, 893 .bpc = 6, 894 .size = { 895 .width = 152, 896 .height = 91, 897 }, 898 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 899}; 900 901static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 902 .pixelclock = { 34500000, 39600000, 50400000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 12, 112, 312 }, 905 .hback_porch = { 87, 87, 48 }, 906 .hsync_len = { 1, 1, 40 }, 907 .vactive = { 600, 600, 600 }, 908 .vfront_porch = { 1, 21, 61 }, 909 .vback_porch = { 38, 38, 19 }, 910 .vsync_len = { 1, 1, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 913 DISPLAY_FLAGS_SYNC_POSEDGE, 914}; 915 916static const struct panel_desc ampire_am800600p5tmqwtb8h = { 917 .timings = &ire_am800600p5tmqw_tb8h_timing, 918 .num_timings = 1, 919 .bpc = 6, 920 .size = { 921 .width = 162, 922 .height = 122, 923 }, 924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 926 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 927 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 928 .connector_type = DRM_MODE_CONNECTOR_DPI, 929}; 930 931static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 932 .pixelclock = { 26400000, 33300000, 46800000 }, 933 .hactive = { 800, 800, 800 }, 934 .hfront_porch = { 16, 210, 354 }, 935 .hback_porch = { 45, 36, 6 }, 936 .hsync_len = { 1, 10, 40 }, 937 .vactive = { 480, 480, 480 }, 938 .vfront_porch = { 7, 22, 147 }, 939 .vback_porch = { 22, 13, 3 }, 940 .vsync_len = { 1, 10, 20 }, 941 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 942 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 943}; 944 945static const struct panel_desc armadeus_st0700_adapt = { 946 .timings = &santek_st0700i5y_rbslw_f_timing, 947 .num_timings = 1, 948 .bpc = 6, 949 .size = { 950 .width = 154, 951 .height = 86, 952 }, 953 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 954 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 955}; 956 957static const struct drm_display_mode auo_b101aw03_mode = { 958 .clock = 51450, 959 .hdisplay = 1024, 960 .hsync_start = 1024 + 156, 961 .hsync_end = 1024 + 156 + 8, 962 .htotal = 1024 + 156 + 8 + 156, 963 .vdisplay = 600, 964 .vsync_start = 600 + 16, 965 .vsync_end = 600 + 16 + 6, 966 .vtotal = 600 + 16 + 6 + 16, 967}; 968 969static const struct panel_desc auo_b101aw03 = { 970 .modes = &auo_b101aw03_mode, 971 .num_modes = 1, 972 .bpc = 6, 973 .size = { 974 .width = 223, 975 .height = 125, 976 }, 977 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 978 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 980}; 981 982static const struct drm_display_mode auo_b101xtn01_mode = { 983 .clock = 72000, 984 .hdisplay = 1366, 985 .hsync_start = 1366 + 20, 986 .hsync_end = 1366 + 20 + 70, 987 .htotal = 1366 + 20 + 70, 988 .vdisplay = 768, 989 .vsync_start = 768 + 14, 990 .vsync_end = 768 + 14 + 42, 991 .vtotal = 768 + 14 + 42, 992 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 993}; 994 995static const struct panel_desc auo_b101xtn01 = { 996 .modes = &auo_b101xtn01_mode, 997 .num_modes = 1, 998 .bpc = 6, 999 .size = { 1000 .width = 223, 1001 .height = 125, 1002 }, 1003}; 1004 1005static const struct drm_display_mode auo_b116xw03_mode = { 1006 .clock = 70589, 1007 .hdisplay = 1366, 1008 .hsync_start = 1366 + 40, 1009 .hsync_end = 1366 + 40 + 40, 1010 .htotal = 1366 + 40 + 40 + 32, 1011 .vdisplay = 768, 1012 .vsync_start = 768 + 10, 1013 .vsync_end = 768 + 10 + 12, 1014 .vtotal = 768 + 10 + 12 + 6, 1015 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1016}; 1017 1018static const struct panel_desc auo_b116xw03 = { 1019 .modes = &auo_b116xw03_mode, 1020 .num_modes = 1, 1021 .bpc = 6, 1022 .size = { 1023 .width = 256, 1024 .height = 144, 1025 }, 1026 .delay = { 1027 .prepare = 1, 1028 .enable = 200, 1029 .disable = 200, 1030 .unprepare = 500, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1035}; 1036 1037static const struct display_timing auo_g070vvn01_timings = { 1038 .pixelclock = { 33300000, 34209000, 45000000 }, 1039 .hactive = { 800, 800, 800 }, 1040 .hfront_porch = { 20, 40, 200 }, 1041 .hback_porch = { 87, 40, 1 }, 1042 .hsync_len = { 1, 48, 87 }, 1043 .vactive = { 480, 480, 480 }, 1044 .vfront_porch = { 5, 13, 200 }, 1045 .vback_porch = { 31, 31, 29 }, 1046 .vsync_len = { 1, 1, 3 }, 1047}; 1048 1049static const struct panel_desc auo_g070vvn01 = { 1050 .timings = &auo_g070vvn01_timings, 1051 .num_timings = 1, 1052 .bpc = 8, 1053 .size = { 1054 .width = 152, 1055 .height = 91, 1056 }, 1057 .delay = { 1058 .prepare = 200, 1059 .enable = 50, 1060 .disable = 50, 1061 .unprepare = 1000, 1062 }, 1063}; 1064 1065static const struct display_timing auo_g101evn010_timing = { 1066 .pixelclock = { 64000000, 68930000, 85000000 }, 1067 .hactive = { 1280, 1280, 1280 }, 1068 .hfront_porch = { 8, 64, 256 }, 1069 .hback_porch = { 8, 64, 256 }, 1070 .hsync_len = { 40, 168, 767 }, 1071 .vactive = { 800, 800, 800 }, 1072 .vfront_porch = { 4, 8, 100 }, 1073 .vback_porch = { 4, 8, 100 }, 1074 .vsync_len = { 8, 16, 223 }, 1075}; 1076 1077static const struct panel_desc auo_g101evn010 = { 1078 .timings = &auo_g101evn010_timing, 1079 .num_timings = 1, 1080 .bpc = 6, 1081 .size = { 1082 .width = 216, 1083 .height = 135, 1084 }, 1085 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1086 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1087 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1088}; 1089 1090static const struct drm_display_mode auo_g104sn02_mode = { 1091 .clock = 40000, 1092 .hdisplay = 800, 1093 .hsync_start = 800 + 40, 1094 .hsync_end = 800 + 40 + 216, 1095 .htotal = 800 + 40 + 216 + 128, 1096 .vdisplay = 600, 1097 .vsync_start = 600 + 10, 1098 .vsync_end = 600 + 10 + 35, 1099 .vtotal = 600 + 10 + 35 + 2, 1100}; 1101 1102static const struct panel_desc auo_g104sn02 = { 1103 .modes = &auo_g104sn02_mode, 1104 .num_modes = 1, 1105 .bpc = 8, 1106 .size = { 1107 .width = 211, 1108 .height = 158, 1109 }, 1110 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1111 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1112}; 1113 1114static const struct drm_display_mode auo_g104stn01_mode = { 1115 .clock = 40000, 1116 .hdisplay = 800, 1117 .hsync_start = 800 + 40, 1118 .hsync_end = 800 + 40 + 88, 1119 .htotal = 800 + 40 + 88 + 128, 1120 .vdisplay = 600, 1121 .vsync_start = 600 + 1, 1122 .vsync_end = 600 + 1 + 23, 1123 .vtotal = 600 + 1 + 23 + 4, 1124}; 1125 1126static const struct panel_desc auo_g104stn01 = { 1127 .modes = &auo_g104stn01_mode, 1128 .num_modes = 1, 1129 .bpc = 8, 1130 .size = { 1131 .width = 211, 1132 .height = 158, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136}; 1137 1138static const struct display_timing auo_g121ean01_timing = { 1139 .pixelclock = { 60000000, 74400000, 90000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 20, 50, 100 }, 1142 .hback_porch = { 20, 50, 100 }, 1143 .hsync_len = { 30, 100, 200 }, 1144 .vactive = { 800, 800, 800 }, 1145 .vfront_porch = { 2, 10, 25 }, 1146 .vback_porch = { 2, 10, 25 }, 1147 .vsync_len = { 4, 18, 50 }, 1148}; 1149 1150static const struct panel_desc auo_g121ean01 = { 1151 .timings = &auo_g121ean01_timing, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 261, 1156 .height = 163, 1157 }, 1158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1160}; 1161 1162static const struct display_timing auo_g133han01_timings = { 1163 .pixelclock = { 134000000, 141200000, 149000000 }, 1164 .hactive = { 1920, 1920, 1920 }, 1165 .hfront_porch = { 39, 58, 77 }, 1166 .hback_porch = { 59, 88, 117 }, 1167 .hsync_len = { 28, 42, 56 }, 1168 .vactive = { 1080, 1080, 1080 }, 1169 .vfront_porch = { 3, 8, 11 }, 1170 .vback_porch = { 5, 14, 19 }, 1171 .vsync_len = { 4, 14, 19 }, 1172}; 1173 1174static const struct panel_desc auo_g133han01 = { 1175 .timings = &auo_g133han01_timings, 1176 .num_timings = 1, 1177 .bpc = 8, 1178 .size = { 1179 .width = 293, 1180 .height = 165, 1181 }, 1182 .delay = { 1183 .prepare = 200, 1184 .enable = 50, 1185 .disable = 50, 1186 .unprepare = 1000, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190}; 1191 1192static const struct display_timing auo_g156han04_timings = { 1193 .pixelclock = { 137000000, 141000000, 146000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 60, 60, 60 }, 1196 .hback_porch = { 90, 92, 111 }, 1197 .hsync_len = { 32, 32, 32 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 12, 12, 12 }, 1200 .vback_porch = { 24, 36, 56 }, 1201 .vsync_len = { 8, 8, 8 }, 1202}; 1203 1204static const struct panel_desc auo_g156han04 = { 1205 .timings = &auo_g156han04_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 344, 1210 .height = 194, 1211 }, 1212 .delay = { 1213 .prepare = 50, /* T2 */ 1214 .enable = 200, /* T3 */ 1215 .disable = 110, /* T10 */ 1216 .unprepare = 1000, /* T13 */ 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1221}; 1222 1223static const struct drm_display_mode auo_g156xtn01_mode = { 1224 .clock = 76000, 1225 .hdisplay = 1366, 1226 .hsync_start = 1366 + 33, 1227 .hsync_end = 1366 + 33 + 67, 1228 .htotal = 1560, 1229 .vdisplay = 768, 1230 .vsync_start = 768 + 4, 1231 .vsync_end = 768 + 4 + 4, 1232 .vtotal = 806, 1233}; 1234 1235static const struct panel_desc auo_g156xtn01 = { 1236 .modes = &auo_g156xtn01_mode, 1237 .num_modes = 1, 1238 .bpc = 8, 1239 .size = { 1240 .width = 344, 1241 .height = 194, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245}; 1246 1247static const struct display_timing auo_g185han01_timings = { 1248 .pixelclock = { 120000000, 144000000, 175000000 }, 1249 .hactive = { 1920, 1920, 1920 }, 1250 .hfront_porch = { 36, 120, 148 }, 1251 .hback_porch = { 24, 88, 108 }, 1252 .hsync_len = { 20, 48, 64 }, 1253 .vactive = { 1080, 1080, 1080 }, 1254 .vfront_porch = { 6, 10, 40 }, 1255 .vback_porch = { 2, 5, 20 }, 1256 .vsync_len = { 2, 5, 20 }, 1257}; 1258 1259static const struct panel_desc auo_g185han01 = { 1260 .timings = &auo_g185han01_timings, 1261 .num_timings = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 409, 1265 .height = 230, 1266 }, 1267 .delay = { 1268 .prepare = 50, 1269 .enable = 200, 1270 .disable = 110, 1271 .unprepare = 1000, 1272 }, 1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1274 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1275}; 1276 1277static const struct display_timing auo_g190ean01_timings = { 1278 .pixelclock = { 90000000, 108000000, 135000000 }, 1279 .hactive = { 1280, 1280, 1280 }, 1280 .hfront_porch = { 126, 184, 1266 }, 1281 .hback_porch = { 84, 122, 844 }, 1282 .hsync_len = { 70, 102, 704 }, 1283 .vactive = { 1024, 1024, 1024 }, 1284 .vfront_porch = { 4, 26, 76 }, 1285 .vback_porch = { 2, 8, 25 }, 1286 .vsync_len = { 2, 8, 25 }, 1287}; 1288 1289static const struct panel_desc auo_g190ean01 = { 1290 .timings = &auo_g190ean01_timings, 1291 .num_timings = 1, 1292 .bpc = 8, 1293 .size = { 1294 .width = 376, 1295 .height = 301, 1296 }, 1297 .delay = { 1298 .prepare = 50, 1299 .enable = 200, 1300 .disable = 110, 1301 .unprepare = 1000, 1302 }, 1303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1304 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1305}; 1306 1307static const struct display_timing auo_p238han01_timings = { 1308 .pixelclock = { 107400000, 142400000, 180000000 }, 1309 .hactive = { 1920, 1920, 1920 }, 1310 .hfront_porch = { 30, 70, 650 }, 1311 .hback_porch = { 30, 70, 650 }, 1312 .hsync_len = { 20, 40, 136 }, 1313 .vactive = { 1080, 1080, 1080 }, 1314 .vfront_porch = { 5, 19, 318 }, 1315 .vback_porch = { 5, 19, 318 }, 1316 .vsync_len = { 4, 12, 120 }, 1317}; 1318 1319static const struct panel_desc auo_p238han01 = { 1320 .timings = &auo_p238han01_timings, 1321 .num_timings = 1, 1322 .bpc = 8, 1323 .size = { 1324 .width = 527, 1325 .height = 296, 1326 }, 1327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1329}; 1330 1331static const struct display_timing auo_p320hvn03_timings = { 1332 .pixelclock = { 106000000, 148500000, 164000000 }, 1333 .hactive = { 1920, 1920, 1920 }, 1334 .hfront_porch = { 25, 50, 130 }, 1335 .hback_porch = { 25, 50, 130 }, 1336 .hsync_len = { 20, 40, 105 }, 1337 .vactive = { 1080, 1080, 1080 }, 1338 .vfront_porch = { 8, 17, 150 }, 1339 .vback_porch = { 8, 17, 150 }, 1340 .vsync_len = { 4, 11, 100 }, 1341}; 1342 1343static const struct panel_desc auo_p320hvn03 = { 1344 .timings = &auo_p320hvn03_timings, 1345 .num_timings = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 698, 1349 .height = 393, 1350 }, 1351 .delay = { 1352 .prepare = 1, 1353 .enable = 450, 1354 .unprepare = 500, 1355 }, 1356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1358}; 1359 1360static const struct drm_display_mode auo_t215hvn01_mode = { 1361 .clock = 148800, 1362 .hdisplay = 1920, 1363 .hsync_start = 1920 + 88, 1364 .hsync_end = 1920 + 88 + 44, 1365 .htotal = 1920 + 88 + 44 + 148, 1366 .vdisplay = 1080, 1367 .vsync_start = 1080 + 4, 1368 .vsync_end = 1080 + 4 + 5, 1369 .vtotal = 1080 + 4 + 5 + 36, 1370}; 1371 1372static const struct panel_desc auo_t215hvn01 = { 1373 .modes = &auo_t215hvn01_mode, 1374 .num_modes = 1, 1375 .bpc = 8, 1376 .size = { 1377 .width = 430, 1378 .height = 270, 1379 }, 1380 .delay = { 1381 .disable = 5, 1382 .unprepare = 1000, 1383 }, 1384 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1386}; 1387 1388static const struct drm_display_mode avic_tm070ddh03_mode = { 1389 .clock = 51200, 1390 .hdisplay = 1024, 1391 .hsync_start = 1024 + 160, 1392 .hsync_end = 1024 + 160 + 4, 1393 .htotal = 1024 + 160 + 4 + 156, 1394 .vdisplay = 600, 1395 .vsync_start = 600 + 17, 1396 .vsync_end = 600 + 17 + 1, 1397 .vtotal = 600 + 17 + 1 + 17, 1398}; 1399 1400static const struct panel_desc avic_tm070ddh03 = { 1401 .modes = &avic_tm070ddh03_mode, 1402 .num_modes = 1, 1403 .bpc = 8, 1404 .size = { 1405 .width = 154, 1406 .height = 90, 1407 }, 1408 .delay = { 1409 .prepare = 20, 1410 .enable = 200, 1411 .disable = 200, 1412 }, 1413}; 1414 1415static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1416 .clock = 30000, 1417 .hdisplay = 800, 1418 .hsync_start = 800 + 40, 1419 .hsync_end = 800 + 40 + 48, 1420 .htotal = 800 + 40 + 48 + 40, 1421 .vdisplay = 480, 1422 .vsync_start = 480 + 13, 1423 .vsync_end = 480 + 13 + 3, 1424 .vtotal = 480 + 13 + 3 + 29, 1425}; 1426 1427static const struct panel_desc bananapi_s070wv20_ct16 = { 1428 .modes = &bananapi_s070wv20_ct16_mode, 1429 .num_modes = 1, 1430 .bpc = 6, 1431 .size = { 1432 .width = 154, 1433 .height = 86, 1434 }, 1435}; 1436 1437static const struct display_timing boe_av101hdt_a10_timing = { 1438 .pixelclock = { 74210000, 75330000, 76780000, }, 1439 .hactive = { 1280, 1280, 1280, }, 1440 .hfront_porch = { 10, 42, 33, }, 1441 .hback_porch = { 10, 18, 33, }, 1442 .hsync_len = { 30, 10, 30, }, 1443 .vactive = { 720, 720, 720, }, 1444 .vfront_porch = { 200, 183, 200, }, 1445 .vback_porch = { 8, 8, 8, }, 1446 .vsync_len = { 2, 19, 2, }, 1447 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1448}; 1449 1450static const struct panel_desc boe_av101hdt_a10 = { 1451 .timings = &boe_av101hdt_a10_timing, 1452 .num_timings = 1, 1453 .bpc = 8, 1454 .size = { 1455 .width = 224, 1456 .height = 126, 1457 }, 1458 .delay = { 1459 .enable = 50, 1460 .disable = 50, 1461 }, 1462 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1464}; 1465 1466static const struct display_timing boe_av123z7m_n17_timing = { 1467 .pixelclock = { 86600000, 88000000, 90800000, }, 1468 .hactive = { 1920, 1920, 1920, }, 1469 .hfront_porch = { 10, 10, 10, }, 1470 .hback_porch = { 10, 10, 10, }, 1471 .hsync_len = { 9, 12, 25, }, 1472 .vactive = { 720, 720, 720, }, 1473 .vfront_porch = { 7, 10, 13, }, 1474 .vback_porch = { 7, 10, 13, }, 1475 .vsync_len = { 7, 11, 14, }, 1476 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1477}; 1478 1479static const struct panel_desc boe_av123z7m_n17 = { 1480 .timings = &boe_av123z7m_n17_timing, 1481 .bpc = 8, 1482 .num_timings = 1, 1483 .size = { 1484 .width = 292, 1485 .height = 110, 1486 }, 1487 .delay = { 1488 .prepare = 50, 1489 .disable = 50, 1490 }, 1491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1493}; 1494 1495static const struct drm_display_mode boe_bp101wx1_100_mode = { 1496 .clock = 78945, 1497 .hdisplay = 1280, 1498 .hsync_start = 1280 + 0, 1499 .hsync_end = 1280 + 0 + 2, 1500 .htotal = 1280 + 62 + 0 + 2, 1501 .vdisplay = 800, 1502 .vsync_start = 800 + 8, 1503 .vsync_end = 800 + 8 + 2, 1504 .vtotal = 800 + 6 + 8 + 2, 1505}; 1506 1507static const struct panel_desc boe_bp082wx1_100 = { 1508 .modes = &boe_bp101wx1_100_mode, 1509 .num_modes = 1, 1510 .bpc = 8, 1511 .size = { 1512 .width = 177, 1513 .height = 110, 1514 }, 1515 .delay = { 1516 .enable = 50, 1517 .disable = 50, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1522}; 1523 1524static const struct panel_desc boe_bp101wx1_100 = { 1525 .modes = &boe_bp101wx1_100_mode, 1526 .num_modes = 1, 1527 .bpc = 8, 1528 .size = { 1529 .width = 217, 1530 .height = 136, 1531 }, 1532 .delay = { 1533 .enable = 50, 1534 .disable = 50, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1537 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1538 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1539}; 1540 1541static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1542 .pixelclock = { 69922000, 71000000, 72293000 }, 1543 .hactive = { 1280, 1280, 1280 }, 1544 .hfront_porch = { 48, 48, 48 }, 1545 .hback_porch = { 80, 80, 80 }, 1546 .hsync_len = { 32, 32, 32 }, 1547 .vactive = { 800, 800, 800 }, 1548 .vfront_porch = { 3, 3, 3 }, 1549 .vback_porch = { 14, 14, 14 }, 1550 .vsync_len = { 6, 6, 6 }, 1551}; 1552 1553static const struct panel_desc boe_ev121wxm_n10_1850 = { 1554 .timings = &boe_ev121wxm_n10_1850_timing, 1555 .num_timings = 1, 1556 .bpc = 8, 1557 .size = { 1558 .width = 261, 1559 .height = 163, 1560 }, 1561 .delay = { 1562 .prepare = 9, 1563 .enable = 300, 1564 .unprepare = 300, 1565 .disable = 560, 1566 }, 1567 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1568 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1569 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1570}; 1571 1572static const struct drm_display_mode boe_hv070wsa_mode = { 1573 .clock = 42105, 1574 .hdisplay = 1024, 1575 .hsync_start = 1024 + 30, 1576 .hsync_end = 1024 + 30 + 30, 1577 .htotal = 1024 + 30 + 30 + 30, 1578 .vdisplay = 600, 1579 .vsync_start = 600 + 10, 1580 .vsync_end = 600 + 10 + 10, 1581 .vtotal = 600 + 10 + 10 + 10, 1582}; 1583 1584static const struct panel_desc boe_hv070wsa = { 1585 .modes = &boe_hv070wsa_mode, 1586 .num_modes = 1, 1587 .bpc = 8, 1588 .size = { 1589 .width = 154, 1590 .height = 90, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1595}; 1596 1597static const struct display_timing cct_cmt430b19n00_timing = { 1598 .pixelclock = { 8000000, 9000000, 12000000 }, 1599 .hactive = { 480, 480, 480 }, 1600 .hfront_porch = { 2, 8, 75 }, 1601 .hback_porch = { 3, 43, 43 }, 1602 .hsync_len = { 2, 4, 75 }, 1603 .vactive = { 272, 272, 272 }, 1604 .vfront_porch = { 2, 8, 37 }, 1605 .vback_porch = { 2, 12, 12 }, 1606 .vsync_len = { 2, 4, 37 }, 1607 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1608}; 1609 1610static const struct panel_desc cct_cmt430b19n00 = { 1611 .timings = &cct_cmt430b19n00_timing, 1612 .num_timings = 1, 1613 .bpc = 8, 1614 .size = { 1615 .width = 95, 1616 .height = 53, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621}; 1622 1623static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1624 .clock = 9000, 1625 .hdisplay = 480, 1626 .hsync_start = 480 + 5, 1627 .hsync_end = 480 + 5 + 5, 1628 .htotal = 480 + 5 + 5 + 40, 1629 .vdisplay = 272, 1630 .vsync_start = 272 + 8, 1631 .vsync_end = 272 + 8 + 8, 1632 .vtotal = 272 + 8 + 8 + 8, 1633 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1634}; 1635 1636static const struct panel_desc cdtech_s043wq26h_ct7 = { 1637 .modes = &cdtech_s043wq26h_ct7_mode, 1638 .num_modes = 1, 1639 .bpc = 8, 1640 .size = { 1641 .width = 95, 1642 .height = 54, 1643 }, 1644 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1645}; 1646 1647/* S070PWS19HP-FC21 2017/04/22 */ 1648static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1649 .clock = 51200, 1650 .hdisplay = 1024, 1651 .hsync_start = 1024 + 160, 1652 .hsync_end = 1024 + 160 + 20, 1653 .htotal = 1024 + 160 + 20 + 140, 1654 .vdisplay = 600, 1655 .vsync_start = 600 + 12, 1656 .vsync_end = 600 + 12 + 3, 1657 .vtotal = 600 + 12 + 3 + 20, 1658 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1659}; 1660 1661static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1662 .modes = &cdtech_s070pws19hp_fc21_mode, 1663 .num_modes = 1, 1664 .bpc = 6, 1665 .size = { 1666 .width = 154, 1667 .height = 86, 1668 }, 1669 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1671 .connector_type = DRM_MODE_CONNECTOR_DPI, 1672}; 1673 1674/* S070SWV29HG-DC44 2017/09/21 */ 1675static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1676 .clock = 33300, 1677 .hdisplay = 800, 1678 .hsync_start = 800 + 210, 1679 .hsync_end = 800 + 210 + 2, 1680 .htotal = 800 + 210 + 2 + 44, 1681 .vdisplay = 480, 1682 .vsync_start = 480 + 22, 1683 .vsync_end = 480 + 22 + 2, 1684 .vtotal = 480 + 22 + 2 + 21, 1685 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1686}; 1687 1688static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1689 .modes = &cdtech_s070swv29hg_dc44_mode, 1690 .num_modes = 1, 1691 .bpc = 6, 1692 .size = { 1693 .width = 154, 1694 .height = 86, 1695 }, 1696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1698 .connector_type = DRM_MODE_CONNECTOR_DPI, 1699}; 1700 1701static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1702 .clock = 35000, 1703 .hdisplay = 800, 1704 .hsync_start = 800 + 40, 1705 .hsync_end = 800 + 40 + 40, 1706 .htotal = 800 + 40 + 40 + 48, 1707 .vdisplay = 480, 1708 .vsync_start = 480 + 29, 1709 .vsync_end = 480 + 29 + 13, 1710 .vtotal = 480 + 29 + 13 + 3, 1711 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1712}; 1713 1714static const struct panel_desc cdtech_s070wv95_ct16 = { 1715 .modes = &cdtech_s070wv95_ct16_mode, 1716 .num_modes = 1, 1717 .bpc = 8, 1718 .size = { 1719 .width = 154, 1720 .height = 85, 1721 }, 1722}; 1723 1724static const struct display_timing chefree_ch101olhlwh_002_timing = { 1725 .pixelclock = { 68900000, 71100000, 73400000 }, 1726 .hactive = { 1280, 1280, 1280 }, 1727 .hfront_porch = { 65, 80, 95 }, 1728 .hback_porch = { 64, 79, 94 }, 1729 .hsync_len = { 1, 1, 1 }, 1730 .vactive = { 800, 800, 800 }, 1731 .vfront_porch = { 7, 11, 14 }, 1732 .vback_porch = { 7, 11, 14 }, 1733 .vsync_len = { 1, 1, 1 }, 1734 .flags = DISPLAY_FLAGS_DE_HIGH, 1735}; 1736 1737static const struct panel_desc chefree_ch101olhlwh_002 = { 1738 .timings = &chefree_ch101olhlwh_002_timing, 1739 .num_timings = 1, 1740 .bpc = 8, 1741 .size = { 1742 .width = 217, 1743 .height = 135, 1744 }, 1745 .delay = { 1746 .enable = 200, 1747 .disable = 200, 1748 }, 1749 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752}; 1753 1754static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1755 .clock = 66770, 1756 .hdisplay = 800, 1757 .hsync_start = 800 + 49, 1758 .hsync_end = 800 + 49 + 33, 1759 .htotal = 800 + 49 + 33 + 17, 1760 .vdisplay = 1280, 1761 .vsync_start = 1280 + 1, 1762 .vsync_end = 1280 + 1 + 7, 1763 .vtotal = 1280 + 1 + 7 + 15, 1764 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1765}; 1766 1767static const struct panel_desc chunghwa_claa070wp03xg = { 1768 .modes = &chunghwa_claa070wp03xg_mode, 1769 .num_modes = 1, 1770 .bpc = 6, 1771 .size = { 1772 .width = 94, 1773 .height = 150, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1776 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1778}; 1779 1780static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1781 .clock = 72070, 1782 .hdisplay = 1366, 1783 .hsync_start = 1366 + 58, 1784 .hsync_end = 1366 + 58 + 58, 1785 .htotal = 1366 + 58 + 58 + 58, 1786 .vdisplay = 768, 1787 .vsync_start = 768 + 4, 1788 .vsync_end = 768 + 4 + 4, 1789 .vtotal = 768 + 4 + 4 + 4, 1790}; 1791 1792static const struct panel_desc chunghwa_claa101wa01a = { 1793 .modes = &chunghwa_claa101wa01a_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 220, 1798 .height = 120, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1802 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1803}; 1804 1805static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1806 .clock = 69300, 1807 .hdisplay = 1366, 1808 .hsync_start = 1366 + 48, 1809 .hsync_end = 1366 + 48 + 32, 1810 .htotal = 1366 + 48 + 32 + 20, 1811 .vdisplay = 768, 1812 .vsync_start = 768 + 16, 1813 .vsync_end = 768 + 16 + 8, 1814 .vtotal = 768 + 16 + 8 + 16, 1815}; 1816 1817static const struct panel_desc chunghwa_claa101wb01 = { 1818 .modes = &chunghwa_claa101wb01_mode, 1819 .num_modes = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 223, 1823 .height = 125, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1828}; 1829 1830static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1831 .pixelclock = { 5000000, 9000000, 12000000 }, 1832 .hactive = { 480, 480, 480 }, 1833 .hfront_porch = { 12, 12, 12 }, 1834 .hback_porch = { 12, 12, 12 }, 1835 .hsync_len = { 21, 21, 21 }, 1836 .vactive = { 272, 272, 272 }, 1837 .vfront_porch = { 4, 4, 4 }, 1838 .vback_porch = { 4, 4, 4 }, 1839 .vsync_len = { 8, 8, 8 }, 1840}; 1841 1842static const struct panel_desc dataimage_fg040346dsswbg04 = { 1843 .timings = &dataimage_fg040346dsswbg04_timing, 1844 .num_timings = 1, 1845 .bpc = 8, 1846 .size = { 1847 .width = 95, 1848 .height = 54, 1849 }, 1850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1851 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1852 .connector_type = DRM_MODE_CONNECTOR_DPI, 1853}; 1854 1855static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1856 .pixelclock = { 68900000, 71110000, 73400000 }, 1857 .hactive = { 1280, 1280, 1280 }, 1858 .vactive = { 800, 800, 800 }, 1859 .hback_porch = { 100, 100, 100 }, 1860 .hfront_porch = { 100, 100, 100 }, 1861 .vback_porch = { 5, 5, 5 }, 1862 .vfront_porch = { 5, 5, 5 }, 1863 .hsync_len = { 24, 24, 24 }, 1864 .vsync_len = { 3, 3, 3 }, 1865 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1866 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1867}; 1868 1869static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1870 .timings = &dataimage_fg1001l0dsswmg01_timing, 1871 .num_timings = 1, 1872 .bpc = 8, 1873 .size = { 1874 .width = 217, 1875 .height = 136, 1876 }, 1877}; 1878 1879static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1880 .clock = 33260, 1881 .hdisplay = 800, 1882 .hsync_start = 800 + 40, 1883 .hsync_end = 800 + 40 + 128, 1884 .htotal = 800 + 40 + 128 + 88, 1885 .vdisplay = 480, 1886 .vsync_start = 480 + 10, 1887 .vsync_end = 480 + 10 + 2, 1888 .vtotal = 480 + 10 + 2 + 33, 1889 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1890}; 1891 1892static const struct panel_desc dataimage_scf0700c48ggu18 = { 1893 .modes = &dataimage_scf0700c48ggu18_mode, 1894 .num_modes = 1, 1895 .bpc = 8, 1896 .size = { 1897 .width = 152, 1898 .height = 91, 1899 }, 1900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1902 .connector_type = DRM_MODE_CONNECTOR_DPI, 1903}; 1904 1905static const struct display_timing dlc_dlc0700yzg_1_timing = { 1906 .pixelclock = { 45000000, 51200000, 57000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 100, 106, 113 }, 1909 .hback_porch = { 100, 106, 113 }, 1910 .hsync_len = { 100, 108, 114 }, 1911 .vactive = { 600, 600, 600 }, 1912 .vfront_porch = { 8, 11, 15 }, 1913 .vback_porch = { 8, 11, 15 }, 1914 .vsync_len = { 9, 13, 15 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916}; 1917 1918static const struct panel_desc dlc_dlc0700yzg_1 = { 1919 .timings = &dlc_dlc0700yzg_1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 154, 1924 .height = 86, 1925 }, 1926 .delay = { 1927 .prepare = 30, 1928 .enable = 200, 1929 .disable = 200, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1933}; 1934 1935static const struct display_timing dlc_dlc1010gig_timing = { 1936 .pixelclock = { 68900000, 71100000, 73400000 }, 1937 .hactive = { 1280, 1280, 1280 }, 1938 .hfront_porch = { 43, 53, 63 }, 1939 .hback_porch = { 43, 53, 63 }, 1940 .hsync_len = { 44, 54, 64 }, 1941 .vactive = { 800, 800, 800 }, 1942 .vfront_porch = { 5, 8, 11 }, 1943 .vback_porch = { 5, 8, 11 }, 1944 .vsync_len = { 5, 7, 11 }, 1945 .flags = DISPLAY_FLAGS_DE_HIGH, 1946}; 1947 1948static const struct panel_desc dlc_dlc1010gig = { 1949 .timings = &dlc_dlc1010gig_timing, 1950 .num_timings = 1, 1951 .bpc = 8, 1952 .size = { 1953 .width = 216, 1954 .height = 135, 1955 }, 1956 .delay = { 1957 .prepare = 60, 1958 .enable = 150, 1959 .disable = 100, 1960 .unprepare = 60, 1961 }, 1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1964}; 1965 1966static const struct drm_display_mode edt_et035012dm6_mode = { 1967 .clock = 6500, 1968 .hdisplay = 320, 1969 .hsync_start = 320 + 20, 1970 .hsync_end = 320 + 20 + 30, 1971 .htotal = 320 + 20 + 68, 1972 .vdisplay = 240, 1973 .vsync_start = 240 + 4, 1974 .vsync_end = 240 + 4 + 4, 1975 .vtotal = 240 + 4 + 4 + 14, 1976 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1977}; 1978 1979static const struct panel_desc edt_et035012dm6 = { 1980 .modes = &edt_et035012dm6_mode, 1981 .num_modes = 1, 1982 .bpc = 8, 1983 .size = { 1984 .width = 70, 1985 .height = 52, 1986 }, 1987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1988 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1989}; 1990 1991static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1992 .clock = 6520, 1993 .hdisplay = 320, 1994 .hsync_start = 320 + 20, 1995 .hsync_end = 320 + 20 + 68, 1996 .htotal = 320 + 20 + 68, 1997 .vdisplay = 240, 1998 .vsync_start = 240 + 4, 1999 .vsync_end = 240 + 4 + 18, 2000 .vtotal = 240 + 4 + 18, 2001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2002}; 2003 2004static const struct panel_desc edt_etm0350g0dh6 = { 2005 .modes = &edt_etm0350g0dh6_mode, 2006 .num_modes = 1, 2007 .bpc = 6, 2008 .size = { 2009 .width = 70, 2010 .height = 53, 2011 }, 2012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2014 .connector_type = DRM_MODE_CONNECTOR_DPI, 2015}; 2016 2017static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2018 .clock = 10870, 2019 .hdisplay = 480, 2020 .hsync_start = 480 + 8, 2021 .hsync_end = 480 + 8 + 4, 2022 .htotal = 480 + 8 + 4 + 41, 2023 2024 /* 2025 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2026 * fb_align 2027 */ 2028 2029 .vdisplay = 288, 2030 .vsync_start = 288 + 2, 2031 .vsync_end = 288 + 2 + 4, 2032 .vtotal = 288 + 2 + 4 + 10, 2033}; 2034 2035static const struct panel_desc edt_etm043080dh6gp = { 2036 .modes = &edt_etm043080dh6gp_mode, 2037 .num_modes = 1, 2038 .bpc = 8, 2039 .size = { 2040 .width = 100, 2041 .height = 65, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2044 .connector_type = DRM_MODE_CONNECTOR_DPI, 2045}; 2046 2047static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2048 .clock = 9000, 2049 .hdisplay = 480, 2050 .hsync_start = 480 + 2, 2051 .hsync_end = 480 + 2 + 41, 2052 .htotal = 480 + 2 + 41 + 2, 2053 .vdisplay = 272, 2054 .vsync_start = 272 + 2, 2055 .vsync_end = 272 + 2 + 10, 2056 .vtotal = 272 + 2 + 10 + 2, 2057 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2058}; 2059 2060static const struct panel_desc edt_etm0430g0dh6 = { 2061 .modes = &edt_etm0430g0dh6_mode, 2062 .num_modes = 1, 2063 .bpc = 6, 2064 .size = { 2065 .width = 95, 2066 .height = 54, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2070 .connector_type = DRM_MODE_CONNECTOR_DPI, 2071}; 2072 2073static const struct drm_display_mode edt_et057090dhu_mode = { 2074 .clock = 25175, 2075 .hdisplay = 640, 2076 .hsync_start = 640 + 16, 2077 .hsync_end = 640 + 16 + 30, 2078 .htotal = 640 + 16 + 30 + 114, 2079 .vdisplay = 480, 2080 .vsync_start = 480 + 10, 2081 .vsync_end = 480 + 10 + 3, 2082 .vtotal = 480 + 10 + 3 + 32, 2083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2084}; 2085 2086static const struct panel_desc edt_et057090dhu = { 2087 .modes = &edt_et057090dhu_mode, 2088 .num_modes = 1, 2089 .bpc = 6, 2090 .size = { 2091 .width = 115, 2092 .height = 86, 2093 }, 2094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2096 .connector_type = DRM_MODE_CONNECTOR_DPI, 2097}; 2098 2099static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2100 .clock = 33260, 2101 .hdisplay = 800, 2102 .hsync_start = 800 + 40, 2103 .hsync_end = 800 + 40 + 128, 2104 .htotal = 800 + 40 + 128 + 88, 2105 .vdisplay = 480, 2106 .vsync_start = 480 + 10, 2107 .vsync_end = 480 + 10 + 2, 2108 .vtotal = 480 + 10 + 2 + 33, 2109 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2110}; 2111 2112static const struct panel_desc edt_etm0700g0dh6 = { 2113 .modes = &edt_etm0700g0dh6_mode, 2114 .num_modes = 1, 2115 .bpc = 6, 2116 .size = { 2117 .width = 152, 2118 .height = 91, 2119 }, 2120 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2121 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2122 .connector_type = DRM_MODE_CONNECTOR_DPI, 2123}; 2124 2125static const struct panel_desc edt_etm0700g0bdh6 = { 2126 .modes = &edt_etm0700g0dh6_mode, 2127 .num_modes = 1, 2128 .bpc = 6, 2129 .size = { 2130 .width = 152, 2131 .height = 91, 2132 }, 2133 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2134 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2135 .connector_type = DRM_MODE_CONNECTOR_DPI, 2136}; 2137 2138static const struct display_timing edt_etml0700y5dha_timing = { 2139 .pixelclock = { 40800000, 51200000, 67200000 }, 2140 .hactive = { 1024, 1024, 1024 }, 2141 .hfront_porch = { 30, 106, 125 }, 2142 .hback_porch = { 30, 106, 125 }, 2143 .hsync_len = { 30, 108, 126 }, 2144 .vactive = { 600, 600, 600 }, 2145 .vfront_porch = { 3, 12, 67}, 2146 .vback_porch = { 3, 12, 67 }, 2147 .vsync_len = { 4, 11, 66 }, 2148 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2149 DISPLAY_FLAGS_DE_HIGH, 2150}; 2151 2152static const struct panel_desc edt_etml0700y5dha = { 2153 .timings = &edt_etml0700y5dha_timing, 2154 .num_timings = 1, 2155 .bpc = 8, 2156 .size = { 2157 .width = 155, 2158 .height = 86, 2159 }, 2160 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2161 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2162}; 2163 2164static const struct display_timing edt_etml1010g3dra_timing = { 2165 .pixelclock = { 66300000, 72400000, 78900000 }, 2166 .hactive = { 1280, 1280, 1280 }, 2167 .hfront_porch = { 12, 72, 132 }, 2168 .hback_porch = { 86, 86, 86 }, 2169 .hsync_len = { 2, 2, 2 }, 2170 .vactive = { 800, 800, 800 }, 2171 .vfront_porch = { 1, 15, 49 }, 2172 .vback_porch = { 21, 21, 21 }, 2173 .vsync_len = { 2, 2, 2 }, 2174 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2175 DISPLAY_FLAGS_DE_HIGH, 2176}; 2177 2178static const struct panel_desc edt_etml1010g3dra = { 2179 .timings = &edt_etml1010g3dra_timing, 2180 .num_timings = 1, 2181 .bpc = 8, 2182 .size = { 2183 .width = 216, 2184 .height = 135, 2185 }, 2186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2187 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2189}; 2190 2191static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2192 .clock = 25175, 2193 .hdisplay = 640, 2194 .hsync_start = 640, 2195 .hsync_end = 640 + 16, 2196 .htotal = 640 + 16 + 30 + 114, 2197 .vdisplay = 480, 2198 .vsync_start = 480 + 10, 2199 .vsync_end = 480 + 10 + 3, 2200 .vtotal = 480 + 10 + 3 + 35, 2201 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2202}; 2203 2204static const struct panel_desc edt_etmv570g2dhu = { 2205 .modes = &edt_etmv570g2dhu_mode, 2206 .num_modes = 1, 2207 .bpc = 6, 2208 .size = { 2209 .width = 115, 2210 .height = 86, 2211 }, 2212 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2213 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2214 .connector_type = DRM_MODE_CONNECTOR_DPI, 2215}; 2216 2217static const struct display_timing eink_vb3300_kca_timing = { 2218 .pixelclock = { 40000000, 40000000, 40000000 }, 2219 .hactive = { 334, 334, 334 }, 2220 .hfront_porch = { 1, 1, 1 }, 2221 .hback_porch = { 1, 1, 1 }, 2222 .hsync_len = { 1, 1, 1 }, 2223 .vactive = { 1405, 1405, 1405 }, 2224 .vfront_porch = { 1, 1, 1 }, 2225 .vback_porch = { 1, 1, 1 }, 2226 .vsync_len = { 1, 1, 1 }, 2227 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2228 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2229}; 2230 2231static const struct panel_desc eink_vb3300_kca = { 2232 .timings = &eink_vb3300_kca_timing, 2233 .num_timings = 1, 2234 .bpc = 6, 2235 .size = { 2236 .width = 157, 2237 .height = 209, 2238 }, 2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2240 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2241 .connector_type = DRM_MODE_CONNECTOR_DPI, 2242}; 2243 2244static const struct display_timing evervision_vgg644804_timing = { 2245 .pixelclock = { 25175000, 25175000, 25175000 }, 2246 .hactive = { 640, 640, 640 }, 2247 .hfront_porch = { 16, 16, 16 }, 2248 .hback_porch = { 82, 114, 170 }, 2249 .hsync_len = { 5, 30, 30 }, 2250 .vactive = { 480, 480, 480 }, 2251 .vfront_porch = { 10, 10, 10 }, 2252 .vback_porch = { 30, 32, 34 }, 2253 .vsync_len = { 1, 3, 5 }, 2254 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2255 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2256 DISPLAY_FLAGS_SYNC_POSEDGE, 2257}; 2258 2259static const struct panel_desc evervision_vgg644804 = { 2260 .timings = &evervision_vgg644804_timing, 2261 .num_timings = 1, 2262 .bpc = 6, 2263 .size = { 2264 .width = 115, 2265 .height = 86, 2266 }, 2267 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2268 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2269 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2270}; 2271 2272static const struct display_timing evervision_vgg804821_timing = { 2273 .pixelclock = { 27600000, 33300000, 50000000 }, 2274 .hactive = { 800, 800, 800 }, 2275 .hfront_porch = { 40, 66, 70 }, 2276 .hback_porch = { 40, 67, 70 }, 2277 .hsync_len = { 40, 67, 70 }, 2278 .vactive = { 480, 480, 480 }, 2279 .vfront_porch = { 6, 10, 10 }, 2280 .vback_porch = { 7, 11, 11 }, 2281 .vsync_len = { 7, 11, 11 }, 2282 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2283 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2284 DISPLAY_FLAGS_SYNC_NEGEDGE, 2285}; 2286 2287static const struct panel_desc evervision_vgg804821 = { 2288 .timings = &evervision_vgg804821_timing, 2289 .num_timings = 1, 2290 .bpc = 8, 2291 .size = { 2292 .width = 108, 2293 .height = 64, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2296 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2297}; 2298 2299static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2300 .clock = 32260, 2301 .hdisplay = 800, 2302 .hsync_start = 800 + 168, 2303 .hsync_end = 800 + 168 + 64, 2304 .htotal = 800 + 168 + 64 + 88, 2305 .vdisplay = 480, 2306 .vsync_start = 480 + 37, 2307 .vsync_end = 480 + 37 + 2, 2308 .vtotal = 480 + 37 + 2 + 8, 2309}; 2310 2311static const struct panel_desc foxlink_fl500wvr00_a0t = { 2312 .modes = &foxlink_fl500wvr00_a0t_mode, 2313 .num_modes = 1, 2314 .bpc = 8, 2315 .size = { 2316 .width = 108, 2317 .height = 65, 2318 }, 2319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2320}; 2321 2322static const struct drm_display_mode frida_frd350h54004_modes[] = { 2323 { /* 60 Hz */ 2324 .clock = 6000, 2325 .hdisplay = 320, 2326 .hsync_start = 320 + 44, 2327 .hsync_end = 320 + 44 + 16, 2328 .htotal = 320 + 44 + 16 + 20, 2329 .vdisplay = 240, 2330 .vsync_start = 240 + 2, 2331 .vsync_end = 240 + 2 + 6, 2332 .vtotal = 240 + 2 + 6 + 2, 2333 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2334 }, 2335 { /* 50 Hz */ 2336 .clock = 5400, 2337 .hdisplay = 320, 2338 .hsync_start = 320 + 56, 2339 .hsync_end = 320 + 56 + 16, 2340 .htotal = 320 + 56 + 16 + 40, 2341 .vdisplay = 240, 2342 .vsync_start = 240 + 2, 2343 .vsync_end = 240 + 2 + 6, 2344 .vtotal = 240 + 2 + 6 + 2, 2345 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2346 }, 2347}; 2348 2349static const struct panel_desc frida_frd350h54004 = { 2350 .modes = frida_frd350h54004_modes, 2351 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2352 .bpc = 8, 2353 .size = { 2354 .width = 77, 2355 .height = 64, 2356 }, 2357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2359 .connector_type = DRM_MODE_CONNECTOR_DPI, 2360}; 2361 2362static const struct drm_display_mode friendlyarm_hd702e_mode = { 2363 .clock = 67185, 2364 .hdisplay = 800, 2365 .hsync_start = 800 + 20, 2366 .hsync_end = 800 + 20 + 24, 2367 .htotal = 800 + 20 + 24 + 20, 2368 .vdisplay = 1280, 2369 .vsync_start = 1280 + 4, 2370 .vsync_end = 1280 + 4 + 8, 2371 .vtotal = 1280 + 4 + 8 + 4, 2372 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2373}; 2374 2375static const struct panel_desc friendlyarm_hd702e = { 2376 .modes = &friendlyarm_hd702e_mode, 2377 .num_modes = 1, 2378 .size = { 2379 .width = 94, 2380 .height = 151, 2381 }, 2382}; 2383 2384static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2385 .clock = 9000, 2386 .hdisplay = 480, 2387 .hsync_start = 480 + 5, 2388 .hsync_end = 480 + 5 + 1, 2389 .htotal = 480 + 5 + 1 + 40, 2390 .vdisplay = 272, 2391 .vsync_start = 272 + 8, 2392 .vsync_end = 272 + 8 + 1, 2393 .vtotal = 272 + 8 + 1 + 8, 2394}; 2395 2396static const struct panel_desc giantplus_gpg482739qs5 = { 2397 .modes = &giantplus_gpg482739qs5_mode, 2398 .num_modes = 1, 2399 .bpc = 8, 2400 .size = { 2401 .width = 95, 2402 .height = 54, 2403 }, 2404 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2405}; 2406 2407static const struct display_timing giantplus_gpm940b0_timing = { 2408 .pixelclock = { 13500000, 27000000, 27500000 }, 2409 .hactive = { 320, 320, 320 }, 2410 .hfront_porch = { 14, 686, 718 }, 2411 .hback_porch = { 50, 70, 255 }, 2412 .hsync_len = { 1, 1, 1 }, 2413 .vactive = { 240, 240, 240 }, 2414 .vfront_porch = { 1, 1, 179 }, 2415 .vback_porch = { 1, 21, 31 }, 2416 .vsync_len = { 1, 1, 6 }, 2417 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2418}; 2419 2420static const struct panel_desc giantplus_gpm940b0 = { 2421 .timings = &giantplus_gpm940b0_timing, 2422 .num_timings = 1, 2423 .bpc = 8, 2424 .size = { 2425 .width = 60, 2426 .height = 45, 2427 }, 2428 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2429 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2430}; 2431 2432static const struct display_timing hannstar_hsd070pww1_timing = { 2433 .pixelclock = { 64300000, 71100000, 82000000 }, 2434 .hactive = { 1280, 1280, 1280 }, 2435 .hfront_porch = { 1, 1, 10 }, 2436 .hback_porch = { 1, 1, 10 }, 2437 /* 2438 * According to the data sheet, the minimum horizontal blanking interval 2439 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2440 * minimum working horizontal blanking interval to be 60 clocks. 2441 */ 2442 .hsync_len = { 58, 158, 661 }, 2443 .vactive = { 800, 800, 800 }, 2444 .vfront_porch = { 1, 1, 10 }, 2445 .vback_porch = { 1, 1, 10 }, 2446 .vsync_len = { 1, 21, 203 }, 2447 .flags = DISPLAY_FLAGS_DE_HIGH, 2448}; 2449 2450static const struct panel_desc hannstar_hsd070pww1 = { 2451 .timings = &hannstar_hsd070pww1_timing, 2452 .num_timings = 1, 2453 .bpc = 6, 2454 .size = { 2455 .width = 151, 2456 .height = 94, 2457 }, 2458 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2459 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2460}; 2461 2462static const struct display_timing hannstar_hsd100pxn1_timing = { 2463 .pixelclock = { 55000000, 65000000, 75000000 }, 2464 .hactive = { 1024, 1024, 1024 }, 2465 .hfront_porch = { 40, 40, 40 }, 2466 .hback_porch = { 220, 220, 220 }, 2467 .hsync_len = { 20, 60, 100 }, 2468 .vactive = { 768, 768, 768 }, 2469 .vfront_porch = { 7, 7, 7 }, 2470 .vback_porch = { 21, 21, 21 }, 2471 .vsync_len = { 10, 10, 10 }, 2472 .flags = DISPLAY_FLAGS_DE_HIGH, 2473}; 2474 2475static const struct panel_desc hannstar_hsd100pxn1 = { 2476 .timings = &hannstar_hsd100pxn1_timing, 2477 .num_timings = 1, 2478 .bpc = 6, 2479 .size = { 2480 .width = 203, 2481 .height = 152, 2482 }, 2483 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2484 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2485}; 2486 2487static const struct display_timing hannstar_hsd101pww2_timing = { 2488 .pixelclock = { 64300000, 71100000, 82000000 }, 2489 .hactive = { 1280, 1280, 1280 }, 2490 .hfront_porch = { 1, 1, 10 }, 2491 .hback_porch = { 1, 1, 10 }, 2492 .hsync_len = { 58, 158, 661 }, 2493 .vactive = { 800, 800, 800 }, 2494 .vfront_porch = { 1, 1, 10 }, 2495 .vback_porch = { 1, 1, 10 }, 2496 .vsync_len = { 1, 21, 203 }, 2497 .flags = DISPLAY_FLAGS_DE_HIGH, 2498}; 2499 2500static const struct panel_desc hannstar_hsd101pww2 = { 2501 .timings = &hannstar_hsd101pww2_timing, 2502 .num_timings = 1, 2503 .bpc = 8, 2504 .size = { 2505 .width = 217, 2506 .height = 136, 2507 }, 2508 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2510}; 2511 2512static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2513 .clock = 33333, 2514 .hdisplay = 800, 2515 .hsync_start = 800 + 85, 2516 .hsync_end = 800 + 85 + 86, 2517 .htotal = 800 + 85 + 86 + 85, 2518 .vdisplay = 480, 2519 .vsync_start = 480 + 16, 2520 .vsync_end = 480 + 16 + 13, 2521 .vtotal = 480 + 16 + 13 + 16, 2522}; 2523 2524static const struct panel_desc hitachi_tx23d38vm0caa = { 2525 .modes = &hitachi_tx23d38vm0caa_mode, 2526 .num_modes = 1, 2527 .bpc = 6, 2528 .size = { 2529 .width = 195, 2530 .height = 117, 2531 }, 2532 .delay = { 2533 .enable = 160, 2534 .disable = 160, 2535 }, 2536}; 2537 2538static const struct drm_display_mode innolux_at043tn24_mode = { 2539 .clock = 9000, 2540 .hdisplay = 480, 2541 .hsync_start = 480 + 2, 2542 .hsync_end = 480 + 2 + 41, 2543 .htotal = 480 + 2 + 41 + 2, 2544 .vdisplay = 272, 2545 .vsync_start = 272 + 2, 2546 .vsync_end = 272 + 2 + 10, 2547 .vtotal = 272 + 2 + 10 + 2, 2548 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2549}; 2550 2551static const struct panel_desc innolux_at043tn24 = { 2552 .modes = &innolux_at043tn24_mode, 2553 .num_modes = 1, 2554 .bpc = 8, 2555 .size = { 2556 .width = 95, 2557 .height = 54, 2558 }, 2559 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2560 .connector_type = DRM_MODE_CONNECTOR_DPI, 2561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2562}; 2563 2564static const struct drm_display_mode innolux_at070tn92_mode = { 2565 .clock = 33333, 2566 .hdisplay = 800, 2567 .hsync_start = 800 + 210, 2568 .hsync_end = 800 + 210 + 20, 2569 .htotal = 800 + 210 + 20 + 46, 2570 .vdisplay = 480, 2571 .vsync_start = 480 + 22, 2572 .vsync_end = 480 + 22 + 10, 2573 .vtotal = 480 + 22 + 23 + 10, 2574}; 2575 2576static const struct panel_desc innolux_at070tn92 = { 2577 .modes = &innolux_at070tn92_mode, 2578 .num_modes = 1, 2579 .size = { 2580 .width = 154, 2581 .height = 86, 2582 }, 2583 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2584}; 2585 2586static const struct display_timing innolux_g070ace_l01_timing = { 2587 .pixelclock = { 25200000, 35000000, 35700000 }, 2588 .hactive = { 800, 800, 800 }, 2589 .hfront_porch = { 30, 32, 87 }, 2590 .hback_porch = { 30, 32, 87 }, 2591 .hsync_len = { 1, 1, 1 }, 2592 .vactive = { 480, 480, 480 }, 2593 .vfront_porch = { 3, 3, 3 }, 2594 .vback_porch = { 13, 13, 13 }, 2595 .vsync_len = { 1, 1, 4 }, 2596 .flags = DISPLAY_FLAGS_DE_HIGH, 2597}; 2598 2599static const struct panel_desc innolux_g070ace_l01 = { 2600 .timings = &innolux_g070ace_l01_timing, 2601 .num_timings = 1, 2602 .bpc = 8, 2603 .size = { 2604 .width = 152, 2605 .height = 91, 2606 }, 2607 .delay = { 2608 .prepare = 10, 2609 .enable = 50, 2610 .disable = 50, 2611 .unprepare = 500, 2612 }, 2613 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2614 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2615 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2616}; 2617 2618static const struct display_timing innolux_g070y2_l01_timing = { 2619 .pixelclock = { 28000000, 29500000, 32000000 }, 2620 .hactive = { 800, 800, 800 }, 2621 .hfront_porch = { 61, 91, 141 }, 2622 .hback_porch = { 60, 90, 140 }, 2623 .hsync_len = { 12, 12, 12 }, 2624 .vactive = { 480, 480, 480 }, 2625 .vfront_porch = { 4, 9, 30 }, 2626 .vback_porch = { 4, 8, 28 }, 2627 .vsync_len = { 2, 2, 2 }, 2628 .flags = DISPLAY_FLAGS_DE_HIGH, 2629}; 2630 2631static const struct panel_desc innolux_g070y2_l01 = { 2632 .timings = &innolux_g070y2_l01_timing, 2633 .num_timings = 1, 2634 .bpc = 8, 2635 .size = { 2636 .width = 152, 2637 .height = 91, 2638 }, 2639 .delay = { 2640 .prepare = 10, 2641 .enable = 100, 2642 .disable = 100, 2643 .unprepare = 800, 2644 }, 2645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2646 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2647 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2648}; 2649 2650static const struct display_timing innolux_g070ace_lh3_timing = { 2651 .pixelclock = { 25200000, 25400000, 35700000 }, 2652 .hactive = { 800, 800, 800 }, 2653 .hfront_porch = { 30, 32, 87 }, 2654 .hback_porch = { 29, 31, 86 }, 2655 .hsync_len = { 1, 1, 1 }, 2656 .vactive = { 480, 480, 480 }, 2657 .vfront_porch = { 4, 5, 65 }, 2658 .vback_porch = { 3, 4, 65 }, 2659 .vsync_len = { 1, 1, 1 }, 2660 .flags = DISPLAY_FLAGS_DE_HIGH, 2661}; 2662 2663static const struct panel_desc innolux_g070ace_lh3 = { 2664 .timings = &innolux_g070ace_lh3_timing, 2665 .num_timings = 1, 2666 .bpc = 8, 2667 .size = { 2668 .width = 152, 2669 .height = 91, 2670 }, 2671 .delay = { 2672 .prepare = 10, 2673 .enable = 450, 2674 .disable = 200, 2675 .unprepare = 510, 2676 }, 2677 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2678 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2679 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2680}; 2681 2682static const struct drm_display_mode innolux_g070y2_t02_mode = { 2683 .clock = 33333, 2684 .hdisplay = 800, 2685 .hsync_start = 800 + 210, 2686 .hsync_end = 800 + 210 + 20, 2687 .htotal = 800 + 210 + 20 + 46, 2688 .vdisplay = 480, 2689 .vsync_start = 480 + 22, 2690 .vsync_end = 480 + 22 + 10, 2691 .vtotal = 480 + 22 + 23 + 10, 2692}; 2693 2694static const struct panel_desc innolux_g070y2_t02 = { 2695 .modes = &innolux_g070y2_t02_mode, 2696 .num_modes = 1, 2697 .bpc = 8, 2698 .size = { 2699 .width = 152, 2700 .height = 92, 2701 }, 2702 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2703 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2704 .connector_type = DRM_MODE_CONNECTOR_DPI, 2705}; 2706 2707static const struct display_timing innolux_g101ice_l01_timing = { 2708 .pixelclock = { 60400000, 71100000, 74700000 }, 2709 .hactive = { 1280, 1280, 1280 }, 2710 .hfront_porch = { 30, 60, 70 }, 2711 .hback_porch = { 30, 60, 70 }, 2712 .hsync_len = { 22, 40, 60 }, 2713 .vactive = { 800, 800, 800 }, 2714 .vfront_porch = { 3, 8, 14 }, 2715 .vback_porch = { 3, 8, 14 }, 2716 .vsync_len = { 4, 7, 12 }, 2717 .flags = DISPLAY_FLAGS_DE_HIGH, 2718}; 2719 2720static const struct panel_desc innolux_g101ice_l01 = { 2721 .timings = &innolux_g101ice_l01_timing, 2722 .num_timings = 1, 2723 .bpc = 8, 2724 .size = { 2725 .width = 217, 2726 .height = 135, 2727 }, 2728 .delay = { 2729 .enable = 200, 2730 .disable = 200, 2731 }, 2732 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2733 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2734 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2735}; 2736 2737static const struct display_timing innolux_g121i1_l01_timing = { 2738 .pixelclock = { 67450000, 71000000, 74550000 }, 2739 .hactive = { 1280, 1280, 1280 }, 2740 .hfront_porch = { 40, 80, 160 }, 2741 .hback_porch = { 39, 79, 159 }, 2742 .hsync_len = { 1, 1, 1 }, 2743 .vactive = { 800, 800, 800 }, 2744 .vfront_porch = { 5, 11, 100 }, 2745 .vback_porch = { 4, 11, 99 }, 2746 .vsync_len = { 1, 1, 1 }, 2747}; 2748 2749static const struct panel_desc innolux_g121i1_l01 = { 2750 .timings = &innolux_g121i1_l01_timing, 2751 .num_timings = 1, 2752 .bpc = 6, 2753 .size = { 2754 .width = 261, 2755 .height = 163, 2756 }, 2757 .delay = { 2758 .enable = 200, 2759 .disable = 20, 2760 }, 2761 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2762 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2763}; 2764 2765static const struct display_timing innolux_g121x1_l03_timings = { 2766 .pixelclock = { 57500000, 64900000, 74400000 }, 2767 .hactive = { 1024, 1024, 1024 }, 2768 .hfront_porch = { 90, 140, 190 }, 2769 .hback_porch = { 90, 140, 190 }, 2770 .hsync_len = { 36, 40, 60 }, 2771 .vactive = { 768, 768, 768 }, 2772 .vfront_porch = { 2, 15, 30 }, 2773 .vback_porch = { 2, 15, 30 }, 2774 .vsync_len = { 2, 8, 20 }, 2775 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2776}; 2777 2778static const struct panel_desc innolux_g121x1_l03 = { 2779 .timings = &innolux_g121x1_l03_timings, 2780 .num_timings = 1, 2781 .bpc = 6, 2782 .size = { 2783 .width = 246, 2784 .height = 185, 2785 }, 2786 .delay = { 2787 .enable = 200, 2788 .unprepare = 200, 2789 .disable = 400, 2790 }, 2791 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2792 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2793 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2794}; 2795 2796static const struct panel_desc innolux_g121xce_l01 = { 2797 .timings = &innolux_g121x1_l03_timings, 2798 .num_timings = 1, 2799 .bpc = 8, 2800 .size = { 2801 .width = 246, 2802 .height = 185, 2803 }, 2804 .delay = { 2805 .enable = 200, 2806 .unprepare = 200, 2807 .disable = 400, 2808 }, 2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2810 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2811 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2812}; 2813 2814static const struct display_timing innolux_g156hce_l01_timings = { 2815 .pixelclock = { 120000000, 141860000, 150000000 }, 2816 .hactive = { 1920, 1920, 1920 }, 2817 .hfront_porch = { 80, 90, 100 }, 2818 .hback_porch = { 80, 90, 100 }, 2819 .hsync_len = { 20, 30, 30 }, 2820 .vactive = { 1080, 1080, 1080 }, 2821 .vfront_porch = { 3, 10, 20 }, 2822 .vback_porch = { 3, 10, 20 }, 2823 .vsync_len = { 4, 10, 10 }, 2824}; 2825 2826static const struct panel_desc innolux_g156hce_l01 = { 2827 .timings = &innolux_g156hce_l01_timings, 2828 .num_timings = 1, 2829 .bpc = 8, 2830 .size = { 2831 .width = 344, 2832 .height = 194, 2833 }, 2834 .delay = { 2835 .prepare = 1, /* T1+T2 */ 2836 .enable = 450, /* T5 */ 2837 .disable = 200, /* T6 */ 2838 .unprepare = 10, /* T3+T7 */ 2839 }, 2840 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2841 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2842 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2843}; 2844 2845static const struct drm_display_mode innolux_n156bge_l21_mode = { 2846 .clock = 69300, 2847 .hdisplay = 1366, 2848 .hsync_start = 1366 + 16, 2849 .hsync_end = 1366 + 16 + 34, 2850 .htotal = 1366 + 16 + 34 + 50, 2851 .vdisplay = 768, 2852 .vsync_start = 768 + 2, 2853 .vsync_end = 768 + 2 + 6, 2854 .vtotal = 768 + 2 + 6 + 12, 2855}; 2856 2857static const struct panel_desc innolux_n156bge_l21 = { 2858 .modes = &innolux_n156bge_l21_mode, 2859 .num_modes = 1, 2860 .bpc = 6, 2861 .size = { 2862 .width = 344, 2863 .height = 193, 2864 }, 2865 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2866 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2868}; 2869 2870static const struct drm_display_mode innolux_zj070na_01p_mode = { 2871 .clock = 51501, 2872 .hdisplay = 1024, 2873 .hsync_start = 1024 + 128, 2874 .hsync_end = 1024 + 128 + 64, 2875 .htotal = 1024 + 128 + 64 + 128, 2876 .vdisplay = 600, 2877 .vsync_start = 600 + 16, 2878 .vsync_end = 600 + 16 + 4, 2879 .vtotal = 600 + 16 + 4 + 16, 2880}; 2881 2882static const struct panel_desc innolux_zj070na_01p = { 2883 .modes = &innolux_zj070na_01p_mode, 2884 .num_modes = 1, 2885 .bpc = 6, 2886 .size = { 2887 .width = 154, 2888 .height = 90, 2889 }, 2890}; 2891 2892static const struct display_timing jutouch_jt101tm023_timing = { 2893 .pixelclock = { 66300000, 72400000, 78900000 }, 2894 .hactive = { 1280, 1280, 1280 }, 2895 .hfront_porch = { 12, 72, 132 }, 2896 .hback_porch = { 88, 88, 88 }, 2897 .hsync_len = { 10, 10, 48 }, 2898 .vactive = { 800, 800, 800 }, 2899 .vfront_porch = { 1, 15, 49 }, 2900 .vback_porch = { 23, 23, 23 }, 2901 .vsync_len = { 5, 6, 13 }, 2902 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2903 DISPLAY_FLAGS_DE_HIGH, 2904}; 2905 2906static const struct panel_desc jutouch_jt101tm023 = { 2907 .timings = &jutouch_jt101tm023_timing, 2908 .num_timings = 1, 2909 .bpc = 8, 2910 .size = { 2911 .width = 217, 2912 .height = 136, 2913 }, 2914 .delay = { 2915 .enable = 50, 2916 .disable = 50, 2917 }, 2918 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2919 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2920 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2921}; 2922 2923 2924static const struct display_timing koe_tx14d24vm1bpa_timing = { 2925 .pixelclock = { 5580000, 5850000, 6200000 }, 2926 .hactive = { 320, 320, 320 }, 2927 .hfront_porch = { 30, 30, 30 }, 2928 .hback_porch = { 30, 30, 30 }, 2929 .hsync_len = { 1, 5, 17 }, 2930 .vactive = { 240, 240, 240 }, 2931 .vfront_porch = { 6, 6, 6 }, 2932 .vback_porch = { 5, 5, 5 }, 2933 .vsync_len = { 1, 2, 11 }, 2934 .flags = DISPLAY_FLAGS_DE_HIGH, 2935}; 2936 2937static const struct panel_desc koe_tx14d24vm1bpa = { 2938 .timings = &koe_tx14d24vm1bpa_timing, 2939 .num_timings = 1, 2940 .bpc = 6, 2941 .size = { 2942 .width = 115, 2943 .height = 86, 2944 }, 2945}; 2946 2947static const struct display_timing koe_tx26d202vm0bwa_timing = { 2948 .pixelclock = { 151820000, 156720000, 159780000 }, 2949 .hactive = { 1920, 1920, 1920 }, 2950 .hfront_porch = { 105, 130, 142 }, 2951 .hback_porch = { 45, 70, 82 }, 2952 .hsync_len = { 30, 30, 30 }, 2953 .vactive = { 1200, 1200, 1200}, 2954 .vfront_porch = { 3, 5, 10 }, 2955 .vback_porch = { 2, 5, 10 }, 2956 .vsync_len = { 5, 5, 5 }, 2957 .flags = DISPLAY_FLAGS_DE_HIGH, 2958}; 2959 2960static const struct panel_desc koe_tx26d202vm0bwa = { 2961 .timings = &koe_tx26d202vm0bwa_timing, 2962 .num_timings = 1, 2963 .bpc = 8, 2964 .size = { 2965 .width = 217, 2966 .height = 136, 2967 }, 2968 .delay = { 2969 .prepare = 1000, 2970 .enable = 1000, 2971 .unprepare = 1000, 2972 .disable = 1000, 2973 }, 2974 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2975 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2976 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2977}; 2978 2979static const struct display_timing koe_tx31d200vm0baa_timing = { 2980 .pixelclock = { 39600000, 43200000, 48000000 }, 2981 .hactive = { 1280, 1280, 1280 }, 2982 .hfront_porch = { 16, 36, 56 }, 2983 .hback_porch = { 16, 36, 56 }, 2984 .hsync_len = { 8, 8, 8 }, 2985 .vactive = { 480, 480, 480 }, 2986 .vfront_porch = { 6, 21, 33 }, 2987 .vback_porch = { 6, 21, 33 }, 2988 .vsync_len = { 8, 8, 8 }, 2989 .flags = DISPLAY_FLAGS_DE_HIGH, 2990}; 2991 2992static const struct panel_desc koe_tx31d200vm0baa = { 2993 .timings = &koe_tx31d200vm0baa_timing, 2994 .num_timings = 1, 2995 .bpc = 6, 2996 .size = { 2997 .width = 292, 2998 .height = 109, 2999 }, 3000 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3001 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3002}; 3003 3004static const struct display_timing kyo_tcg121xglp_timing = { 3005 .pixelclock = { 52000000, 65000000, 71000000 }, 3006 .hactive = { 1024, 1024, 1024 }, 3007 .hfront_porch = { 2, 2, 2 }, 3008 .hback_porch = { 2, 2, 2 }, 3009 .hsync_len = { 86, 124, 244 }, 3010 .vactive = { 768, 768, 768 }, 3011 .vfront_porch = { 2, 2, 2 }, 3012 .vback_porch = { 2, 2, 2 }, 3013 .vsync_len = { 6, 34, 73 }, 3014 .flags = DISPLAY_FLAGS_DE_HIGH, 3015}; 3016 3017static const struct panel_desc kyo_tcg121xglp = { 3018 .timings = &kyo_tcg121xglp_timing, 3019 .num_timings = 1, 3020 .bpc = 8, 3021 .size = { 3022 .width = 246, 3023 .height = 184, 3024 }, 3025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3027}; 3028 3029static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3030 .clock = 7000, 3031 .hdisplay = 320, 3032 .hsync_start = 320 + 20, 3033 .hsync_end = 320 + 20 + 30, 3034 .htotal = 320 + 20 + 30 + 38, 3035 .vdisplay = 240, 3036 .vsync_start = 240 + 4, 3037 .vsync_end = 240 + 4 + 3, 3038 .vtotal = 240 + 4 + 3 + 15, 3039}; 3040 3041static const struct panel_desc lemaker_bl035_rgb_002 = { 3042 .modes = &lemaker_bl035_rgb_002_mode, 3043 .num_modes = 1, 3044 .size = { 3045 .width = 70, 3046 .height = 52, 3047 }, 3048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3049 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3050}; 3051 3052static const struct display_timing lg_lb070wv8_timing = { 3053 .pixelclock = { 31950000, 33260000, 34600000 }, 3054 .hactive = { 800, 800, 800 }, 3055 .hfront_porch = { 88, 88, 88 }, 3056 .hback_porch = { 88, 88, 88 }, 3057 .hsync_len = { 80, 80, 80 }, 3058 .vactive = { 480, 480, 480 }, 3059 .vfront_porch = { 10, 10, 10 }, 3060 .vback_porch = { 10, 10, 10 }, 3061 .vsync_len = { 25, 25, 25 }, 3062}; 3063 3064static const struct panel_desc lg_lb070wv8 = { 3065 .timings = &lg_lb070wv8_timing, 3066 .num_timings = 1, 3067 .bpc = 8, 3068 .size = { 3069 .width = 151, 3070 .height = 91, 3071 }, 3072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3073 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3074}; 3075 3076static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3077 .clock = 155127, 3078 .hdisplay = 1920, 3079 .hsync_start = 1920 + 128, 3080 .hsync_end = 1920 + 128 + 20, 3081 .htotal = 1920 + 128 + 20 + 12, 3082 .vdisplay = 1200, 3083 .vsync_start = 1200 + 19, 3084 .vsync_end = 1200 + 19 + 4, 3085 .vtotal = 1200 + 19 + 4 + 20, 3086}; 3087 3088static const struct panel_desc lincolntech_lcd185_101ct = { 3089 .modes = &lincolntech_lcd185_101ct_mode, 3090 .bpc = 8, 3091 .num_modes = 1, 3092 .size = { 3093 .width = 217, 3094 .height = 136, 3095 }, 3096 .delay = { 3097 .prepare = 50, 3098 .disable = 50, 3099 }, 3100 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3101 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3102 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3103}; 3104 3105static const struct display_timing logictechno_lt161010_2nh_timing = { 3106 .pixelclock = { 26400000, 33300000, 46800000 }, 3107 .hactive = { 800, 800, 800 }, 3108 .hfront_porch = { 16, 210, 354 }, 3109 .hback_porch = { 46, 46, 46 }, 3110 .hsync_len = { 1, 20, 40 }, 3111 .vactive = { 480, 480, 480 }, 3112 .vfront_porch = { 7, 22, 147 }, 3113 .vback_porch = { 23, 23, 23 }, 3114 .vsync_len = { 1, 10, 20 }, 3115 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3116 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3117 DISPLAY_FLAGS_SYNC_POSEDGE, 3118}; 3119 3120static const struct panel_desc logictechno_lt161010_2nh = { 3121 .timings = &logictechno_lt161010_2nh_timing, 3122 .num_timings = 1, 3123 .bpc = 6, 3124 .size = { 3125 .width = 154, 3126 .height = 86, 3127 }, 3128 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3129 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3130 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3131 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3132 .connector_type = DRM_MODE_CONNECTOR_DPI, 3133}; 3134 3135static const struct display_timing logictechno_lt170410_2whc_timing = { 3136 .pixelclock = { 68900000, 71100000, 73400000 }, 3137 .hactive = { 1280, 1280, 1280 }, 3138 .hfront_porch = { 23, 60, 71 }, 3139 .hback_porch = { 23, 60, 71 }, 3140 .hsync_len = { 15, 40, 47 }, 3141 .vactive = { 800, 800, 800 }, 3142 .vfront_porch = { 5, 7, 10 }, 3143 .vback_porch = { 5, 7, 10 }, 3144 .vsync_len = { 6, 9, 12 }, 3145 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3146 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3147 DISPLAY_FLAGS_SYNC_POSEDGE, 3148}; 3149 3150static const struct panel_desc logictechno_lt170410_2whc = { 3151 .timings = &logictechno_lt170410_2whc_timing, 3152 .num_timings = 1, 3153 .bpc = 8, 3154 .size = { 3155 .width = 217, 3156 .height = 136, 3157 }, 3158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3159 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3161}; 3162 3163static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3164 .clock = 33000, 3165 .hdisplay = 800, 3166 .hsync_start = 800 + 112, 3167 .hsync_end = 800 + 112 + 3, 3168 .htotal = 800 + 112 + 3 + 85, 3169 .vdisplay = 480, 3170 .vsync_start = 480 + 38, 3171 .vsync_end = 480 + 38 + 3, 3172 .vtotal = 480 + 38 + 3 + 29, 3173 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3174}; 3175 3176static const struct panel_desc logictechno_lttd800480070_l2rt = { 3177 .modes = &logictechno_lttd800480070_l2rt_mode, 3178 .num_modes = 1, 3179 .bpc = 8, 3180 .size = { 3181 .width = 154, 3182 .height = 86, 3183 }, 3184 .delay = { 3185 .prepare = 45, 3186 .enable = 100, 3187 .disable = 100, 3188 .unprepare = 45 3189 }, 3190 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3191 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3192 .connector_type = DRM_MODE_CONNECTOR_DPI, 3193}; 3194 3195static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3196 .clock = 33000, 3197 .hdisplay = 800, 3198 .hsync_start = 800 + 154, 3199 .hsync_end = 800 + 154 + 3, 3200 .htotal = 800 + 154 + 3 + 43, 3201 .vdisplay = 480, 3202 .vsync_start = 480 + 47, 3203 .vsync_end = 480 + 47 + 3, 3204 .vtotal = 480 + 47 + 3 + 20, 3205 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3206}; 3207 3208static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3209 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3210 .num_modes = 1, 3211 .bpc = 8, 3212 .size = { 3213 .width = 154, 3214 .height = 86, 3215 }, 3216 .delay = { 3217 .prepare = 45, 3218 .enable = 100, 3219 .disable = 100, 3220 .unprepare = 45 3221 }, 3222 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3223 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3224 .connector_type = DRM_MODE_CONNECTOR_DPI, 3225}; 3226 3227static const struct drm_display_mode logicpd_type_28_mode = { 3228 .clock = 9107, 3229 .hdisplay = 480, 3230 .hsync_start = 480 + 3, 3231 .hsync_end = 480 + 3 + 42, 3232 .htotal = 480 + 3 + 42 + 2, 3233 3234 .vdisplay = 272, 3235 .vsync_start = 272 + 2, 3236 .vsync_end = 272 + 2 + 11, 3237 .vtotal = 272 + 2 + 11 + 3, 3238 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3239}; 3240 3241static const struct panel_desc logicpd_type_28 = { 3242 .modes = &logicpd_type_28_mode, 3243 .num_modes = 1, 3244 .bpc = 8, 3245 .size = { 3246 .width = 105, 3247 .height = 67, 3248 }, 3249 .delay = { 3250 .prepare = 200, 3251 .enable = 200, 3252 .unprepare = 200, 3253 .disable = 200, 3254 }, 3255 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3256 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3257 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3258 .connector_type = DRM_MODE_CONNECTOR_DPI, 3259}; 3260 3261static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3262 .clock = 150275, 3263 .hdisplay = 1920, 3264 .hsync_start = 1920 + 32, 3265 .hsync_end = 1920 + 32 + 52, 3266 .htotal = 1920 + 32 + 52 + 24, 3267 .vdisplay = 1200, 3268 .vsync_start = 1200 + 24, 3269 .vsync_end = 1200 + 24 + 8, 3270 .vtotal = 1200 + 24 + 8 + 3, 3271}; 3272 3273static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3274 .modes = µtips_mf_101hiebcaf0_c_mode, 3275 .bpc = 8, 3276 .num_modes = 1, 3277 .size = { 3278 .width = 217, 3279 .height = 136, 3280 }, 3281 .delay = { 3282 .prepare = 50, 3283 .disable = 50, 3284 }, 3285 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3286 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3287 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3288}; 3289 3290static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3291 .clock = 93301, 3292 .hdisplay = 1920, 3293 .hsync_start = 1920 + 72, 3294 .hsync_end = 1920 + 72 + 72, 3295 .htotal = 1920 + 72 + 72 + 72, 3296 .vdisplay = 720, 3297 .vsync_start = 720 + 3, 3298 .vsync_end = 720 + 3 + 3, 3299 .vtotal = 720 + 3 + 3 + 2, 3300}; 3301 3302static const struct panel_desc microtips_mf_103hieb0ga0 = { 3303 .modes = µtips_mf_103hieb0ga0_mode, 3304 .bpc = 8, 3305 .num_modes = 1, 3306 .size = { 3307 .width = 244, 3308 .height = 92, 3309 }, 3310 .delay = { 3311 .prepare = 50, 3312 .disable = 50, 3313 }, 3314 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3315 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3316 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3317}; 3318 3319static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3320 .clock = 30400, 3321 .hdisplay = 800, 3322 .hsync_start = 800 + 0, 3323 .hsync_end = 800 + 1, 3324 .htotal = 800 + 0 + 1 + 160, 3325 .vdisplay = 480, 3326 .vsync_start = 480 + 0, 3327 .vsync_end = 480 + 48 + 1, 3328 .vtotal = 480 + 48 + 1 + 0, 3329 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3330}; 3331 3332static const struct panel_desc mitsubishi_aa070mc01 = { 3333 .modes = &mitsubishi_aa070mc01_mode, 3334 .num_modes = 1, 3335 .bpc = 8, 3336 .size = { 3337 .width = 152, 3338 .height = 91, 3339 }, 3340 3341 .delay = { 3342 .enable = 200, 3343 .unprepare = 200, 3344 .disable = 400, 3345 }, 3346 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3347 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3348 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3349}; 3350 3351static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3352 .clock = 56234, 3353 .hdisplay = 1024, 3354 .hsync_start = 1024 + 24, 3355 .hsync_end = 1024 + 24 + 63, 3356 .htotal = 1024 + 24 + 63 + 1, 3357 .vdisplay = 768, 3358 .vsync_start = 768 + 3, 3359 .vsync_end = 768 + 3 + 6, 3360 .vtotal = 768 + 3 + 6 + 1, 3361 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3362}; 3363 3364static const struct panel_desc mitsubishi_aa084xe01 = { 3365 .modes = &mitsubishi_aa084xe01_mode, 3366 .num_modes = 1, 3367 .bpc = 8, 3368 .size = { 3369 .width = 1024, 3370 .height = 768, 3371 }, 3372 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3373 .connector_type = DRM_MODE_CONNECTOR_DPI, 3374 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3375}; 3376 3377static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3378 .pixelclock = { 26400000, 33000000, 46800000 }, 3379 .hactive = { 800, 800, 800 }, 3380 .hfront_porch = { 16, 204, 354 }, 3381 .hback_porch = { 46, 46, 46 }, 3382 .hsync_len = { 1, 6, 40 }, 3383 .vactive = { 480, 480, 480 }, 3384 .vfront_porch = { 7, 22, 147 }, 3385 .vback_porch = { 23, 23, 23 }, 3386 .vsync_len = { 1, 3, 20 }, 3387 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3388 DISPLAY_FLAGS_DE_HIGH, 3389}; 3390 3391static const struct panel_desc multi_inno_mi0700a2t_30 = { 3392 .timings = &multi_inno_mi0700a2t_30_timing, 3393 .num_timings = 1, 3394 .bpc = 6, 3395 .size = { 3396 .width = 153, 3397 .height = 92, 3398 }, 3399 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3400 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3402}; 3403 3404static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3405 .pixelclock = { 29000000, 33000000, 38000000 }, 3406 .hactive = { 800, 800, 800 }, 3407 .hfront_porch = { 180, 210, 240 }, 3408 .hback_porch = { 16, 16, 16 }, 3409 .hsync_len = { 30, 30, 30 }, 3410 .vactive = { 480, 480, 480 }, 3411 .vfront_porch = { 12, 22, 32 }, 3412 .vback_porch = { 10, 10, 10 }, 3413 .vsync_len = { 13, 13, 13 }, 3414 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3415 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3416 DISPLAY_FLAGS_SYNC_POSEDGE, 3417}; 3418 3419static const struct panel_desc multi_inno_mi0700s4t_6 = { 3420 .timings = &multi_inno_mi0700s4t_6_timing, 3421 .num_timings = 1, 3422 .bpc = 8, 3423 .size = { 3424 .width = 154, 3425 .height = 86, 3426 }, 3427 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3428 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3429 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3430 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3431 .connector_type = DRM_MODE_CONNECTOR_DPI, 3432}; 3433 3434static const struct display_timing multi_inno_mi0800ft_9_timing = { 3435 .pixelclock = { 32000000, 40000000, 50000000 }, 3436 .hactive = { 800, 800, 800 }, 3437 .hfront_porch = { 16, 210, 354 }, 3438 .hback_porch = { 6, 26, 45 }, 3439 .hsync_len = { 1, 20, 40 }, 3440 .vactive = { 600, 600, 600 }, 3441 .vfront_porch = { 1, 12, 77 }, 3442 .vback_porch = { 3, 13, 22 }, 3443 .vsync_len = { 1, 10, 20 }, 3444 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3445 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3446 DISPLAY_FLAGS_SYNC_POSEDGE, 3447}; 3448 3449static const struct panel_desc multi_inno_mi0800ft_9 = { 3450 .timings = &multi_inno_mi0800ft_9_timing, 3451 .num_timings = 1, 3452 .bpc = 8, 3453 .size = { 3454 .width = 162, 3455 .height = 122, 3456 }, 3457 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3458 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3459 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3460 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3461 .connector_type = DRM_MODE_CONNECTOR_DPI, 3462}; 3463 3464static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3465 .pixelclock = { 68900000, 70000000, 73400000 }, 3466 .hactive = { 1280, 1280, 1280 }, 3467 .hfront_porch = { 30, 60, 71 }, 3468 .hback_porch = { 30, 60, 71 }, 3469 .hsync_len = { 10, 10, 48 }, 3470 .vactive = { 800, 800, 800 }, 3471 .vfront_porch = { 5, 10, 10 }, 3472 .vback_porch = { 5, 10, 10 }, 3473 .vsync_len = { 5, 6, 13 }, 3474 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3475 DISPLAY_FLAGS_DE_HIGH, 3476}; 3477 3478static const struct panel_desc multi_inno_mi1010ait_1cp = { 3479 .timings = &multi_inno_mi1010ait_1cp_timing, 3480 .num_timings = 1, 3481 .bpc = 8, 3482 .size = { 3483 .width = 217, 3484 .height = 136, 3485 }, 3486 .delay = { 3487 .enable = 50, 3488 .disable = 50, 3489 }, 3490 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3491 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3493}; 3494 3495static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3496 .pixelclock = { 40800000, 51200000, 67200000 }, 3497 .hactive = { 1024, 1024, 1024 }, 3498 .hfront_porch = { 30, 110, 130 }, 3499 .hback_porch = { 30, 110, 130 }, 3500 .hsync_len = { 30, 100, 116 }, 3501 .vactive = { 600, 600, 600 }, 3502 .vfront_porch = { 4, 13, 80 }, 3503 .vback_porch = { 4, 13, 80 }, 3504 .vsync_len = { 2, 9, 40 }, 3505 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3506 DISPLAY_FLAGS_DE_HIGH, 3507}; 3508 3509static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3510 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3511 .num_timings = 1, 3512 .bpc = 6, 3513 .size = { 3514 .width = 260, 3515 .height = 162, 3516 }, 3517 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3518 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3519 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3520}; 3521 3522static const struct display_timing nec_nl12880bc20_05_timing = { 3523 .pixelclock = { 67000000, 71000000, 75000000 }, 3524 .hactive = { 1280, 1280, 1280 }, 3525 .hfront_porch = { 2, 30, 30 }, 3526 .hback_porch = { 6, 100, 100 }, 3527 .hsync_len = { 2, 30, 30 }, 3528 .vactive = { 800, 800, 800 }, 3529 .vfront_porch = { 5, 5, 5 }, 3530 .vback_porch = { 11, 11, 11 }, 3531 .vsync_len = { 7, 7, 7 }, 3532}; 3533 3534static const struct panel_desc nec_nl12880bc20_05 = { 3535 .timings = &nec_nl12880bc20_05_timing, 3536 .num_timings = 1, 3537 .bpc = 8, 3538 .size = { 3539 .width = 261, 3540 .height = 163, 3541 }, 3542 .delay = { 3543 .enable = 50, 3544 .disable = 50, 3545 }, 3546 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3547 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3548}; 3549 3550static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3551 .clock = 10870, 3552 .hdisplay = 480, 3553 .hsync_start = 480 + 2, 3554 .hsync_end = 480 + 2 + 41, 3555 .htotal = 480 + 2 + 41 + 2, 3556 .vdisplay = 272, 3557 .vsync_start = 272 + 2, 3558 .vsync_end = 272 + 2 + 4, 3559 .vtotal = 272 + 2 + 4 + 2, 3560 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3561}; 3562 3563static const struct panel_desc nec_nl4827hc19_05b = { 3564 .modes = &nec_nl4827hc19_05b_mode, 3565 .num_modes = 1, 3566 .bpc = 8, 3567 .size = { 3568 .width = 95, 3569 .height = 54, 3570 }, 3571 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3572 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3573}; 3574 3575static const struct drm_display_mode netron_dy_e231732_mode = { 3576 .clock = 66000, 3577 .hdisplay = 1024, 3578 .hsync_start = 1024 + 160, 3579 .hsync_end = 1024 + 160 + 70, 3580 .htotal = 1024 + 160 + 70 + 90, 3581 .vdisplay = 600, 3582 .vsync_start = 600 + 127, 3583 .vsync_end = 600 + 127 + 20, 3584 .vtotal = 600 + 127 + 20 + 3, 3585}; 3586 3587static const struct panel_desc netron_dy_e231732 = { 3588 .modes = &netron_dy_e231732_mode, 3589 .num_modes = 1, 3590 .size = { 3591 .width = 154, 3592 .height = 87, 3593 }, 3594 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3595}; 3596 3597static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3598 .clock = 9000, 3599 .hdisplay = 480, 3600 .hsync_start = 480 + 2, 3601 .hsync_end = 480 + 2 + 41, 3602 .htotal = 480 + 2 + 41 + 2, 3603 .vdisplay = 272, 3604 .vsync_start = 272 + 2, 3605 .vsync_end = 272 + 2 + 10, 3606 .vtotal = 272 + 2 + 10 + 2, 3607 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3608}; 3609 3610static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3611 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3612 .num_modes = 1, 3613 .bpc = 8, 3614 .size = { 3615 .width = 95, 3616 .height = 54, 3617 }, 3618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3620 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3621 .connector_type = DRM_MODE_CONNECTOR_DPI, 3622}; 3623 3624static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3625 .clock = 75400, 3626 .hdisplay = 1366, 3627 .hsync_start = 1366 + 14, 3628 .hsync_end = 1366 + 14 + 56, 3629 .htotal = 1366 + 14 + 56 + 64, 3630 .vdisplay = 768, 3631 .vsync_start = 768 + 1, 3632 .vsync_end = 768 + 1 + 3, 3633 .vtotal = 768 + 1 + 3 + 22, 3634}; 3635 3636static const struct panel_desc nlt_nl13676bc25_03f = { 3637 .modes = &nlt_nl13676bc25_03f_mode, 3638 .num_modes = 1, 3639 .bpc = 8, 3640 .size = { 3641 .width = 363, 3642 .height = 215, 3643 }, 3644 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3645 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3646}; 3647 3648static const struct display_timing nlt_nl192108ac18_02d_timing = { 3649 .pixelclock = { 130000000, 148350000, 163000000 }, 3650 .hactive = { 1920, 1920, 1920 }, 3651 .hfront_porch = { 80, 100, 100 }, 3652 .hback_porch = { 100, 120, 120 }, 3653 .hsync_len = { 50, 60, 60 }, 3654 .vactive = { 1080, 1080, 1080 }, 3655 .vfront_porch = { 12, 30, 30 }, 3656 .vback_porch = { 4, 10, 10 }, 3657 .vsync_len = { 4, 5, 5 }, 3658}; 3659 3660static const struct panel_desc nlt_nl192108ac18_02d = { 3661 .timings = &nlt_nl192108ac18_02d_timing, 3662 .num_timings = 1, 3663 .bpc = 8, 3664 .size = { 3665 .width = 344, 3666 .height = 194, 3667 }, 3668 .delay = { 3669 .unprepare = 500, 3670 }, 3671 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3672 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3673}; 3674 3675static const struct drm_display_mode nvd_9128_mode = { 3676 .clock = 29500, 3677 .hdisplay = 800, 3678 .hsync_start = 800 + 130, 3679 .hsync_end = 800 + 130 + 98, 3680 .htotal = 800 + 0 + 130 + 98, 3681 .vdisplay = 480, 3682 .vsync_start = 480 + 10, 3683 .vsync_end = 480 + 10 + 50, 3684 .vtotal = 480 + 0 + 10 + 50, 3685}; 3686 3687static const struct panel_desc nvd_9128 = { 3688 .modes = &nvd_9128_mode, 3689 .num_modes = 1, 3690 .bpc = 8, 3691 .size = { 3692 .width = 156, 3693 .height = 88, 3694 }, 3695 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3696 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3697}; 3698 3699static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3700 .pixelclock = { 30000000, 30000000, 40000000 }, 3701 .hactive = { 800, 800, 800 }, 3702 .hfront_porch = { 40, 40, 40 }, 3703 .hback_porch = { 40, 40, 40 }, 3704 .hsync_len = { 1, 48, 48 }, 3705 .vactive = { 480, 480, 480 }, 3706 .vfront_porch = { 13, 13, 13 }, 3707 .vback_porch = { 29, 29, 29 }, 3708 .vsync_len = { 3, 3, 3 }, 3709 .flags = DISPLAY_FLAGS_DE_HIGH, 3710}; 3711 3712static const struct panel_desc okaya_rs800480t_7x0gp = { 3713 .timings = &okaya_rs800480t_7x0gp_timing, 3714 .num_timings = 1, 3715 .bpc = 6, 3716 .size = { 3717 .width = 154, 3718 .height = 87, 3719 }, 3720 .delay = { 3721 .prepare = 41, 3722 .enable = 50, 3723 .unprepare = 41, 3724 .disable = 50, 3725 }, 3726 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3727}; 3728 3729static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3730 .clock = 9000, 3731 .hdisplay = 480, 3732 .hsync_start = 480 + 5, 3733 .hsync_end = 480 + 5 + 30, 3734 .htotal = 480 + 5 + 30 + 10, 3735 .vdisplay = 272, 3736 .vsync_start = 272 + 8, 3737 .vsync_end = 272 + 8 + 5, 3738 .vtotal = 272 + 8 + 5 + 3, 3739}; 3740 3741static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3742 .modes = &olimex_lcd_olinuxino_43ts_mode, 3743 .num_modes = 1, 3744 .size = { 3745 .width = 95, 3746 .height = 54, 3747 }, 3748 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3749}; 3750 3751static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3752 .clock = 33300, 3753 .hdisplay = 800, 3754 .hsync_start = 800 + 210, 3755 .hsync_end = 800 + 210 + 20, 3756 .htotal = 800 + 210 + 20 + 26, 3757 .vdisplay = 480, 3758 .vsync_start = 480 + 22, 3759 .vsync_end = 480 + 22 + 10, 3760 .vtotal = 480 + 22 + 10 + 13, 3761}; 3762 3763static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3764 .modes = &olimex_lcd_olinuxino_5cts_mode, 3765 .num_modes = 1, 3766 .size = { 3767 .width = 154, 3768 .height = 86, 3769 }, 3770 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3771}; 3772 3773 3774static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3775 .pixelclock = { 30000000, 30000000, 50000000 }, 3776 .hactive = { 800, 800, 800 }, 3777 .hfront_porch = { 1, 40, 255 }, 3778 .hback_porch = { 1, 40, 87 }, 3779 .hsync_len = { 1, 48, 87 }, 3780 .vactive = { 480, 480, 480 }, 3781 .vfront_porch = { 1, 13, 255 }, 3782 .vback_porch = { 1, 29, 29 }, 3783 .vsync_len = { 3, 3, 31 }, 3784 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3785 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3786}; 3787 3788static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3789 .timings = &ontat_kd50g21_40nt_a1_timing, 3790 .num_timings = 1, 3791 .bpc = 8, 3792 .size = { 3793 .width = 108, 3794 .height = 65, 3795 }, 3796 .delay = { 3797 .prepare = 147, /* 5 VSDs */ 3798 .enable = 147, /* 5 VSDs */ 3799 .disable = 88, /* 3 VSDs */ 3800 .unprepare = 117, /* 4 VSDs */ 3801 }, 3802 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3803 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3804 .connector_type = DRM_MODE_CONNECTOR_DPI, 3805}; 3806 3807/* 3808 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3809 * pixel clocks, but this is the timing that was being used in the Adafruit 3810 * installation instructions. 3811 */ 3812static const struct drm_display_mode ontat_yx700wv03_mode = { 3813 .clock = 29500, 3814 .hdisplay = 800, 3815 .hsync_start = 824, 3816 .hsync_end = 896, 3817 .htotal = 992, 3818 .vdisplay = 480, 3819 .vsync_start = 483, 3820 .vsync_end = 493, 3821 .vtotal = 500, 3822 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3823}; 3824 3825/* 3826 * Specification at: 3827 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3828 */ 3829static const struct panel_desc ontat_yx700wv03 = { 3830 .modes = &ontat_yx700wv03_mode, 3831 .num_modes = 1, 3832 .bpc = 8, 3833 .size = { 3834 .width = 154, 3835 .height = 83, 3836 }, 3837 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3838}; 3839 3840static const struct drm_display_mode ortustech_com37h3m_mode = { 3841 .clock = 22230, 3842 .hdisplay = 480, 3843 .hsync_start = 480 + 40, 3844 .hsync_end = 480 + 40 + 10, 3845 .htotal = 480 + 40 + 10 + 40, 3846 .vdisplay = 640, 3847 .vsync_start = 640 + 4, 3848 .vsync_end = 640 + 4 + 2, 3849 .vtotal = 640 + 4 + 2 + 4, 3850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3851}; 3852 3853static const struct panel_desc ortustech_com37h3m = { 3854 .modes = &ortustech_com37h3m_mode, 3855 .num_modes = 1, 3856 .bpc = 8, 3857 .size = { 3858 .width = 56, /* 56.16mm */ 3859 .height = 75, /* 74.88mm */ 3860 }, 3861 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3862 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3863 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3864}; 3865 3866static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3867 .clock = 25000, 3868 .hdisplay = 480, 3869 .hsync_start = 480 + 10, 3870 .hsync_end = 480 + 10 + 10, 3871 .htotal = 480 + 10 + 10 + 15, 3872 .vdisplay = 800, 3873 .vsync_start = 800 + 3, 3874 .vsync_end = 800 + 3 + 3, 3875 .vtotal = 800 + 3 + 3 + 3, 3876}; 3877 3878static const struct panel_desc ortustech_com43h4m85ulc = { 3879 .modes = &ortustech_com43h4m85ulc_mode, 3880 .num_modes = 1, 3881 .bpc = 6, 3882 .size = { 3883 .width = 56, 3884 .height = 93, 3885 }, 3886 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3887 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3888 .connector_type = DRM_MODE_CONNECTOR_DPI, 3889}; 3890 3891static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3892 .clock = 33000, 3893 .hdisplay = 800, 3894 .hsync_start = 800 + 210, 3895 .hsync_end = 800 + 210 + 30, 3896 .htotal = 800 + 210 + 30 + 16, 3897 .vdisplay = 480, 3898 .vsync_start = 480 + 22, 3899 .vsync_end = 480 + 22 + 13, 3900 .vtotal = 480 + 22 + 13 + 10, 3901 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3902}; 3903 3904static const struct panel_desc osddisplays_osd070t1718_19ts = { 3905 .modes = &osddisplays_osd070t1718_19ts_mode, 3906 .num_modes = 1, 3907 .bpc = 8, 3908 .size = { 3909 .width = 152, 3910 .height = 91, 3911 }, 3912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3914 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3915 .connector_type = DRM_MODE_CONNECTOR_DPI, 3916}; 3917 3918static const struct drm_display_mode pda_91_00156_a0_mode = { 3919 .clock = 33300, 3920 .hdisplay = 800, 3921 .hsync_start = 800 + 1, 3922 .hsync_end = 800 + 1 + 64, 3923 .htotal = 800 + 1 + 64 + 64, 3924 .vdisplay = 480, 3925 .vsync_start = 480 + 1, 3926 .vsync_end = 480 + 1 + 23, 3927 .vtotal = 480 + 1 + 23 + 22, 3928}; 3929 3930static const struct panel_desc pda_91_00156_a0 = { 3931 .modes = &pda_91_00156_a0_mode, 3932 .num_modes = 1, 3933 .size = { 3934 .width = 152, 3935 .height = 91, 3936 }, 3937 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3938}; 3939 3940static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3941 .clock = 71150, 3942 .hdisplay = 1280, 3943 .hsync_start = 1280 + 48, 3944 .hsync_end = 1280 + 48 + 32, 3945 .htotal = 1280 + 48 + 32 + 80, 3946 .vdisplay = 800, 3947 .vsync_start = 800 + 9, 3948 .vsync_end = 800 + 9 + 8, 3949 .vtotal = 800 + 9 + 8 + 6, 3950 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3951}; 3952 3953static const struct panel_desc powertip_ph128800t004_zza01 = { 3954 .modes = &powertip_ph128800t004_zza01_mode, 3955 .num_modes = 1, 3956 .bpc = 8, 3957 .size = { 3958 .width = 216, 3959 .height = 135, 3960 }, 3961 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3962 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3964}; 3965 3966static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3967 .clock = 66500, 3968 .hdisplay = 1280, 3969 .hsync_start = 1280 + 12, 3970 .hsync_end = 1280 + 12 + 20, 3971 .htotal = 1280 + 12 + 20 + 56, 3972 .vdisplay = 800, 3973 .vsync_start = 800 + 1, 3974 .vsync_end = 800 + 1 + 3, 3975 .vtotal = 800 + 1 + 3 + 20, 3976 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3977}; 3978 3979static const struct panel_desc powertip_ph128800t006_zhc01 = { 3980 .modes = &powertip_ph128800t006_zhc01_mode, 3981 .num_modes = 1, 3982 .bpc = 8, 3983 .size = { 3984 .width = 216, 3985 .height = 135, 3986 }, 3987 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3988 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3989 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3990}; 3991 3992static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3993 .clock = 24750, 3994 .hdisplay = 800, 3995 .hsync_start = 800 + 54, 3996 .hsync_end = 800 + 54 + 2, 3997 .htotal = 800 + 54 + 2 + 44, 3998 .vdisplay = 480, 3999 .vsync_start = 480 + 49, 4000 .vsync_end = 480 + 49 + 2, 4001 .vtotal = 480 + 49 + 2 + 22, 4002 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4003}; 4004 4005static const struct panel_desc powertip_ph800480t013_idf02 = { 4006 .modes = &powertip_ph800480t013_idf02_mode, 4007 .num_modes = 1, 4008 .bpc = 8, 4009 .size = { 4010 .width = 152, 4011 .height = 91, 4012 }, 4013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4014 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4015 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4016 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4017 .connector_type = DRM_MODE_CONNECTOR_DPI, 4018}; 4019 4020static const struct drm_display_mode primeview_pm070wl4_mode = { 4021 .clock = 32000, 4022 .hdisplay = 800, 4023 .hsync_start = 800 + 42, 4024 .hsync_end = 800 + 42 + 128, 4025 .htotal = 800 + 42 + 128 + 86, 4026 .vdisplay = 480, 4027 .vsync_start = 480 + 10, 4028 .vsync_end = 480 + 10 + 2, 4029 .vtotal = 480 + 10 + 2 + 33, 4030 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4031}; 4032 4033static const struct panel_desc primeview_pm070wl4 = { 4034 .modes = &primeview_pm070wl4_mode, 4035 .num_modes = 1, 4036 .bpc = 6, 4037 .size = { 4038 .width = 152, 4039 .height = 91, 4040 }, 4041 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4042 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4043 .connector_type = DRM_MODE_CONNECTOR_DPI, 4044}; 4045 4046static const struct drm_display_mode qd43003c0_40_mode = { 4047 .clock = 9000, 4048 .hdisplay = 480, 4049 .hsync_start = 480 + 8, 4050 .hsync_end = 480 + 8 + 4, 4051 .htotal = 480 + 8 + 4 + 39, 4052 .vdisplay = 272, 4053 .vsync_start = 272 + 4, 4054 .vsync_end = 272 + 4 + 10, 4055 .vtotal = 272 + 4 + 10 + 2, 4056}; 4057 4058static const struct panel_desc qd43003c0_40 = { 4059 .modes = &qd43003c0_40_mode, 4060 .num_modes = 1, 4061 .bpc = 8, 4062 .size = { 4063 .width = 95, 4064 .height = 53, 4065 }, 4066 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4067}; 4068 4069static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4070 { /* 60 Hz */ 4071 .clock = 10800, 4072 .hdisplay = 480, 4073 .hsync_start = 480 + 77, 4074 .hsync_end = 480 + 77 + 41, 4075 .htotal = 480 + 77 + 41 + 2, 4076 .vdisplay = 272, 4077 .vsync_start = 272 + 16, 4078 .vsync_end = 272 + 16 + 10, 4079 .vtotal = 272 + 16 + 10 + 2, 4080 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4081 }, 4082 { /* 50 Hz */ 4083 .clock = 10800, 4084 .hdisplay = 480, 4085 .hsync_start = 480 + 17, 4086 .hsync_end = 480 + 17 + 41, 4087 .htotal = 480 + 17 + 41 + 2, 4088 .vdisplay = 272, 4089 .vsync_start = 272 + 116, 4090 .vsync_end = 272 + 116 + 10, 4091 .vtotal = 272 + 116 + 10 + 2, 4092 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4093 }, 4094}; 4095 4096static const struct panel_desc qishenglong_gopher2b_lcd = { 4097 .modes = qishenglong_gopher2b_lcd_modes, 4098 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4099 .bpc = 8, 4100 .size = { 4101 .width = 95, 4102 .height = 54, 4103 }, 4104 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4105 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4106 .connector_type = DRM_MODE_CONNECTOR_DPI, 4107}; 4108 4109static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4110 .pixelclock = { 23000000, 25000000, 27000000 }, 4111 .hactive = { 800, 800, 800 }, 4112 .hback_porch = { 4, 8, 48 }, 4113 .hfront_porch = { 4, 8, 48 }, 4114 .hsync_len = { 2, 4, 8 }, 4115 .vactive = { 480, 480, 480 }, 4116 .vback_porch = { 4, 8, 12 }, 4117 .vfront_porch = { 4, 8, 12 }, 4118 .vsync_len = { 2, 4, 8 }, 4119}; 4120 4121static const struct panel_desc raystar_rff500f_awh_dnn = { 4122 .timings = &raystar_rff500f_awh_dnn_timing, 4123 .num_timings = 1, 4124 .bpc = 8, 4125 .size = { 4126 .width = 108, 4127 .height = 65, 4128 }, 4129 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4130 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4131}; 4132 4133static const struct display_timing rocktech_rk043fn48h_timing = { 4134 .pixelclock = { 6000000, 9000000, 12000000 }, 4135 .hactive = { 480, 480, 480 }, 4136 .hback_porch = { 8, 43, 43 }, 4137 .hfront_porch = { 2, 8, 10 }, 4138 .hsync_len = { 1, 1, 1 }, 4139 .vactive = { 272, 272, 272 }, 4140 .vback_porch = { 2, 12, 26 }, 4141 .vfront_porch = { 1, 4, 4 }, 4142 .vsync_len = { 1, 10, 10 }, 4143 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4144 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4145 DISPLAY_FLAGS_SYNC_POSEDGE, 4146}; 4147 4148static const struct panel_desc rocktech_rk043fn48h = { 4149 .timings = &rocktech_rk043fn48h_timing, 4150 .num_timings = 1, 4151 .bpc = 8, 4152 .size = { 4153 .width = 95, 4154 .height = 54, 4155 }, 4156 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4157 .connector_type = DRM_MODE_CONNECTOR_DPI, 4158}; 4159 4160static const struct display_timing rocktech_rk070er9427_timing = { 4161 .pixelclock = { 26400000, 33300000, 46800000 }, 4162 .hactive = { 800, 800, 800 }, 4163 .hfront_porch = { 16, 210, 354 }, 4164 .hback_porch = { 46, 46, 46 }, 4165 .hsync_len = { 1, 1, 1 }, 4166 .vactive = { 480, 480, 480 }, 4167 .vfront_porch = { 7, 22, 147 }, 4168 .vback_porch = { 23, 23, 23 }, 4169 .vsync_len = { 1, 1, 1 }, 4170 .flags = DISPLAY_FLAGS_DE_HIGH, 4171}; 4172 4173static const struct panel_desc rocktech_rk070er9427 = { 4174 .timings = &rocktech_rk070er9427_timing, 4175 .num_timings = 1, 4176 .bpc = 6, 4177 .size = { 4178 .width = 154, 4179 .height = 86, 4180 }, 4181 .delay = { 4182 .prepare = 41, 4183 .enable = 50, 4184 .unprepare = 41, 4185 .disable = 50, 4186 }, 4187 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4188}; 4189 4190static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4191 .clock = 71100, 4192 .hdisplay = 1280, 4193 .hsync_start = 1280 + 48, 4194 .hsync_end = 1280 + 48 + 32, 4195 .htotal = 1280 + 48 + 32 + 80, 4196 .vdisplay = 800, 4197 .vsync_start = 800 + 2, 4198 .vsync_end = 800 + 2 + 5, 4199 .vtotal = 800 + 2 + 5 + 16, 4200}; 4201 4202static const struct panel_desc rocktech_rk101ii01d_ct = { 4203 .modes = &rocktech_rk101ii01d_ct_mode, 4204 .bpc = 8, 4205 .num_modes = 1, 4206 .size = { 4207 .width = 217, 4208 .height = 136, 4209 }, 4210 .delay = { 4211 .prepare = 50, 4212 .disable = 50, 4213 }, 4214 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4215 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4216 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4217}; 4218 4219static const struct display_timing samsung_ltl101al01_timing = { 4220 .pixelclock = { 66663000, 66663000, 66663000 }, 4221 .hactive = { 1280, 1280, 1280 }, 4222 .hfront_porch = { 18, 18, 18 }, 4223 .hback_porch = { 36, 36, 36 }, 4224 .hsync_len = { 16, 16, 16 }, 4225 .vactive = { 800, 800, 800 }, 4226 .vfront_porch = { 4, 4, 4 }, 4227 .vback_porch = { 16, 16, 16 }, 4228 .vsync_len = { 3, 3, 3 }, 4229 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4230}; 4231 4232static const struct panel_desc samsung_ltl101al01 = { 4233 .timings = &samsung_ltl101al01_timing, 4234 .num_timings = 1, 4235 .bpc = 8, 4236 .size = { 4237 .width = 217, 4238 .height = 135, 4239 }, 4240 .delay = { 4241 .prepare = 40, 4242 .enable = 300, 4243 .disable = 200, 4244 .unprepare = 600, 4245 }, 4246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4248}; 4249 4250static const struct display_timing samsung_ltl106al01_timing = { 4251 .pixelclock = { 71980000, 71980000, 71980000 }, 4252 .hactive = { 1366, 1366, 1366 }, 4253 .hfront_porch = { 56, 56, 56 }, 4254 .hback_porch = { 106, 106, 106 }, 4255 .hsync_len = { 14, 14, 14 }, 4256 .vactive = { 768, 768, 768 }, 4257 .vfront_porch = { 3, 3, 3 }, 4258 .vback_porch = { 6, 6, 6 }, 4259 .vsync_len = { 1, 1, 1 }, 4260 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4261}; 4262 4263static const struct panel_desc samsung_ltl106al01 = { 4264 .timings = &samsung_ltl106al01_timing, 4265 .num_timings = 1, 4266 .bpc = 8, 4267 .size = { 4268 .width = 235, 4269 .height = 132, 4270 }, 4271 .delay = { 4272 .prepare = 5, 4273 .enable = 10, 4274 .disable = 10, 4275 .unprepare = 5, 4276 }, 4277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4279}; 4280 4281static const struct drm_display_mode samsung_ltn101nt05_mode = { 4282 .clock = 54030, 4283 .hdisplay = 1024, 4284 .hsync_start = 1024 + 24, 4285 .hsync_end = 1024 + 24 + 136, 4286 .htotal = 1024 + 24 + 136 + 160, 4287 .vdisplay = 600, 4288 .vsync_start = 600 + 3, 4289 .vsync_end = 600 + 3 + 6, 4290 .vtotal = 600 + 3 + 6 + 61, 4291}; 4292 4293static const struct panel_desc samsung_ltn101nt05 = { 4294 .modes = &samsung_ltn101nt05_mode, 4295 .num_modes = 1, 4296 .bpc = 6, 4297 .size = { 4298 .width = 223, 4299 .height = 125, 4300 }, 4301 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4302 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4303 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4304}; 4305 4306static const struct display_timing satoz_sat050at40h12r2_timing = { 4307 .pixelclock = {33300000, 33300000, 50000000}, 4308 .hactive = {800, 800, 800}, 4309 .hfront_porch = {16, 210, 354}, 4310 .hback_porch = {46, 46, 46}, 4311 .hsync_len = {1, 1, 40}, 4312 .vactive = {480, 480, 480}, 4313 .vfront_porch = {7, 22, 147}, 4314 .vback_porch = {23, 23, 23}, 4315 .vsync_len = {1, 1, 20}, 4316}; 4317 4318static const struct panel_desc satoz_sat050at40h12r2 = { 4319 .timings = &satoz_sat050at40h12r2_timing, 4320 .num_timings = 1, 4321 .bpc = 8, 4322 .size = { 4323 .width = 108, 4324 .height = 65, 4325 }, 4326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4327 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4328}; 4329 4330static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4331 .clock = 33260, 4332 .hdisplay = 800, 4333 .hsync_start = 800 + 64, 4334 .hsync_end = 800 + 64 + 128, 4335 .htotal = 800 + 64 + 128 + 64, 4336 .vdisplay = 480, 4337 .vsync_start = 480 + 8, 4338 .vsync_end = 480 + 8 + 2, 4339 .vtotal = 480 + 8 + 2 + 35, 4340 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4341}; 4342 4343static const struct panel_desc sharp_lq070y3dg3b = { 4344 .modes = &sharp_lq070y3dg3b_mode, 4345 .num_modes = 1, 4346 .bpc = 8, 4347 .size = { 4348 .width = 152, /* 152.4mm */ 4349 .height = 91, /* 91.4mm */ 4350 }, 4351 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4352 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4353 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4354}; 4355 4356static const struct drm_display_mode sharp_lq035q7db03_mode = { 4357 .clock = 5500, 4358 .hdisplay = 240, 4359 .hsync_start = 240 + 16, 4360 .hsync_end = 240 + 16 + 7, 4361 .htotal = 240 + 16 + 7 + 5, 4362 .vdisplay = 320, 4363 .vsync_start = 320 + 9, 4364 .vsync_end = 320 + 9 + 1, 4365 .vtotal = 320 + 9 + 1 + 7, 4366}; 4367 4368static const struct panel_desc sharp_lq035q7db03 = { 4369 .modes = &sharp_lq035q7db03_mode, 4370 .num_modes = 1, 4371 .bpc = 6, 4372 .size = { 4373 .width = 54, 4374 .height = 72, 4375 }, 4376 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4377}; 4378 4379static const struct display_timing sharp_lq101k1ly04_timing = { 4380 .pixelclock = { 60000000, 65000000, 80000000 }, 4381 .hactive = { 1280, 1280, 1280 }, 4382 .hfront_porch = { 20, 20, 20 }, 4383 .hback_porch = { 20, 20, 20 }, 4384 .hsync_len = { 10, 10, 10 }, 4385 .vactive = { 800, 800, 800 }, 4386 .vfront_porch = { 4, 4, 4 }, 4387 .vback_porch = { 4, 4, 4 }, 4388 .vsync_len = { 4, 4, 4 }, 4389 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4390}; 4391 4392static const struct panel_desc sharp_lq101k1ly04 = { 4393 .timings = &sharp_lq101k1ly04_timing, 4394 .num_timings = 1, 4395 .bpc = 8, 4396 .size = { 4397 .width = 217, 4398 .height = 136, 4399 }, 4400 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4402}; 4403 4404static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4405 { /* 50 Hz */ 4406 .clock = 3000, 4407 .hdisplay = 240, 4408 .hsync_start = 240 + 58, 4409 .hsync_end = 240 + 58 + 1, 4410 .htotal = 240 + 58 + 1 + 1, 4411 .vdisplay = 160, 4412 .vsync_start = 160 + 24, 4413 .vsync_end = 160 + 24 + 10, 4414 .vtotal = 160 + 24 + 10 + 6, 4415 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4416 }, 4417 { /* 60 Hz */ 4418 .clock = 3000, 4419 .hdisplay = 240, 4420 .hsync_start = 240 + 8, 4421 .hsync_end = 240 + 8 + 1, 4422 .htotal = 240 + 8 + 1 + 1, 4423 .vdisplay = 160, 4424 .vsync_start = 160 + 24, 4425 .vsync_end = 160 + 24 + 10, 4426 .vtotal = 160 + 24 + 10 + 6, 4427 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4428 }, 4429}; 4430 4431static const struct panel_desc sharp_ls020b1dd01d = { 4432 .modes = sharp_ls020b1dd01d_modes, 4433 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4434 .bpc = 6, 4435 .size = { 4436 .width = 42, 4437 .height = 28, 4438 }, 4439 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4440 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4441 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4442 | DRM_BUS_FLAG_SHARP_SIGNALS, 4443}; 4444 4445static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4446 .clock = 33300, 4447 .hdisplay = 800, 4448 .hsync_start = 800 + 1, 4449 .hsync_end = 800 + 1 + 64, 4450 .htotal = 800 + 1 + 64 + 64, 4451 .vdisplay = 480, 4452 .vsync_start = 480 + 1, 4453 .vsync_end = 480 + 1 + 23, 4454 .vtotal = 480 + 1 + 23 + 22, 4455}; 4456 4457static const struct panel_desc shelly_sca07010_bfn_lnn = { 4458 .modes = &shelly_sca07010_bfn_lnn_mode, 4459 .num_modes = 1, 4460 .size = { 4461 .width = 152, 4462 .height = 91, 4463 }, 4464 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4465}; 4466 4467static const struct drm_display_mode starry_kr070pe2t_mode = { 4468 .clock = 33000, 4469 .hdisplay = 800, 4470 .hsync_start = 800 + 209, 4471 .hsync_end = 800 + 209 + 1, 4472 .htotal = 800 + 209 + 1 + 45, 4473 .vdisplay = 480, 4474 .vsync_start = 480 + 22, 4475 .vsync_end = 480 + 22 + 1, 4476 .vtotal = 480 + 22 + 1 + 22, 4477}; 4478 4479static const struct panel_desc starry_kr070pe2t = { 4480 .modes = &starry_kr070pe2t_mode, 4481 .num_modes = 1, 4482 .bpc = 8, 4483 .size = { 4484 .width = 152, 4485 .height = 86, 4486 }, 4487 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4488 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4489 .connector_type = DRM_MODE_CONNECTOR_DPI, 4490}; 4491 4492static const struct display_timing startek_kd070wvfpa_mode = { 4493 .pixelclock = { 25200000, 27200000, 30500000 }, 4494 .hactive = { 800, 800, 800 }, 4495 .hfront_porch = { 19, 44, 115 }, 4496 .hback_porch = { 5, 16, 101 }, 4497 .hsync_len = { 1, 2, 100 }, 4498 .vactive = { 480, 480, 480 }, 4499 .vfront_porch = { 5, 43, 67 }, 4500 .vback_porch = { 5, 5, 67 }, 4501 .vsync_len = { 1, 2, 66 }, 4502 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4503 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4504 DISPLAY_FLAGS_SYNC_POSEDGE, 4505}; 4506 4507static const struct panel_desc startek_kd070wvfpa = { 4508 .timings = &startek_kd070wvfpa_mode, 4509 .num_timings = 1, 4510 .bpc = 8, 4511 .size = { 4512 .width = 152, 4513 .height = 91, 4514 }, 4515 .delay = { 4516 .prepare = 20, 4517 .enable = 200, 4518 .disable = 200, 4519 }, 4520 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4521 .connector_type = DRM_MODE_CONNECTOR_DPI, 4522 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4523 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4524 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4525}; 4526 4527static const struct display_timing tsd_tst043015cmhx_timing = { 4528 .pixelclock = { 5000000, 9000000, 12000000 }, 4529 .hactive = { 480, 480, 480 }, 4530 .hfront_porch = { 4, 5, 65 }, 4531 .hback_porch = { 36, 40, 255 }, 4532 .hsync_len = { 1, 1, 1 }, 4533 .vactive = { 272, 272, 272 }, 4534 .vfront_porch = { 2, 8, 97 }, 4535 .vback_porch = { 3, 8, 31 }, 4536 .vsync_len = { 1, 1, 1 }, 4537 4538 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4539 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4540}; 4541 4542static const struct panel_desc tsd_tst043015cmhx = { 4543 .timings = &tsd_tst043015cmhx_timing, 4544 .num_timings = 1, 4545 .bpc = 8, 4546 .size = { 4547 .width = 105, 4548 .height = 67, 4549 }, 4550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4551 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4552}; 4553 4554static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4555 .clock = 30000, 4556 .hdisplay = 800, 4557 .hsync_start = 800 + 39, 4558 .hsync_end = 800 + 39 + 47, 4559 .htotal = 800 + 39 + 47 + 39, 4560 .vdisplay = 480, 4561 .vsync_start = 480 + 13, 4562 .vsync_end = 480 + 13 + 2, 4563 .vtotal = 480 + 13 + 2 + 29, 4564}; 4565 4566static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4567 .modes = &tfc_s9700rtwv43tr_01b_mode, 4568 .num_modes = 1, 4569 .bpc = 8, 4570 .size = { 4571 .width = 155, 4572 .height = 90, 4573 }, 4574 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4575 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4576}; 4577 4578static const struct display_timing tianma_tm070jdhg30_timing = { 4579 .pixelclock = { 62600000, 68200000, 78100000 }, 4580 .hactive = { 1280, 1280, 1280 }, 4581 .hfront_porch = { 15, 64, 159 }, 4582 .hback_porch = { 5, 5, 5 }, 4583 .hsync_len = { 1, 1, 256 }, 4584 .vactive = { 800, 800, 800 }, 4585 .vfront_porch = { 3, 40, 99 }, 4586 .vback_porch = { 2, 2, 2 }, 4587 .vsync_len = { 1, 1, 128 }, 4588 .flags = DISPLAY_FLAGS_DE_HIGH, 4589}; 4590 4591static const struct panel_desc tianma_tm070jdhg30 = { 4592 .timings = &tianma_tm070jdhg30_timing, 4593 .num_timings = 1, 4594 .bpc = 8, 4595 .size = { 4596 .width = 151, 4597 .height = 95, 4598 }, 4599 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4600 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4601 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4602}; 4603 4604static const struct panel_desc tianma_tm070jvhg33 = { 4605 .timings = &tianma_tm070jdhg30_timing, 4606 .num_timings = 1, 4607 .bpc = 8, 4608 .size = { 4609 .width = 150, 4610 .height = 94, 4611 }, 4612 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4613 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4614 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4615}; 4616 4617/* 4618 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4619 * front porch, not including sync pulse width. This is for both H and 4620 * V. To make the total blanking and period correct, subtract the pulse 4621 * width from the front porch. 4622 * 4623 * This works well for the Min and Typ values, but for Max values the sync 4624 * pulse width is higher than back porch + front porch, so work around that 4625 * by reducing the Max sync length value to 1 and then treating the Max 4626 * porches as in the Min and Typ cases. 4627 * 4628 * Exact datasheet values are added as a comment where they differ from the 4629 * ones implemented for the above reason. 4630 * 4631 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4632 * and total blanking time, however the resulting values are the same as 4633 * the TM070JDHG34-00. 4634 */ 4635static const struct display_timing tianma_tm070jdhg34_00_timing = { 4636 .pixelclock = { 68400000, 71900000, 78100000 }, 4637 .hactive = { 1280, 1280, 1280 }, 4638 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4639 .hback_porch = { 5, 5, 5 }, 4640 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4641 .vactive = { 800, 800, 800 }, 4642 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4643 .vback_porch = { 2, 2, 2 }, 4644 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4645 .flags = DISPLAY_FLAGS_DE_HIGH, 4646}; 4647 4648static const struct panel_desc tianma_tm070jdhg34_00 = { 4649 .timings = &tianma_tm070jdhg34_00_timing, 4650 .num_timings = 1, 4651 .bpc = 8, 4652 .size = { 4653 .width = 150, /* 149.76 */ 4654 .height = 94, /* 93.60 */ 4655 }, 4656 .delay = { 4657 .prepare = 15, /* Tp1 */ 4658 .enable = 150, /* Tp2 */ 4659 .disable = 150, /* Tp4 */ 4660 .unprepare = 120, /* Tp3 */ 4661 }, 4662 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4663 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4664}; 4665 4666static const struct panel_desc tianma_p0700wxf1mbaa = { 4667 .timings = &tianma_tm070jdhg34_00_timing, 4668 .num_timings = 1, 4669 .bpc = 8, 4670 .size = { 4671 .width = 150, /* 149.76 */ 4672 .height = 94, /* 93.60 */ 4673 }, 4674 .delay = { 4675 .prepare = 18, /* Tr + Tp1 */ 4676 .enable = 152, /* Tp2 + Tp5 */ 4677 .disable = 152, /* Tp6 + Tp4 */ 4678 .unprepare = 120, /* Tp3 */ 4679 }, 4680 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4681 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4682}; 4683 4684static const struct display_timing tianma_tm070rvhg71_timing = { 4685 .pixelclock = { 27700000, 29200000, 39600000 }, 4686 .hactive = { 800, 800, 800 }, 4687 .hfront_porch = { 12, 40, 212 }, 4688 .hback_porch = { 88, 88, 88 }, 4689 .hsync_len = { 1, 1, 40 }, 4690 .vactive = { 480, 480, 480 }, 4691 .vfront_porch = { 1, 13, 88 }, 4692 .vback_porch = { 32, 32, 32 }, 4693 .vsync_len = { 1, 1, 3 }, 4694 .flags = DISPLAY_FLAGS_DE_HIGH, 4695}; 4696 4697static const struct panel_desc tianma_tm070rvhg71 = { 4698 .timings = &tianma_tm070rvhg71_timing, 4699 .num_timings = 1, 4700 .bpc = 8, 4701 .size = { 4702 .width = 154, 4703 .height = 86, 4704 }, 4705 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4706 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4707}; 4708 4709static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4710 { 4711 .clock = 10000, 4712 .hdisplay = 320, 4713 .hsync_start = 320 + 50, 4714 .hsync_end = 320 + 50 + 6, 4715 .htotal = 320 + 50 + 6 + 38, 4716 .vdisplay = 240, 4717 .vsync_start = 240 + 3, 4718 .vsync_end = 240 + 3 + 1, 4719 .vtotal = 240 + 3 + 1 + 17, 4720 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4721 }, 4722}; 4723 4724static const struct panel_desc ti_nspire_cx_lcd_panel = { 4725 .modes = ti_nspire_cx_lcd_mode, 4726 .num_modes = 1, 4727 .bpc = 8, 4728 .size = { 4729 .width = 65, 4730 .height = 49, 4731 }, 4732 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4733 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4734}; 4735 4736static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4737 { 4738 .clock = 10000, 4739 .hdisplay = 320, 4740 .hsync_start = 320 + 6, 4741 .hsync_end = 320 + 6 + 6, 4742 .htotal = 320 + 6 + 6 + 6, 4743 .vdisplay = 240, 4744 .vsync_start = 240 + 0, 4745 .vsync_end = 240 + 0 + 1, 4746 .vtotal = 240 + 0 + 1 + 0, 4747 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4748 }, 4749}; 4750 4751static const struct panel_desc ti_nspire_classic_lcd_panel = { 4752 .modes = ti_nspire_classic_lcd_mode, 4753 .num_modes = 1, 4754 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4755 .bpc = 8, 4756 .size = { 4757 .width = 71, 4758 .height = 53, 4759 }, 4760 /* This is the grayscale bus format */ 4761 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4762 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4763}; 4764 4765static const struct display_timing topland_tian_g07017_01_timing = { 4766 .pixelclock = { 44900000, 51200000, 63000000 }, 4767 .hactive = { 1024, 1024, 1024 }, 4768 .hfront_porch = { 16, 160, 216 }, 4769 .hback_porch = { 160, 160, 160 }, 4770 .hsync_len = { 1, 1, 140 }, 4771 .vactive = { 600, 600, 600 }, 4772 .vfront_porch = { 1, 12, 127 }, 4773 .vback_porch = { 23, 23, 23 }, 4774 .vsync_len = { 1, 1, 20 }, 4775}; 4776 4777static const struct panel_desc topland_tian_g07017_01 = { 4778 .timings = &topland_tian_g07017_01_timing, 4779 .num_timings = 1, 4780 .bpc = 8, 4781 .size = { 4782 .width = 154, 4783 .height = 86, 4784 }, 4785 .delay = { 4786 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4787 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4788 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4789 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4790 }, 4791 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4792 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4793 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4794}; 4795 4796static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4797 .clock = 79500, 4798 .hdisplay = 1280, 4799 .hsync_start = 1280 + 192, 4800 .hsync_end = 1280 + 192 + 128, 4801 .htotal = 1280 + 192 + 128 + 64, 4802 .vdisplay = 768, 4803 .vsync_start = 768 + 20, 4804 .vsync_end = 768 + 20 + 7, 4805 .vtotal = 768 + 20 + 7 + 3, 4806}; 4807 4808static const struct panel_desc toshiba_lt089ac29000 = { 4809 .modes = &toshiba_lt089ac29000_mode, 4810 .num_modes = 1, 4811 .size = { 4812 .width = 194, 4813 .height = 116, 4814 }, 4815 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4816 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4817 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4818}; 4819 4820static const struct drm_display_mode tpk_f07a_0102_mode = { 4821 .clock = 33260, 4822 .hdisplay = 800, 4823 .hsync_start = 800 + 40, 4824 .hsync_end = 800 + 40 + 128, 4825 .htotal = 800 + 40 + 128 + 88, 4826 .vdisplay = 480, 4827 .vsync_start = 480 + 10, 4828 .vsync_end = 480 + 10 + 2, 4829 .vtotal = 480 + 10 + 2 + 33, 4830}; 4831 4832static const struct panel_desc tpk_f07a_0102 = { 4833 .modes = &tpk_f07a_0102_mode, 4834 .num_modes = 1, 4835 .size = { 4836 .width = 152, 4837 .height = 91, 4838 }, 4839 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4840}; 4841 4842static const struct drm_display_mode tpk_f10a_0102_mode = { 4843 .clock = 45000, 4844 .hdisplay = 1024, 4845 .hsync_start = 1024 + 176, 4846 .hsync_end = 1024 + 176 + 5, 4847 .htotal = 1024 + 176 + 5 + 88, 4848 .vdisplay = 600, 4849 .vsync_start = 600 + 20, 4850 .vsync_end = 600 + 20 + 5, 4851 .vtotal = 600 + 20 + 5 + 25, 4852}; 4853 4854static const struct panel_desc tpk_f10a_0102 = { 4855 .modes = &tpk_f10a_0102_mode, 4856 .num_modes = 1, 4857 .size = { 4858 .width = 223, 4859 .height = 125, 4860 }, 4861}; 4862 4863static const struct display_timing urt_umsh_8596md_timing = { 4864 .pixelclock = { 33260000, 33260000, 33260000 }, 4865 .hactive = { 800, 800, 800 }, 4866 .hfront_porch = { 41, 41, 41 }, 4867 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4868 .hsync_len = { 71, 128, 128 }, 4869 .vactive = { 480, 480, 480 }, 4870 .vfront_porch = { 10, 10, 10 }, 4871 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4872 .vsync_len = { 2, 2, 2 }, 4873 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4874 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4875}; 4876 4877static const struct panel_desc urt_umsh_8596md_lvds = { 4878 .timings = &urt_umsh_8596md_timing, 4879 .num_timings = 1, 4880 .bpc = 6, 4881 .size = { 4882 .width = 152, 4883 .height = 91, 4884 }, 4885 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4886 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4887}; 4888 4889static const struct panel_desc urt_umsh_8596md_parallel = { 4890 .timings = &urt_umsh_8596md_timing, 4891 .num_timings = 1, 4892 .bpc = 6, 4893 .size = { 4894 .width = 152, 4895 .height = 91, 4896 }, 4897 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4898}; 4899 4900static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4901 .clock = 60000, 4902 .hdisplay = 1024, 4903 .hsync_start = 1024 + 160, 4904 .hsync_end = 1024 + 160 + 100, 4905 .htotal = 1024 + 160 + 100 + 60, 4906 .vdisplay = 600, 4907 .vsync_start = 600 + 12, 4908 .vsync_end = 600 + 12 + 10, 4909 .vtotal = 600 + 12 + 10 + 13, 4910}; 4911 4912static const struct panel_desc vivax_tpc9150_panel = { 4913 .modes = &vivax_tpc9150_panel_mode, 4914 .num_modes = 1, 4915 .bpc = 6, 4916 .size = { 4917 .width = 200, 4918 .height = 115, 4919 }, 4920 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4921 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4922 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4923}; 4924 4925static const struct drm_display_mode vl050_8048nt_c01_mode = { 4926 .clock = 33333, 4927 .hdisplay = 800, 4928 .hsync_start = 800 + 210, 4929 .hsync_end = 800 + 210 + 20, 4930 .htotal = 800 + 210 + 20 + 46, 4931 .vdisplay = 480, 4932 .vsync_start = 480 + 22, 4933 .vsync_end = 480 + 22 + 10, 4934 .vtotal = 480 + 22 + 10 + 23, 4935 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4936}; 4937 4938static const struct panel_desc vl050_8048nt_c01 = { 4939 .modes = &vl050_8048nt_c01_mode, 4940 .num_modes = 1, 4941 .bpc = 8, 4942 .size = { 4943 .width = 120, 4944 .height = 76, 4945 }, 4946 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4947 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4948}; 4949 4950static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4951 .clock = 6410, 4952 .hdisplay = 320, 4953 .hsync_start = 320 + 20, 4954 .hsync_end = 320 + 20 + 30, 4955 .htotal = 320 + 20 + 30 + 38, 4956 .vdisplay = 240, 4957 .vsync_start = 240 + 4, 4958 .vsync_end = 240 + 4 + 3, 4959 .vtotal = 240 + 4 + 3 + 15, 4960 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4961}; 4962 4963static const struct panel_desc winstar_wf35ltiacd = { 4964 .modes = &winstar_wf35ltiacd_mode, 4965 .num_modes = 1, 4966 .bpc = 8, 4967 .size = { 4968 .width = 70, 4969 .height = 53, 4970 }, 4971 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4972}; 4973 4974static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4975 .clock = 51200, 4976 .hdisplay = 1024, 4977 .hsync_start = 1024 + 100, 4978 .hsync_end = 1024 + 100 + 100, 4979 .htotal = 1024 + 100 + 100 + 120, 4980 .vdisplay = 600, 4981 .vsync_start = 600 + 10, 4982 .vsync_end = 600 + 10 + 10, 4983 .vtotal = 600 + 10 + 10 + 15, 4984 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4985}; 4986 4987static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4988 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4989 .num_modes = 1, 4990 .bpc = 8, 4991 .size = { 4992 .width = 154, 4993 .height = 90, 4994 }, 4995 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4996 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4997 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4998}; 4999 5000static const struct drm_display_mode mchp_ac69t88a_mode = { 5001 .clock = 25000, 5002 .hdisplay = 800, 5003 .hsync_start = 800 + 88, 5004 .hsync_end = 800 + 88 + 5, 5005 .htotal = 800 + 88 + 5 + 40, 5006 .vdisplay = 480, 5007 .vsync_start = 480 + 23, 5008 .vsync_end = 480 + 23 + 5, 5009 .vtotal = 480 + 23 + 5 + 1, 5010}; 5011 5012static const struct panel_desc mchp_ac69t88a = { 5013 .modes = &mchp_ac69t88a_mode, 5014 .num_modes = 1, 5015 .bpc = 8, 5016 .size = { 5017 .width = 108, 5018 .height = 65, 5019 }, 5020 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5021 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5022 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5023}; 5024 5025static const struct drm_display_mode arm_rtsm_mode[] = { 5026 { 5027 .clock = 65000, 5028 .hdisplay = 1024, 5029 .hsync_start = 1024 + 24, 5030 .hsync_end = 1024 + 24 + 136, 5031 .htotal = 1024 + 24 + 136 + 160, 5032 .vdisplay = 768, 5033 .vsync_start = 768 + 3, 5034 .vsync_end = 768 + 3 + 6, 5035 .vtotal = 768 + 3 + 6 + 29, 5036 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5037 }, 5038}; 5039 5040static const struct panel_desc arm_rtsm = { 5041 .modes = arm_rtsm_mode, 5042 .num_modes = 1, 5043 .bpc = 8, 5044 .size = { 5045 .width = 400, 5046 .height = 300, 5047 }, 5048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5049}; 5050 5051static const struct of_device_id platform_of_match[] = { 5052 { 5053 .compatible = "ampire,am-1280800n3tzqw-t00h", 5054 .data = &ire_am_1280800n3tzqw_t00h, 5055 }, { 5056 .compatible = "ampire,am-480272h3tmqw-t01h", 5057 .data = &ire_am_480272h3tmqw_t01h, 5058 }, { 5059 .compatible = "ampire,am-800480l1tmqw-t00h", 5060 .data = &ire_am_800480l1tmqw_t00h, 5061 }, { 5062 .compatible = "ampire,am800480r3tmqwa1h", 5063 .data = &ire_am800480r3tmqwa1h, 5064 }, { 5065 .compatible = "ampire,am800600p5tmqw-tb8h", 5066 .data = &ire_am800600p5tmqwtb8h, 5067 }, { 5068 .compatible = "arm,rtsm-display", 5069 .data = &arm_rtsm, 5070 }, { 5071 .compatible = "armadeus,st0700-adapt", 5072 .data = &armadeus_st0700_adapt, 5073 }, { 5074 .compatible = "auo,b101aw03", 5075 .data = &auo_b101aw03, 5076 }, { 5077 .compatible = "auo,b101xtn01", 5078 .data = &auo_b101xtn01, 5079 }, { 5080 .compatible = "auo,b116xw03", 5081 .data = &auo_b116xw03, 5082 }, { 5083 .compatible = "auo,g070vvn01", 5084 .data = &auo_g070vvn01, 5085 }, { 5086 .compatible = "auo,g101evn010", 5087 .data = &auo_g101evn010, 5088 }, { 5089 .compatible = "auo,g104sn02", 5090 .data = &auo_g104sn02, 5091 }, { 5092 .compatible = "auo,g104stn01", 5093 .data = &auo_g104stn01, 5094 }, { 5095 .compatible = "auo,g121ean01", 5096 .data = &auo_g121ean01, 5097 }, { 5098 .compatible = "auo,g133han01", 5099 .data = &auo_g133han01, 5100 }, { 5101 .compatible = "auo,g156han04", 5102 .data = &auo_g156han04, 5103 }, { 5104 .compatible = "auo,g156xtn01", 5105 .data = &auo_g156xtn01, 5106 }, { 5107 .compatible = "auo,g185han01", 5108 .data = &auo_g185han01, 5109 }, { 5110 .compatible = "auo,g190ean01", 5111 .data = &auo_g190ean01, 5112 }, { 5113 .compatible = "auo,p238han01", 5114 .data = &auo_p238han01, 5115 }, { 5116 .compatible = "auo,p320hvn03", 5117 .data = &auo_p320hvn03, 5118 }, { 5119 .compatible = "auo,t215hvn01", 5120 .data = &auo_t215hvn01, 5121 }, { 5122 .compatible = "avic,tm070ddh03", 5123 .data = &avic_tm070ddh03, 5124 }, { 5125 .compatible = "bananapi,s070wv20-ct16", 5126 .data = &bananapi_s070wv20_ct16, 5127 }, { 5128 .compatible = "boe,av101hdt-a10", 5129 .data = &boe_av101hdt_a10, 5130 }, { 5131 .compatible = "boe,av123z7m-n17", 5132 .data = &boe_av123z7m_n17, 5133 }, { 5134 .compatible = "boe,bp082wx1-100", 5135 .data = &boe_bp082wx1_100, 5136 }, { 5137 .compatible = "boe,bp101wx1-100", 5138 .data = &boe_bp101wx1_100, 5139 }, { 5140 .compatible = "boe,ev121wxm-n10-1850", 5141 .data = &boe_ev121wxm_n10_1850, 5142 }, { 5143 .compatible = "boe,hv070wsa-100", 5144 .data = &boe_hv070wsa 5145 }, { 5146 .compatible = "cct,cmt430b19n00", 5147 .data = &cct_cmt430b19n00, 5148 }, { 5149 .compatible = "cdtech,s043wq26h-ct7", 5150 .data = &cdtech_s043wq26h_ct7, 5151 }, { 5152 .compatible = "cdtech,s070pws19hp-fc21", 5153 .data = &cdtech_s070pws19hp_fc21, 5154 }, { 5155 .compatible = "cdtech,s070swv29hg-dc44", 5156 .data = &cdtech_s070swv29hg_dc44, 5157 }, { 5158 .compatible = "cdtech,s070wv95-ct16", 5159 .data = &cdtech_s070wv95_ct16, 5160 }, { 5161 .compatible = "chefree,ch101olhlwh-002", 5162 .data = &chefree_ch101olhlwh_002, 5163 }, { 5164 .compatible = "chunghwa,claa070wp03xg", 5165 .data = &chunghwa_claa070wp03xg, 5166 }, { 5167 .compatible = "chunghwa,claa101wa01a", 5168 .data = &chunghwa_claa101wa01a 5169 }, { 5170 .compatible = "chunghwa,claa101wb01", 5171 .data = &chunghwa_claa101wb01 5172 }, { 5173 .compatible = "dataimage,fg040346dsswbg04", 5174 .data = &dataimage_fg040346dsswbg04, 5175 }, { 5176 .compatible = "dataimage,fg1001l0dsswmg01", 5177 .data = &dataimage_fg1001l0dsswmg01, 5178 }, { 5179 .compatible = "dataimage,scf0700c48ggu18", 5180 .data = &dataimage_scf0700c48ggu18, 5181 }, { 5182 .compatible = "dlc,dlc0700yzg-1", 5183 .data = &dlc_dlc0700yzg_1, 5184 }, { 5185 .compatible = "dlc,dlc1010gig", 5186 .data = &dlc_dlc1010gig, 5187 }, { 5188 .compatible = "edt,et035012dm6", 5189 .data = &edt_et035012dm6, 5190 }, { 5191 .compatible = "edt,etm0350g0dh6", 5192 .data = &edt_etm0350g0dh6, 5193 }, { 5194 .compatible = "edt,etm043080dh6gp", 5195 .data = &edt_etm043080dh6gp, 5196 }, { 5197 .compatible = "edt,etm0430g0dh6", 5198 .data = &edt_etm0430g0dh6, 5199 }, { 5200 .compatible = "edt,et057090dhu", 5201 .data = &edt_et057090dhu, 5202 }, { 5203 .compatible = "edt,et070080dh6", 5204 .data = &edt_etm0700g0dh6, 5205 }, { 5206 .compatible = "edt,etm0700g0dh6", 5207 .data = &edt_etm0700g0dh6, 5208 }, { 5209 .compatible = "edt,etm0700g0bdh6", 5210 .data = &edt_etm0700g0bdh6, 5211 }, { 5212 .compatible = "edt,etm0700g0edh6", 5213 .data = &edt_etm0700g0bdh6, 5214 }, { 5215 .compatible = "edt,etml0700y5dha", 5216 .data = &edt_etml0700y5dha, 5217 }, { 5218 .compatible = "edt,etml1010g3dra", 5219 .data = &edt_etml1010g3dra, 5220 }, { 5221 .compatible = "edt,etmv570g2dhu", 5222 .data = &edt_etmv570g2dhu, 5223 }, { 5224 .compatible = "eink,vb3300-kca", 5225 .data = &eink_vb3300_kca, 5226 }, { 5227 .compatible = "evervision,vgg644804", 5228 .data = &evervision_vgg644804, 5229 }, { 5230 .compatible = "evervision,vgg804821", 5231 .data = &evervision_vgg804821, 5232 }, { 5233 .compatible = "foxlink,fl500wvr00-a0t", 5234 .data = &foxlink_fl500wvr00_a0t, 5235 }, { 5236 .compatible = "frida,frd350h54004", 5237 .data = &frida_frd350h54004, 5238 }, { 5239 .compatible = "friendlyarm,hd702e", 5240 .data = &friendlyarm_hd702e, 5241 }, { 5242 .compatible = "giantplus,gpg482739qs5", 5243 .data = &giantplus_gpg482739qs5 5244 }, { 5245 .compatible = "giantplus,gpm940b0", 5246 .data = &giantplus_gpm940b0, 5247 }, { 5248 .compatible = "hannstar,hsd070pww1", 5249 .data = &hannstar_hsd070pww1, 5250 }, { 5251 .compatible = "hannstar,hsd100pxn1", 5252 .data = &hannstar_hsd100pxn1, 5253 }, { 5254 .compatible = "hannstar,hsd101pww2", 5255 .data = &hannstar_hsd101pww2, 5256 }, { 5257 .compatible = "hit,tx23d38vm0caa", 5258 .data = &hitachi_tx23d38vm0caa 5259 }, { 5260 .compatible = "innolux,at043tn24", 5261 .data = &innolux_at043tn24, 5262 }, { 5263 .compatible = "innolux,at070tn92", 5264 .data = &innolux_at070tn92, 5265 }, { 5266 .compatible = "innolux,g070ace-l01", 5267 .data = &innolux_g070ace_l01, 5268 }, { 5269 .compatible = "innolux,g070ace-lh3", 5270 .data = &innolux_g070ace_lh3, 5271 }, { 5272 .compatible = "innolux,g070y2-l01", 5273 .data = &innolux_g070y2_l01, 5274 }, { 5275 .compatible = "innolux,g070y2-t02", 5276 .data = &innolux_g070y2_t02, 5277 }, { 5278 .compatible = "innolux,g101ice-l01", 5279 .data = &innolux_g101ice_l01 5280 }, { 5281 .compatible = "innolux,g121i1-l01", 5282 .data = &innolux_g121i1_l01 5283 }, { 5284 .compatible = "innolux,g121x1-l03", 5285 .data = &innolux_g121x1_l03, 5286 }, { 5287 .compatible = "innolux,g121xce-l01", 5288 .data = &innolux_g121xce_l01, 5289 }, { 5290 .compatible = "innolux,g156hce-l01", 5291 .data = &innolux_g156hce_l01, 5292 }, { 5293 .compatible = "innolux,n156bge-l21", 5294 .data = &innolux_n156bge_l21, 5295 }, { 5296 .compatible = "innolux,zj070na-01p", 5297 .data = &innolux_zj070na_01p, 5298 }, { 5299 .compatible = "jutouch,jt101tm023", 5300 .data = &jutouch_jt101tm023, 5301 }, { 5302 .compatible = "koe,tx14d24vm1bpa", 5303 .data = &koe_tx14d24vm1bpa, 5304 }, { 5305 .compatible = "koe,tx26d202vm0bwa", 5306 .data = &koe_tx26d202vm0bwa, 5307 }, { 5308 .compatible = "koe,tx31d200vm0baa", 5309 .data = &koe_tx31d200vm0baa, 5310 }, { 5311 .compatible = "kyo,tcg121xglp", 5312 .data = &kyo_tcg121xglp, 5313 }, { 5314 .compatible = "lemaker,bl035-rgb-002", 5315 .data = &lemaker_bl035_rgb_002, 5316 }, { 5317 .compatible = "lg,lb070wv8", 5318 .data = &lg_lb070wv8, 5319 }, { 5320 .compatible = "lincolntech,lcd185-101ct", 5321 .data = &lincolntech_lcd185_101ct, 5322 }, { 5323 .compatible = "logicpd,type28", 5324 .data = &logicpd_type_28, 5325 }, { 5326 .compatible = "logictechno,lt161010-2nhc", 5327 .data = &logictechno_lt161010_2nh, 5328 }, { 5329 .compatible = "logictechno,lt161010-2nhr", 5330 .data = &logictechno_lt161010_2nh, 5331 }, { 5332 .compatible = "logictechno,lt170410-2whc", 5333 .data = &logictechno_lt170410_2whc, 5334 }, { 5335 .compatible = "logictechno,lttd800480070-l2rt", 5336 .data = &logictechno_lttd800480070_l2rt, 5337 }, { 5338 .compatible = "logictechno,lttd800480070-l6wh-rt", 5339 .data = &logictechno_lttd800480070_l6wh_rt, 5340 }, { 5341 .compatible = "microtips,mf-101hiebcaf0", 5342 .data = µtips_mf_101hiebcaf0_c, 5343 }, { 5344 .compatible = "microtips,mf-103hieb0ga0", 5345 .data = µtips_mf_103hieb0ga0, 5346 }, { 5347 .compatible = "mitsubishi,aa070mc01-ca1", 5348 .data = &mitsubishi_aa070mc01, 5349 }, { 5350 .compatible = "mitsubishi,aa084xe01", 5351 .data = &mitsubishi_aa084xe01, 5352 }, { 5353 .compatible = "multi-inno,mi0700a2t-30", 5354 .data = &multi_inno_mi0700a2t_30, 5355 }, { 5356 .compatible = "multi-inno,mi0700s4t-6", 5357 .data = &multi_inno_mi0700s4t_6, 5358 }, { 5359 .compatible = "multi-inno,mi0800ft-9", 5360 .data = &multi_inno_mi0800ft_9, 5361 }, { 5362 .compatible = "multi-inno,mi1010ait-1cp", 5363 .data = &multi_inno_mi1010ait_1cp, 5364 }, { 5365 .compatible = "multi-inno,mi1010z1t-1cp11", 5366 .data = &multi_inno_mi1010z1t_1cp11, 5367 }, { 5368 .compatible = "nec,nl12880bc20-05", 5369 .data = &nec_nl12880bc20_05, 5370 }, { 5371 .compatible = "nec,nl4827hc19-05b", 5372 .data = &nec_nl4827hc19_05b, 5373 }, { 5374 .compatible = "netron-dy,e231732", 5375 .data = &netron_dy_e231732, 5376 }, { 5377 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5378 .data = &newhaven_nhd_43_480272ef_atxl, 5379 }, { 5380 .compatible = "nlt,nl13676bc25-03f", 5381 .data = &nlt_nl13676bc25_03f, 5382 }, { 5383 .compatible = "nlt,nl192108ac18-02d", 5384 .data = &nlt_nl192108ac18_02d, 5385 }, { 5386 .compatible = "nvd,9128", 5387 .data = &nvd_9128, 5388 }, { 5389 .compatible = "okaya,rs800480t-7x0gp", 5390 .data = &okaya_rs800480t_7x0gp, 5391 }, { 5392 .compatible = "olimex,lcd-olinuxino-43-ts", 5393 .data = &olimex_lcd_olinuxino_43ts, 5394 }, { 5395 .compatible = "olimex,lcd-olinuxino-5-cts", 5396 .data = &olimex_lcd_olinuxino_5cts, 5397 }, { 5398 .compatible = "ontat,kd50g21-40nt-a1", 5399 .data = &ontat_kd50g21_40nt_a1, 5400 }, { 5401 .compatible = "ontat,yx700wv03", 5402 .data = &ontat_yx700wv03, 5403 }, { 5404 .compatible = "ortustech,com37h3m05dtc", 5405 .data = &ortustech_com37h3m, 5406 }, { 5407 .compatible = "ortustech,com37h3m99dtc", 5408 .data = &ortustech_com37h3m, 5409 }, { 5410 .compatible = "ortustech,com43h4m85ulc", 5411 .data = &ortustech_com43h4m85ulc, 5412 }, { 5413 .compatible = "osddisplays,osd070t1718-19ts", 5414 .data = &osddisplays_osd070t1718_19ts, 5415 }, { 5416 .compatible = "pda,91-00156-a0", 5417 .data = &pda_91_00156_a0, 5418 }, { 5419 .compatible = "powertip,ph128800t004-zza01", 5420 .data = &powertip_ph128800t004_zza01, 5421 }, { 5422 .compatible = "powertip,ph128800t006-zhc01", 5423 .data = &powertip_ph128800t006_zhc01, 5424 }, { 5425 .compatible = "powertip,ph800480t013-idf02", 5426 .data = &powertip_ph800480t013_idf02, 5427 }, { 5428 .compatible = "primeview,pm070wl4", 5429 .data = &primeview_pm070wl4, 5430 }, { 5431 .compatible = "qiaodian,qd43003c0-40", 5432 .data = &qd43003c0_40, 5433 }, { 5434 .compatible = "qishenglong,gopher2b-lcd", 5435 .data = &qishenglong_gopher2b_lcd, 5436 }, { 5437 .compatible = "raystar,rff500f-awh-dnn", 5438 .data = &raystar_rff500f_awh_dnn, 5439 }, { 5440 .compatible = "rocktech,rk043fn48h", 5441 .data = &rocktech_rk043fn48h, 5442 }, { 5443 .compatible = "rocktech,rk070er9427", 5444 .data = &rocktech_rk070er9427, 5445 }, { 5446 .compatible = "rocktech,rk101ii01d-ct", 5447 .data = &rocktech_rk101ii01d_ct, 5448 }, { 5449 .compatible = "samsung,ltl101al01", 5450 .data = &samsung_ltl101al01, 5451 }, { 5452 .compatible = "samsung,ltl106al01", 5453 .data = &samsung_ltl106al01, 5454 }, { 5455 .compatible = "samsung,ltn101nt05", 5456 .data = &samsung_ltn101nt05, 5457 }, { 5458 .compatible = "satoz,sat050at40h12r2", 5459 .data = &satoz_sat050at40h12r2, 5460 }, { 5461 .compatible = "sharp,lq035q7db03", 5462 .data = &sharp_lq035q7db03, 5463 }, { 5464 .compatible = "sharp,lq070y3dg3b", 5465 .data = &sharp_lq070y3dg3b, 5466 }, { 5467 .compatible = "sharp,lq101k1ly04", 5468 .data = &sharp_lq101k1ly04, 5469 }, { 5470 .compatible = "sharp,ls020b1dd01d", 5471 .data = &sharp_ls020b1dd01d, 5472 }, { 5473 .compatible = "shelly,sca07010-bfn-lnn", 5474 .data = &shelly_sca07010_bfn_lnn, 5475 }, { 5476 .compatible = "starry,kr070pe2t", 5477 .data = &starry_kr070pe2t, 5478 }, { 5479 .compatible = "startek,kd070wvfpa", 5480 .data = &startek_kd070wvfpa, 5481 }, { 5482 .compatible = "team-source-display,tst043015cmhx", 5483 .data = &tsd_tst043015cmhx, 5484 }, { 5485 .compatible = "tfc,s9700rtwv43tr-01b", 5486 .data = &tfc_s9700rtwv43tr_01b, 5487 }, { 5488 .compatible = "tianma,p0700wxf1mbaa", 5489 .data = &tianma_p0700wxf1mbaa, 5490 }, { 5491 .compatible = "tianma,tm070jdhg30", 5492 .data = &tianma_tm070jdhg30, 5493 }, { 5494 .compatible = "tianma,tm070jdhg34-00", 5495 .data = &tianma_tm070jdhg34_00, 5496 }, { 5497 .compatible = "tianma,tm070jvhg33", 5498 .data = &tianma_tm070jvhg33, 5499 }, { 5500 .compatible = "tianma,tm070rvhg71", 5501 .data = &tianma_tm070rvhg71, 5502 }, { 5503 .compatible = "ti,nspire-cx-lcd-panel", 5504 .data = &ti_nspire_cx_lcd_panel, 5505 }, { 5506 .compatible = "ti,nspire-classic-lcd-panel", 5507 .data = &ti_nspire_classic_lcd_panel, 5508 }, { 5509 .compatible = "toshiba,lt089ac29000", 5510 .data = &toshiba_lt089ac29000, 5511 }, { 5512 .compatible = "topland,tian-g07017-01", 5513 .data = &topland_tian_g07017_01, 5514 }, { 5515 .compatible = "tpk,f07a-0102", 5516 .data = &tpk_f07a_0102, 5517 }, { 5518 .compatible = "tpk,f10a-0102", 5519 .data = &tpk_f10a_0102, 5520 }, { 5521 .compatible = "urt,umsh-8596md-t", 5522 .data = &urt_umsh_8596md_parallel, 5523 }, { 5524 .compatible = "urt,umsh-8596md-1t", 5525 .data = &urt_umsh_8596md_parallel, 5526 }, { 5527 .compatible = "urt,umsh-8596md-7t", 5528 .data = &urt_umsh_8596md_parallel, 5529 }, { 5530 .compatible = "urt,umsh-8596md-11t", 5531 .data = &urt_umsh_8596md_lvds, 5532 }, { 5533 .compatible = "urt,umsh-8596md-19t", 5534 .data = &urt_umsh_8596md_lvds, 5535 }, { 5536 .compatible = "urt,umsh-8596md-20t", 5537 .data = &urt_umsh_8596md_parallel, 5538 }, { 5539 .compatible = "vivax,tpc9150-panel", 5540 .data = &vivax_tpc9150_panel, 5541 }, { 5542 .compatible = "vxt,vl050-8048nt-c01", 5543 .data = &vl050_8048nt_c01, 5544 }, { 5545 .compatible = "winstar,wf35ltiacd", 5546 .data = &winstar_wf35ltiacd, 5547 }, { 5548 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5549 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5550 }, { 5551 .compatible = "microchip,ac69t88a", 5552 .data = &mchp_ac69t88a, 5553 }, { 5554 /* Must be the last entry */ 5555 .compatible = "panel-dpi", 5556 5557 /* 5558 * Explicitly NULL, the panel_desc structure will be 5559 * allocated by panel_dpi_probe(). 5560 */ 5561 .data = NULL, 5562 }, { 5563 /* sentinel */ 5564 } 5565}; 5566MODULE_DEVICE_TABLE(of, platform_of_match); 5567 5568static int panel_simple_platform_probe(struct platform_device *pdev) 5569{ 5570 struct panel_simple *panel; 5571 5572 panel = panel_simple_probe(&pdev->dev); 5573 if (IS_ERR(panel)) 5574 return PTR_ERR(panel); 5575 5576 return 0; 5577} 5578 5579static void panel_simple_platform_remove(struct platform_device *pdev) 5580{ 5581 panel_simple_remove(&pdev->dev); 5582} 5583 5584static void panel_simple_platform_shutdown(struct platform_device *pdev) 5585{ 5586 panel_simple_shutdown(&pdev->dev); 5587} 5588 5589static const struct dev_pm_ops panel_simple_pm_ops = { 5590 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5591 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5592 pm_runtime_force_resume) 5593}; 5594 5595static struct platform_driver panel_simple_platform_driver = { 5596 .driver = { 5597 .name = "panel-simple", 5598 .of_match_table = platform_of_match, 5599 .pm = &panel_simple_pm_ops, 5600 }, 5601 .probe = panel_simple_platform_probe, 5602 .remove = panel_simple_platform_remove, 5603 .shutdown = panel_simple_platform_shutdown, 5604}; 5605 5606static const struct drm_display_mode auo_b080uan01_mode = { 5607 .clock = 154500, 5608 .hdisplay = 1200, 5609 .hsync_start = 1200 + 62, 5610 .hsync_end = 1200 + 62 + 4, 5611 .htotal = 1200 + 62 + 4 + 62, 5612 .vdisplay = 1920, 5613 .vsync_start = 1920 + 9, 5614 .vsync_end = 1920 + 9 + 2, 5615 .vtotal = 1920 + 9 + 2 + 8, 5616}; 5617 5618static const struct panel_desc_dsi auo_b080uan01 = { 5619 .desc = { 5620 .modes = &auo_b080uan01_mode, 5621 .num_modes = 1, 5622 .bpc = 8, 5623 .size = { 5624 .width = 108, 5625 .height = 272, 5626 }, 5627 .connector_type = DRM_MODE_CONNECTOR_DSI, 5628 }, 5629 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5630 .format = MIPI_DSI_FMT_RGB888, 5631 .lanes = 4, 5632}; 5633 5634static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5635 .clock = 160000, 5636 .hdisplay = 1200, 5637 .hsync_start = 1200 + 120, 5638 .hsync_end = 1200 + 120 + 20, 5639 .htotal = 1200 + 120 + 20 + 21, 5640 .vdisplay = 1920, 5641 .vsync_start = 1920 + 21, 5642 .vsync_end = 1920 + 21 + 3, 5643 .vtotal = 1920 + 21 + 3 + 18, 5644 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5645}; 5646 5647static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5648 .desc = { 5649 .modes = &boe_tv080wum_nl0_mode, 5650 .num_modes = 1, 5651 .size = { 5652 .width = 107, 5653 .height = 172, 5654 }, 5655 .connector_type = DRM_MODE_CONNECTOR_DSI, 5656 }, 5657 .flags = MIPI_DSI_MODE_VIDEO | 5658 MIPI_DSI_MODE_VIDEO_BURST | 5659 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5660 .format = MIPI_DSI_FMT_RGB888, 5661 .lanes = 4, 5662}; 5663 5664static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5665 .clock = 67000, 5666 .hdisplay = 720, 5667 .hsync_start = 720 + 12, 5668 .hsync_end = 720 + 12 + 4, 5669 .htotal = 720 + 12 + 4 + 112, 5670 .vdisplay = 1280, 5671 .vsync_start = 1280 + 8, 5672 .vsync_end = 1280 + 8 + 4, 5673 .vtotal = 1280 + 8 + 4 + 12, 5674}; 5675 5676static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5677 .desc = { 5678 .modes = &lg_lh500wx1_sd03_mode, 5679 .num_modes = 1, 5680 .bpc = 8, 5681 .size = { 5682 .width = 62, 5683 .height = 110, 5684 }, 5685 .connector_type = DRM_MODE_CONNECTOR_DSI, 5686 }, 5687 .flags = MIPI_DSI_MODE_VIDEO, 5688 .format = MIPI_DSI_FMT_RGB888, 5689 .lanes = 4, 5690}; 5691 5692static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5693 .clock = 157200, 5694 .hdisplay = 1920, 5695 .hsync_start = 1920 + 154, 5696 .hsync_end = 1920 + 154 + 16, 5697 .htotal = 1920 + 154 + 16 + 32, 5698 .vdisplay = 1200, 5699 .vsync_start = 1200 + 17, 5700 .vsync_end = 1200 + 17 + 2, 5701 .vtotal = 1200 + 17 + 2 + 16, 5702}; 5703 5704static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5705 .desc = { 5706 .modes = &panasonic_vvx10f004b00_mode, 5707 .num_modes = 1, 5708 .bpc = 8, 5709 .size = { 5710 .width = 217, 5711 .height = 136, 5712 }, 5713 .connector_type = DRM_MODE_CONNECTOR_DSI, 5714 }, 5715 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5716 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5717 .format = MIPI_DSI_FMT_RGB888, 5718 .lanes = 4, 5719}; 5720 5721static const struct drm_display_mode lg_acx467akm_7_mode = { 5722 .clock = 150000, 5723 .hdisplay = 1080, 5724 .hsync_start = 1080 + 2, 5725 .hsync_end = 1080 + 2 + 2, 5726 .htotal = 1080 + 2 + 2 + 2, 5727 .vdisplay = 1920, 5728 .vsync_start = 1920 + 2, 5729 .vsync_end = 1920 + 2 + 2, 5730 .vtotal = 1920 + 2 + 2 + 2, 5731}; 5732 5733static const struct panel_desc_dsi lg_acx467akm_7 = { 5734 .desc = { 5735 .modes = &lg_acx467akm_7_mode, 5736 .num_modes = 1, 5737 .bpc = 8, 5738 .size = { 5739 .width = 62, 5740 .height = 110, 5741 }, 5742 .connector_type = DRM_MODE_CONNECTOR_DSI, 5743 }, 5744 .flags = 0, 5745 .format = MIPI_DSI_FMT_RGB888, 5746 .lanes = 4, 5747}; 5748 5749static const struct drm_display_mode osd101t2045_53ts_mode = { 5750 .clock = 154500, 5751 .hdisplay = 1920, 5752 .hsync_start = 1920 + 112, 5753 .hsync_end = 1920 + 112 + 16, 5754 .htotal = 1920 + 112 + 16 + 32, 5755 .vdisplay = 1200, 5756 .vsync_start = 1200 + 16, 5757 .vsync_end = 1200 + 16 + 2, 5758 .vtotal = 1200 + 16 + 2 + 16, 5759 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5760}; 5761 5762static const struct panel_desc_dsi osd101t2045_53ts = { 5763 .desc = { 5764 .modes = &osd101t2045_53ts_mode, 5765 .num_modes = 1, 5766 .bpc = 8, 5767 .size = { 5768 .width = 217, 5769 .height = 136, 5770 }, 5771 .connector_type = DRM_MODE_CONNECTOR_DSI, 5772 }, 5773 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5774 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5775 MIPI_DSI_MODE_NO_EOT_PACKET, 5776 .format = MIPI_DSI_FMT_RGB888, 5777 .lanes = 4, 5778}; 5779 5780static const struct of_device_id dsi_of_match[] = { 5781 { 5782 .compatible = "auo,b080uan01", 5783 .data = &auo_b080uan01 5784 }, { 5785 .compatible = "boe,tv080wum-nl0", 5786 .data = &boe_tv080wum_nl0 5787 }, { 5788 .compatible = "lg,lh500wx1-sd03", 5789 .data = &lg_lh500wx1_sd03 5790 }, { 5791 .compatible = "panasonic,vvx10f004b00", 5792 .data = &panasonic_vvx10f004b00 5793 }, { 5794 .compatible = "lg,acx467akm-7", 5795 .data = &lg_acx467akm_7 5796 }, { 5797 .compatible = "osddisplays,osd101t2045-53ts", 5798 .data = &osd101t2045_53ts 5799 }, { 5800 /* sentinel */ 5801 } 5802}; 5803MODULE_DEVICE_TABLE(of, dsi_of_match); 5804 5805static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5806{ 5807 const struct panel_desc_dsi *desc; 5808 struct panel_simple *panel; 5809 int err; 5810 5811 panel = panel_simple_probe(&dsi->dev); 5812 if (IS_ERR(panel)) 5813 return PTR_ERR(panel); 5814 5815 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5816 dsi->mode_flags = desc->flags; 5817 dsi->format = desc->format; 5818 dsi->lanes = desc->lanes; 5819 5820 err = mipi_dsi_attach(dsi); 5821 if (err) { 5822 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5823 5824 drm_panel_remove(&panel->base); 5825 } 5826 5827 return err; 5828} 5829 5830static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5831{ 5832 int err; 5833 5834 err = mipi_dsi_detach(dsi); 5835 if (err < 0) 5836 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5837 5838 panel_simple_remove(&dsi->dev); 5839} 5840 5841static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5842{ 5843 panel_simple_shutdown(&dsi->dev); 5844} 5845 5846static struct mipi_dsi_driver panel_simple_dsi_driver = { 5847 .driver = { 5848 .name = "panel-simple-dsi", 5849 .of_match_table = dsi_of_match, 5850 .pm = &panel_simple_pm_ops, 5851 }, 5852 .probe = panel_simple_dsi_probe, 5853 .remove = panel_simple_dsi_remove, 5854 .shutdown = panel_simple_dsi_shutdown, 5855}; 5856 5857static int __init panel_simple_init(void) 5858{ 5859 int err; 5860 5861 err = platform_driver_register(&panel_simple_platform_driver); 5862 if (err < 0) 5863 return err; 5864 5865 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5866 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5867 if (err < 0) 5868 goto err_did_platform_register; 5869 } 5870 5871 return 0; 5872 5873err_did_platform_register: 5874 platform_driver_unregister(&panel_simple_platform_driver); 5875 5876 return err; 5877} 5878module_init(panel_simple_init); 5879 5880static void __exit panel_simple_exit(void) 5881{ 5882 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5883 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5884 5885 platform_driver_unregister(&panel_simple_platform_driver); 5886} 5887module_exit(panel_simple_exit); 5888 5889MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5890MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5891MODULE_LICENSE("GPL and additional rights");
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