omap_drv.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  4 * Author: Rob Clark <rob@ti.com>
  5 */
  6
  7#include <linux/dma-mapping.h>
  8#include <linux/platform_device.h>
  9#include <linux/of.h>
 10#include <linux/sort.h>
 11#include <linux/sys_soc.h>
 12
 13#include <drm/drm_atomic.h>
 14#include <drm/drm_atomic_helper.h>
 15#include <drm/drm_bridge.h>
 16#include <drm/drm_bridge_connector.h>
 17#include <drm/drm_drv.h>
 18#include <drm/drm_file.h>
 19#include <drm/drm_ioctl.h>
 20#include <drm/drm_panel.h>
 21#include <drm/drm_prime.h>
 22#include <drm/drm_print.h>
 23#include <drm/drm_probe_helper.h>
 24#include <drm/drm_vblank.h>
 25
 26#include "omap_dmm_tiler.h"
 27#include "omap_drv.h"
 28#include "omap_fbdev.h"
 29
 30#define DRIVER_NAME		MODULE_NAME
 31#define DRIVER_DESC		"OMAP DRM"
 32#define DRIVER_MAJOR		1
 33#define DRIVER_MINOR		0
 34#define DRIVER_PATCHLEVEL	0
 35
 36/*
 37 * mode config funcs
 38 */
 39
 40/* Notes about mapping DSS and DRM entities:
 41 *    CRTC:        overlay
 42 *    encoder:     manager.. with some extension to allow one primary CRTC
 43 *                 and zero or more video CRTC's to be mapped to one encoder?
 44 *    connector:   dssdev.. manager can be attached/detached from different
 45 *                 devices
 46 */
 47
 48static void omap_atomic_wait_for_completion(struct drm_device *dev,
 49					    struct drm_atomic_state *old_state)
 50{
 51	struct drm_crtc_state *new_crtc_state;
 52	struct drm_crtc *crtc;
 53	unsigned int i;
 54	int ret;
 55
 56	for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
 57		if (!new_crtc_state->active)
 58			continue;
 59
 60		ret = omap_crtc_wait_pending(crtc);
 61
 62		if (!ret)
 63			dev_warn(dev->dev,
 64				 "atomic complete timeout (pipe %u)!\n", i);
 65	}
 66}
 67
 68static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
 69{
 70	struct drm_device *dev = old_state->dev;
 71	struct omap_drm_private *priv = dev->dev_private;
 72
 73	dispc_runtime_get(priv->dispc);
 74
 75	/* Apply the atomic update. */
 76	drm_atomic_helper_commit_modeset_disables(dev, old_state);
 77
 78	if (priv->omaprev != 0x3430) {
 79		/* With the current dss dispc implementation we have to enable
 80		 * the new modeset before we can commit planes. The dispc ovl
 81		 * configuration relies on the video mode configuration been
 82		 * written into the HW when the ovl configuration is
 83		 * calculated.
 84		 *
 85		 * This approach is not ideal because after a mode change the
 86		 * plane update is executed only after the first vblank
 87		 * interrupt. The dispc implementation should be fixed so that
 88		 * it is able use uncommitted drm state information.
 89		 */
 90		drm_atomic_helper_commit_modeset_enables(dev, old_state);
 91		omap_atomic_wait_for_completion(dev, old_state);
 92
 93		drm_atomic_helper_commit_planes(dev, old_state, 0);
 94
 95		drm_atomic_helper_commit_hw_done(old_state);
 96	} else {
 97		/*
 98		 * OMAP3 DSS seems to have issues with the work-around above,
 99		 * resulting in endless sync losts if a crtc is enabled without
100		 * a plane. For now, skip the WA for OMAP3.
101		 */
102		drm_atomic_helper_commit_planes(dev, old_state, 0);
103
104		drm_atomic_helper_commit_modeset_enables(dev, old_state);
105
106		drm_atomic_helper_commit_hw_done(old_state);
107	}
108
109	/*
110	 * Wait for completion of the page flips to ensure that old buffers
111	 * can't be touched by the hardware anymore before cleaning up planes.
112	 */
113	omap_atomic_wait_for_completion(dev, old_state);
114
115	drm_atomic_helper_cleanup_planes(dev, old_state);
116
117	dispc_runtime_put(priv->dispc);
118}
119
120static int drm_atomic_state_normalized_zpos_cmp(const void *a, const void *b)
121{
122	const struct drm_plane_state *sa = *(struct drm_plane_state **)a;
123	const struct drm_plane_state *sb = *(struct drm_plane_state **)b;
124
125	if (sa->normalized_zpos != sb->normalized_zpos)
126		return sa->normalized_zpos - sb->normalized_zpos;
127	else
128		return sa->plane->base.id - sb->plane->base.id;
129}
130
131/*
132 * This replaces the drm_atomic_normalize_zpos to handle the dual overlay case.
133 *
134 * Since both halves need to be 'appear' side by side the zpos is
135 * recalculated when dealing with dual overlay cases so that the other
136 * planes zpos is consistent.
137 */
138static int omap_atomic_update_normalize_zpos(struct drm_device *dev,
139					     struct drm_atomic_state *state)
140{
141	struct drm_crtc *crtc;
142	struct drm_crtc_state *old_state, *new_state;
143	struct drm_plane *plane;
144	int c, i, n, inc;
145	int total_planes = dev->mode_config.num_total_plane;
146	struct drm_plane_state **states;
147	int ret = 0;
148
149	states = kmalloc_array(total_planes, sizeof(*states), GFP_KERNEL);
150	if (!states)
151		return -ENOMEM;
152
153	for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, c) {
154		if (old_state->plane_mask == new_state->plane_mask &&
155		    !new_state->zpos_changed)
156			continue;
157
158		/* Reset plane increment and index value for every crtc */
159		n = 0;
160
161		/*
162		 * Normalization process might create new states for planes
163		 * which normalized_zpos has to be recalculated.
164		 */
165		drm_for_each_plane_mask(plane, dev, new_state->plane_mask) {
166			struct drm_plane_state *plane_state =
167				drm_atomic_get_plane_state(new_state->state,
168							   plane);
169			if (IS_ERR(plane_state)) {
170				ret = PTR_ERR(plane_state);
171				goto done;
172			}
173			states[n++] = plane_state;
174		}
175
176		sort(states, n, sizeof(*states),
177		     drm_atomic_state_normalized_zpos_cmp, NULL);
178
179		for (i = 0, inc = 0; i < n; i++) {
180			plane = states[i]->plane;
181
182			states[i]->normalized_zpos = i + inc;
183			DRM_DEBUG_ATOMIC("[PLANE:%d:%s] updated normalized zpos value %d\n",
184					 plane->base.id, plane->name,
185					 states[i]->normalized_zpos);
186
187			if (is_omap_plane_dual_overlay(states[i]))
188				inc++;
189		}
190		new_state->zpos_changed = true;
191	}
192
193done:
194	kfree(states);
195	return ret;
196}
197
198static int omap_atomic_check(struct drm_device *dev,
199			     struct drm_atomic_state *state)
200{
201	int ret;
202
203	ret = drm_atomic_helper_check(dev, state);
204	if (ret)
205		return ret;
206
207	if (dev->mode_config.normalize_zpos) {
208		ret = omap_atomic_update_normalize_zpos(dev, state);
209		if (ret)
210			return ret;
211	}
212
213	return 0;
214}
215
216static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
217	.atomic_commit_tail = omap_atomic_commit_tail,
218};
219
220static const struct drm_mode_config_funcs omap_mode_config_funcs = {
221	.fb_create = omap_framebuffer_create,
222	.atomic_check = omap_atomic_check,
223	.atomic_commit = drm_atomic_helper_commit,
224};
225
226/* Global/shared object state funcs */
227
228/*
229 * This is a helper that returns the private state currently in operation.
230 * Note that this would return the "old_state" if called in the atomic check
231 * path, and the "new_state" after the atomic swap has been done.
232 */
233struct omap_global_state *
234omap_get_existing_global_state(struct omap_drm_private *priv)
235{
236	return to_omap_global_state(priv->glob_obj.state);
237}
238
239/*
240 * This acquires the modeset lock set aside for global state, creates
241 * a new duplicated private object state.
242 */
243struct omap_global_state *__must_check
244omap_get_global_state(struct drm_atomic_state *s)
245{
246	struct omap_drm_private *priv = s->dev->dev_private;
247	struct drm_private_state *priv_state;
248
249	priv_state = drm_atomic_get_private_obj_state(s, &priv->glob_obj);
250	if (IS_ERR(priv_state))
251		return ERR_CAST(priv_state);
252
253	return to_omap_global_state(priv_state);
254}
255
256static struct drm_private_state *
257omap_global_duplicate_state(struct drm_private_obj *obj)
258{
259	struct omap_global_state *state;
260
261	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
262	if (!state)
263		return NULL;
264
265	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
266
267	return &state->base;
268}
269
270static void omap_global_destroy_state(struct drm_private_obj *obj,
271				      struct drm_private_state *state)
272{
273	struct omap_global_state *omap_state = to_omap_global_state(state);
274
275	kfree(omap_state);
276}
277
278static const struct drm_private_state_funcs omap_global_state_funcs = {
279	.atomic_duplicate_state = omap_global_duplicate_state,
280	.atomic_destroy_state = omap_global_destroy_state,
281};
282
283static int omap_global_obj_init(struct drm_device *dev)
284{
285	struct omap_drm_private *priv = dev->dev_private;
286	struct omap_global_state *state;
287
288	state = kzalloc(sizeof(*state), GFP_KERNEL);
289	if (!state)
290		return -ENOMEM;
291
292	drm_atomic_private_obj_init(dev, &priv->glob_obj, &state->base,
293				    &omap_global_state_funcs);
294	return 0;
295}
296
297static void omap_global_obj_fini(struct omap_drm_private *priv)
298{
299	drm_atomic_private_obj_fini(&priv->glob_obj);
300}
301
302static void omap_disconnect_pipelines(struct drm_device *ddev)
303{
304	struct omap_drm_private *priv = ddev->dev_private;
305	unsigned int i;
306
307	for (i = 0; i < priv->num_pipes; i++) {
308		struct omap_drm_pipeline *pipe = &priv->pipes[i];
309
310		omapdss_device_disconnect(priv->dss, pipe->output);
311
312		omapdss_device_put(pipe->output);
313		pipe->output = NULL;
314	}
315
316	memset(&priv->channels, 0, sizeof(priv->channels));
317
318	priv->num_pipes = 0;
319}
320
321static int omap_connect_pipelines(struct drm_device *ddev)
322{
323	struct omap_drm_private *priv = ddev->dev_private;
324	struct omap_dss_device *output = NULL;
325	int r;
326
327	for_each_dss_output(output) {
328		r = omapdss_device_connect(priv->dss, output);
329		if (r == -EPROBE_DEFER) {
330			omapdss_device_put(output);
331			return r;
332		} else if (r) {
333			dev_warn(output->dev, "could not connect output %s\n",
334				 output->name);
335		} else {
336			struct omap_drm_pipeline *pipe;
337
338			pipe = &priv->pipes[priv->num_pipes++];
339			pipe->output = omapdss_device_get(output);
340
341			if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
342				/* To balance the 'for_each_dss_output' loop */
343				omapdss_device_put(output);
344				break;
345			}
346		}
347	}
348
349	return 0;
350}
351
352static int omap_compare_pipelines(const void *a, const void *b)
353{
354	const struct omap_drm_pipeline *pipe1 = a;
355	const struct omap_drm_pipeline *pipe2 = b;
356
357	if (pipe1->alias_id > pipe2->alias_id)
358		return 1;
359	else if (pipe1->alias_id < pipe2->alias_id)
360		return -1;
361	return 0;
362}
363
364static int omap_modeset_init_properties(struct drm_device *dev)
365{
366	struct omap_drm_private *priv = dev->dev_private;
367	unsigned int num_planes = dispc_get_num_ovls(priv->dispc);
368
369	priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
370						      num_planes - 1);
371	if (!priv->zorder_prop)
372		return -ENOMEM;
373
374	return 0;
375}
376
377static int omap_display_id(struct omap_dss_device *output)
378{
379	struct device_node *node = NULL;
380
381	if (output->bridge) {
382		struct drm_bridge *bridge __free(drm_bridge_put) =
383			drm_bridge_chain_get_last_bridge(output->bridge->encoder);
384
385		node = bridge->of_node;
386	}
387
388	return node ? of_alias_get_id(node, "display") : -ENODEV;
389}
390
391static int omap_modeset_init(struct drm_device *dev)
392{
393	struct omap_drm_private *priv = dev->dev_private;
394	int num_ovls = dispc_get_num_ovls(priv->dispc);
395	int num_mgrs = dispc_get_num_mgrs(priv->dispc);
396	unsigned int i;
397	int ret;
398	u32 plane_crtc_mask;
399
400	if (!omapdss_stack_is_ready())
401		return -EPROBE_DEFER;
402
403	ret = omap_modeset_init_properties(dev);
404	if (ret < 0)
405		return ret;
406
407	/*
408	 * This function creates exactly one connector, encoder, crtc,
409	 * and primary plane per each connected dss-device. Each
410	 * connector->encoder->crtc chain is expected to be separate
411	 * and each crtc is connect to a single dss-channel. If the
412	 * configuration does not match the expectations or exceeds
413	 * the available resources, the configuration is rejected.
414	 */
415	ret = omap_connect_pipelines(dev);
416	if (ret < 0)
417		return ret;
418
419	if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
420		dev_err(dev->dev, "%s(): Too many connected displays\n",
421			__func__);
422		return -EINVAL;
423	}
424
425	/* Create all planes first. They can all be put to any CRTC. */
426	plane_crtc_mask = (1 << priv->num_pipes) - 1;
427
428	for (i = 0; i < num_ovls; i++) {
429		enum drm_plane_type type = i < priv->num_pipes
430					 ? DRM_PLANE_TYPE_PRIMARY
431					 : DRM_PLANE_TYPE_OVERLAY;
432		struct drm_plane *plane;
433
434		if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
435			return -EINVAL;
436
437		plane = omap_plane_init(dev, i, type, plane_crtc_mask);
438		if (IS_ERR(plane))
439			return PTR_ERR(plane);
440
441		priv->planes[priv->num_planes++] = plane;
442	}
443
444	/*
445	 * Create the encoders, attach the bridges and get the pipeline alias
446	 * IDs.
447	 */
448	for (i = 0; i < priv->num_pipes; i++) {
449		struct omap_drm_pipeline *pipe = &priv->pipes[i];
450		int id;
451
452		pipe->encoder = omap_encoder_init(dev, pipe->output);
453		if (!pipe->encoder)
454			return -ENOMEM;
455
456		if (pipe->output->bridge) {
457			ret = drm_bridge_attach(pipe->encoder,
458						pipe->output->bridge, NULL,
459						DRM_BRIDGE_ATTACH_NO_CONNECTOR);
460			if (ret < 0)
461				return ret;
462		}
463
464		id = omap_display_id(pipe->output);
465		pipe->alias_id = id >= 0 ? id : i;
466	}
467
468	/* Sort the pipelines by DT aliases. */
469	sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
470	     omap_compare_pipelines, NULL);
471
472	/*
473	 * Populate the pipeline lookup table by DISPC channel. Only one display
474	 * is allowed per channel.
475	 */
476	for (i = 0; i < priv->num_pipes; ++i) {
477		struct omap_drm_pipeline *pipe = &priv->pipes[i];
478		enum omap_channel channel = pipe->output->dispc_channel;
479
480		if (WARN_ON(priv->channels[channel] != NULL))
481			return -EINVAL;
482
483		priv->channels[channel] = pipe;
484	}
485
486	/* Create the connectors and CRTCs. */
487	for (i = 0; i < priv->num_pipes; i++) {
488		struct omap_drm_pipeline *pipe = &priv->pipes[i];
489		struct drm_encoder *encoder = pipe->encoder;
490		struct drm_crtc *crtc;
491
492		pipe->connector = drm_bridge_connector_init(dev, encoder);
493		if (IS_ERR(pipe->connector)) {
494			dev_err(priv->dev,
495				"unable to create bridge connector for %s\n",
496				pipe->output->name);
497			return PTR_ERR(pipe->connector);
498		}
499
500		drm_connector_attach_encoder(pipe->connector, encoder);
501
502		crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
503		if (IS_ERR(crtc))
504			return PTR_ERR(crtc);
505
506		encoder->possible_crtcs = 1 << i;
507		pipe->crtc = crtc;
508	}
509
510	DBG("registered %u planes, %u crtcs/encoders/connectors\n",
511	    priv->num_planes, priv->num_pipes);
512
513	dev->mode_config.min_width = 8;
514	dev->mode_config.min_height = 2;
515
516	/*
517	 * Note: these values are used for multiple independent things:
518	 * connector mode filtering, buffer sizes, crtc sizes...
519	 * Use big enough values here to cover all use cases, and do more
520	 * specific checking in the respective code paths.
521	 */
522	dev->mode_config.max_width = 8192;
523	dev->mode_config.max_height = 8192;
524
525	/* We want the zpos to be normalized */
526	dev->mode_config.normalize_zpos = true;
527
528	dev->mode_config.funcs = &omap_mode_config_funcs;
529	dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
530
531	drm_mode_config_reset(dev);
532
533	omap_drm_irq_install(dev);
534
535	return 0;
536}
537
538static void omap_modeset_fini(struct drm_device *ddev)
539{
540	omap_drm_irq_uninstall(ddev);
541
542	drm_mode_config_cleanup(ddev);
543}
544
545/*
546 * drm ioctl funcs
547 */
548
549
550static int ioctl_get_param(struct drm_device *dev, void *data,
551		struct drm_file *file_priv)
552{
553	struct omap_drm_private *priv = dev->dev_private;
554	struct drm_omap_param *args = data;
555
556	DBG("%p: param=%llu", dev, args->param);
557
558	switch (args->param) {
559	case OMAP_PARAM_CHIPSET_ID:
560		args->value = priv->omaprev;
561		break;
562	default:
563		DBG("unknown parameter %lld", args->param);
564		return -EINVAL;
565	}
566
567	return 0;
568}
569
570#define OMAP_BO_USER_MASK	0x00ffffff	/* flags settable by userspace */
571
572static int ioctl_gem_new(struct drm_device *dev, void *data,
573		struct drm_file *file_priv)
574{
575	struct drm_omap_gem_new *args = data;
576	u32 flags = args->flags & OMAP_BO_USER_MASK;
577
578	VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
579	     args->size.bytes, flags);
580
581	return omap_gem_new_handle(dev, file_priv, args->size, flags,
582				   &args->handle);
583}
584
585static int ioctl_gem_info(struct drm_device *dev, void *data,
586		struct drm_file *file_priv)
587{
588	struct drm_omap_gem_info *args = data;
589	struct drm_gem_object *obj;
590	int ret = 0;
591
592	VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
593
594	obj = drm_gem_object_lookup(file_priv, args->handle);
595	if (!obj)
596		return -ENOENT;
597
598	args->size = omap_gem_mmap_size(obj);
599	args->offset = omap_gem_mmap_offset(obj);
600
601	drm_gem_object_put(obj);
602
603	return ret;
604}
605
606static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
607	DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
608			  DRM_RENDER_ALLOW),
609	DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
610			  DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
611	DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
612			  DRM_RENDER_ALLOW),
613	/* Deprecated, to be removed. */
614	DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
615			  DRM_RENDER_ALLOW),
616	/* Deprecated, to be removed. */
617	DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
618			  DRM_RENDER_ALLOW),
619	DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
620			  DRM_RENDER_ALLOW),
621};
622
623/*
624 * drm driver funcs
625 */
626
627static int dev_open(struct drm_device *dev, struct drm_file *file)
628{
629	file->driver_priv = NULL;
630
631	DBG("open: dev=%p, file=%p", dev, file);
632
633	return 0;
634}
635
636DEFINE_DRM_GEM_FOPS(omapdriver_fops);
637
638static const struct drm_driver omap_drm_driver = {
639	.driver_features = DRIVER_MODESET | DRIVER_GEM  |
640		DRIVER_ATOMIC | DRIVER_RENDER,
641	.open = dev_open,
642#ifdef CONFIG_DEBUG_FS
643	.debugfs_init = omap_debugfs_init,
644#endif
645	.gem_prime_import = omap_gem_prime_import,
646	.dumb_create = omap_gem_dumb_create,
647	.dumb_map_offset = omap_gem_dumb_map_offset,
648	OMAP_FBDEV_DRIVER_OPS,
649	.ioctls = ioctls,
650	.num_ioctls = DRM_OMAP_NUM_IOCTLS,
651	.fops = &omapdriver_fops,
652	.name = DRIVER_NAME,
653	.desc = DRIVER_DESC,
654	.major = DRIVER_MAJOR,
655	.minor = DRIVER_MINOR,
656	.patchlevel = DRIVER_PATCHLEVEL,
657};
658
659static const struct soc_device_attribute omapdrm_soc_devices[] = {
660	{ .family = "OMAP3", .data = (void *)0x3430 },
661	{ .family = "OMAP4", .data = (void *)0x4430 },
662	{ .family = "OMAP5", .data = (void *)0x5430 },
663	{ .family = "DRA7",  .data = (void *)0x0752 },
664	{ /* sentinel */ }
665};
666
667static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
668{
669	const struct soc_device_attribute *soc;
670	struct dss_pdata *pdata = dev->platform_data;
671	struct drm_device *ddev;
672	int ret;
673
674	DBG("%s", dev_name(dev));
675
676	if (drm_firmware_drivers_only())
677		return -ENODEV;
678
679	/* Allocate and initialize the DRM device. */
680	ddev = drm_dev_alloc(&omap_drm_driver, dev);
681	if (IS_ERR(ddev))
682		return PTR_ERR(ddev);
683
684	priv->ddev = ddev;
685	ddev->dev_private = priv;
686
687	priv->dev = dev;
688	priv->dss = pdata->dss;
689	priv->dispc = dispc_get_dispc(priv->dss);
690
691	priv->dss->mgr_ops_priv = priv;
692
693	soc = soc_device_match(omapdrm_soc_devices);
694	priv->omaprev = soc ? (uintptr_t)soc->data : 0;
695	priv->wq = alloc_ordered_workqueue("omapdrm", 0);
696	if (!priv->wq) {
697		ret = -ENOMEM;
698		goto err_alloc_workqueue;
699	}
700
701	mutex_init(&priv->list_lock);
702	INIT_LIST_HEAD(&priv->obj_list);
703
704	/* Get memory bandwidth limits */
705	priv->max_bandwidth = dispc_get_memory_bandwidth_limit(priv->dispc);
706
707	omap_gem_init(ddev);
708
709	drm_mode_config_init(ddev);
710
711	ret = omap_global_obj_init(ddev);
712	if (ret)
713		goto err_gem_deinit;
714
715	ret = omap_hwoverlays_init(priv);
716	if (ret)
717		goto err_free_priv_obj;
718
719	ret = omap_modeset_init(ddev);
720	if (ret) {
721		dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
722		goto err_free_overlays;
723	}
724
725	/* Initialize vblank handling, start with all CRTCs disabled. */
726	ret = drm_vblank_init(ddev, priv->num_pipes);
727	if (ret) {
728		dev_err(priv->dev, "could not init vblank\n");
729		goto err_cleanup_modeset;
730	}
731
732	drm_kms_helper_poll_init(ddev);
733
734	/*
735	 * Register the DRM device with the core and the connectors with
736	 * sysfs.
737	 */
738	ret = drm_dev_register(ddev, 0);
739	if (ret)
740		goto err_cleanup_helpers;
741
742	omap_fbdev_setup(ddev);
743
744	return 0;
745
746err_cleanup_helpers:
747	drm_kms_helper_poll_fini(ddev);
748err_cleanup_modeset:
749	omap_modeset_fini(ddev);
750err_free_overlays:
751	omap_hwoverlays_destroy(priv);
752err_free_priv_obj:
753	omap_global_obj_fini(priv);
754err_gem_deinit:
755	drm_mode_config_cleanup(ddev);
756	omap_gem_deinit(ddev);
757	destroy_workqueue(priv->wq);
758err_alloc_workqueue:
759	omap_disconnect_pipelines(ddev);
760	drm_dev_put(ddev);
761	return ret;
762}
763
764static void omapdrm_cleanup(struct omap_drm_private *priv)
765{
766	struct drm_device *ddev = priv->ddev;
767
768	DBG("");
769
770	drm_dev_unregister(ddev);
771
772	drm_kms_helper_poll_fini(ddev);
773
774	drm_atomic_helper_shutdown(ddev);
775
776	omap_modeset_fini(ddev);
777	omap_hwoverlays_destroy(priv);
778	omap_global_obj_fini(priv);
779	drm_mode_config_cleanup(ddev);
780	omap_gem_deinit(ddev);
781
782	destroy_workqueue(priv->wq);
783
784	omap_disconnect_pipelines(ddev);
785
786	drm_dev_put(ddev);
787}
788
789static int pdev_probe(struct platform_device *pdev)
790{
791	struct omap_drm_private *priv;
792	int ret;
793
794	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
795	if (ret) {
796		dev_err(&pdev->dev, "Failed to set the DMA mask\n");
797		return ret;
798	}
799
800	/* Allocate and initialize the driver private structure. */
801	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
802	if (!priv)
803		return -ENOMEM;
804
805	platform_set_drvdata(pdev, priv);
806
807	ret = omapdrm_init(priv, &pdev->dev);
808	if (ret < 0)
809		kfree(priv);
810
811	return ret;
812}
813
814static void pdev_remove(struct platform_device *pdev)
815{
816	struct omap_drm_private *priv = platform_get_drvdata(pdev);
817
818	omapdrm_cleanup(priv);
819	kfree(priv);
820}
821
822static void pdev_shutdown(struct platform_device *pdev)
823{
824	struct omap_drm_private *priv = platform_get_drvdata(pdev);
825
826	drm_atomic_helper_shutdown(priv->ddev);
827}
828
829#ifdef CONFIG_PM_SLEEP
830static int omap_drm_suspend(struct device *dev)
831{
832	struct omap_drm_private *priv = dev_get_drvdata(dev);
833	struct drm_device *drm_dev = priv->ddev;
834
835	return drm_mode_config_helper_suspend(drm_dev);
836}
837
838static int omap_drm_resume(struct device *dev)
839{
840	struct omap_drm_private *priv = dev_get_drvdata(dev);
841	struct drm_device *drm_dev = priv->ddev;
842
843	drm_mode_config_helper_resume(drm_dev);
844
845	return omap_gem_resume(drm_dev);
846}
847#endif
848
849static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
850
851static struct platform_driver pdev = {
852	.driver = {
853		.name = "omapdrm",
854		.pm = &omapdrm_pm_ops,
855	},
856	.probe = pdev_probe,
857	.remove = pdev_remove,
858	.shutdown = pdev_shutdown,
859};
860
861static struct platform_driver * const drivers[] = {
862	&omap_dmm_driver,
863	&pdev,
864};
865
866static int __init omap_drm_init(void)
867{
868	int r;
869
870	DBG("init");
871
872	r = omap_dss_init();
873	if (r)
874		return r;
875
876	r = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
877	if (r) {
878		omap_dss_exit();
879		return r;
880	}
881
882	return 0;
883}
884
885static void __exit omap_drm_fini(void)
886{
887	DBG("fini");
888
889	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
890
891	omap_dss_exit();
892}
893
894module_init(omap_drm_init);
895module_exit(omap_drm_fini);
896
897MODULE_AUTHOR("Rob Clark <rob@ti.com>");
898MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ti.com>");
899MODULE_DESCRIPTION("OMAP DRM Display Driver");
900MODULE_ALIAS("platform:" DRIVER_NAME);
901MODULE_LICENSE("GPL v2");