sdi.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2009 Nokia Corporation
  4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  5 */
  6
  7#define DSS_SUBSYS_NAME "SDI"
  8
  9#include <linux/delay.h>
 10#include <linux/err.h>
 11#include <linux/export.h>
 12#include <linux/kernel.h>
 13#include <linux/of.h>
 14#include <linux/of_graph.h>
 15#include <linux/platform_device.h>
 16#include <linux/regulator/consumer.h>
 17#include <linux/string.h>
 18
 19#include <drm/drm_bridge.h>
 20
 21#include "dss.h"
 22#include "omapdss.h"
 23
 24struct sdi_device {
 25	struct platform_device *pdev;
 26	struct dss_device *dss;
 27
 28	bool update_enabled;
 29	struct regulator *vdds_sdi_reg;
 30
 31	struct dss_lcd_mgr_config mgr_config;
 32	unsigned long pixelclock;
 33	int datapairs;
 34
 35	struct omap_dss_device output;
 36	struct drm_bridge bridge;
 37};
 38
 39#define drm_bridge_to_sdi(bridge) \
 40	container_of(bridge, struct sdi_device, bridge)
 41
 42struct sdi_clk_calc_ctx {
 43	struct sdi_device *sdi;
 44	unsigned long pck_min, pck_max;
 45
 46	unsigned long fck;
 47	struct dispc_clock_info dispc_cinfo;
 48};
 49
 50static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
 51		unsigned long pck, void *data)
 52{
 53	struct sdi_clk_calc_ctx *ctx = data;
 54
 55	ctx->dispc_cinfo.lck_div = lckd;
 56	ctx->dispc_cinfo.pck_div = pckd;
 57	ctx->dispc_cinfo.lck = lck;
 58	ctx->dispc_cinfo.pck = pck;
 59
 60	return true;
 61}
 62
 63static bool dpi_calc_dss_cb(unsigned long fck, void *data)
 64{
 65	struct sdi_clk_calc_ctx *ctx = data;
 66
 67	ctx->fck = fck;
 68
 69	return dispc_div_calc(ctx->sdi->dss->dispc, fck,
 70			      ctx->pck_min, ctx->pck_max,
 71			      dpi_calc_dispc_cb, ctx);
 72}
 73
 74static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
 75			      unsigned long *fck,
 76			      struct dispc_clock_info *dispc_cinfo)
 77{
 78	int i;
 79	struct sdi_clk_calc_ctx ctx;
 80
 81	/*
 82	 * DSS fclk gives us very few possibilities, so finding a good pixel
 83	 * clock may not be possible. We try multiple times to find the clock,
 84	 * each time widening the pixel clock range we look for, up to
 85	 * +/- 1MHz.
 86	 */
 87
 88	for (i = 0; i < 10; ++i) {
 89		bool ok;
 90
 91		memset(&ctx, 0, sizeof(ctx));
 92
 93		ctx.sdi = sdi;
 94
 95		if (pclk > 1000 * i * i * i)
 96			ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
 97		else
 98			ctx.pck_min = 0;
 99		ctx.pck_max = pclk + 1000 * i * i * i;
100
101		ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
102				  dpi_calc_dss_cb, &ctx);
103		if (ok) {
104			*fck = ctx.fck;
105			*dispc_cinfo = ctx.dispc_cinfo;
106			return 0;
107		}
108	}
109
110	return -EINVAL;
111}
112
113static void sdi_config_lcd_manager(struct sdi_device *sdi)
114{
115	sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
116
117	sdi->mgr_config.stallmode = false;
118	sdi->mgr_config.fifohandcheck = false;
119
120	sdi->mgr_config.video_port_width = 24;
121	sdi->mgr_config.lcden_sig_polarity = 1;
122
123	dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
124}
125
126/* -----------------------------------------------------------------------------
127 * DRM Bridge Operations
128 */
129
130static int sdi_bridge_attach(struct drm_bridge *bridge,
131			     struct drm_encoder *encoder,
132			     enum drm_bridge_attach_flags flags)
133{
134	struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
135
136	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
137		return -EINVAL;
138
139	return drm_bridge_attach(encoder, sdi->output.next_bridge,
140				 bridge, flags);
141}
142
143static enum drm_mode_status
144sdi_bridge_mode_valid(struct drm_bridge *bridge,
145		      const struct drm_display_info *info,
146		      const struct drm_display_mode *mode)
147{
148	struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
149	unsigned long pixelclock = mode->clock * 1000;
150	struct dispc_clock_info dispc_cinfo;
151	unsigned long fck;
152	int ret;
153
154	if (pixelclock == 0)
155		return MODE_NOCLOCK;
156
157	ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo);
158	if (ret < 0)
159		return MODE_CLOCK_RANGE;
160
161	return MODE_OK;
162}
163
164static bool sdi_bridge_mode_fixup(struct drm_bridge *bridge,
165				  const struct drm_display_mode *mode,
166				  struct drm_display_mode *adjusted_mode)
167{
168	struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
169	unsigned long pixelclock = mode->clock * 1000;
170	struct dispc_clock_info dispc_cinfo;
171	unsigned long fck;
172	unsigned long pck;
173	int ret;
174
175	ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo);
176	if (ret < 0)
177		return false;
178
179	pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
180
181	if (pck != pixelclock)
182		dev_dbg(&sdi->pdev->dev,
183			"pixel clock adjusted from %lu Hz to %lu Hz\n",
184			pixelclock, pck);
185
186	adjusted_mode->clock = pck / 1000;
187
188	return true;
189}
190
191static void sdi_bridge_mode_set(struct drm_bridge *bridge,
192				const struct drm_display_mode *mode,
193				const struct drm_display_mode *adjusted_mode)
194{
195	struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
196
197	sdi->pixelclock = adjusted_mode->clock * 1000;
198}
199
200static void sdi_bridge_enable(struct drm_bridge *bridge)
201{
202	struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
203	struct dispc_clock_info dispc_cinfo;
204	unsigned long fck;
205	int r;
206
207	r = regulator_enable(sdi->vdds_sdi_reg);
208	if (r)
209		return;
210
211	r = dispc_runtime_get(sdi->dss->dispc);
212	if (r)
213		goto err_get_dispc;
214
215	r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo);
216	if (r)
217		goto err_calc_clock_div;
218
219	sdi->mgr_config.clock_info = dispc_cinfo;
220
221	r = dss_set_fck_rate(sdi->dss, fck);
222	if (r)
223		goto err_set_dss_clock_div;
224
225	sdi_config_lcd_manager(sdi);
226
227	/*
228	 * LCLK and PCLK divisors are located in shadow registers, and we
229	 * normally write them to DISPC registers when enabling the output.
230	 * However, SDI uses pck-free as source clock for its PLL, and pck-free
231	 * is affected by the divisors. And as we need the PLL before enabling
232	 * the output, we need to write the divisors early.
233	 *
234	 * It seems just writing to the DISPC register is enough, and we don't
235	 * need to care about the shadow register mechanism for pck-free. The
236	 * exact reason for this is unknown.
237	 */
238	dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
239				&sdi->mgr_config.clock_info);
240
241	dss_sdi_init(sdi->dss, sdi->datapairs);
242	r = dss_sdi_enable(sdi->dss);
243	if (r)
244		goto err_sdi_enable;
245	mdelay(2);
246
247	r = dss_mgr_enable(&sdi->output);
248	if (r)
249		goto err_mgr_enable;
250
251	return;
252
253err_mgr_enable:
254	dss_sdi_disable(sdi->dss);
255err_sdi_enable:
256err_set_dss_clock_div:
257err_calc_clock_div:
258	dispc_runtime_put(sdi->dss->dispc);
259err_get_dispc:
260	regulator_disable(sdi->vdds_sdi_reg);
261}
262
263static void sdi_bridge_disable(struct drm_bridge *bridge)
264{
265	struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
266
267	dss_mgr_disable(&sdi->output);
268
269	dss_sdi_disable(sdi->dss);
270
271	dispc_runtime_put(sdi->dss->dispc);
272
273	regulator_disable(sdi->vdds_sdi_reg);
274}
275
276static const struct drm_bridge_funcs sdi_bridge_funcs = {
277	.attach = sdi_bridge_attach,
278	.mode_valid = sdi_bridge_mode_valid,
279	.mode_fixup = sdi_bridge_mode_fixup,
280	.mode_set = sdi_bridge_mode_set,
281	.enable = sdi_bridge_enable,
282	.disable = sdi_bridge_disable,
283};
284
285static void sdi_bridge_init(struct sdi_device *sdi)
286{
287	sdi->bridge.of_node = sdi->pdev->dev.of_node;
288	sdi->bridge.type = DRM_MODE_CONNECTOR_LVDS;
289
290	drm_bridge_add(&sdi->bridge);
291}
292
293static void sdi_bridge_cleanup(struct sdi_device *sdi)
294{
295	drm_bridge_remove(&sdi->bridge);
296}
297
298/* -----------------------------------------------------------------------------
299 * Initialisation and Cleanup
300 */
301
302static int sdi_init_output(struct sdi_device *sdi)
303{
304	struct omap_dss_device *out = &sdi->output;
305	int r;
306
307	sdi_bridge_init(sdi);
308
309	out->dev = &sdi->pdev->dev;
310	out->id = OMAP_DSS_OUTPUT_SDI;
311	out->type = OMAP_DISPLAY_TYPE_SDI;
312	out->name = "sdi.0";
313	out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
314	/* We have SDI only on OMAP3, where it's on port 1 */
315	out->of_port = 1;
316	out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE	/* 15.5.9.1.2 */
317		       | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE;
318
319	r = omapdss_device_init_output(out, &sdi->bridge);
320	if (r < 0) {
321		sdi_bridge_cleanup(sdi);
322		return r;
323	}
324
325	omapdss_device_register(out);
326
327	return 0;
328}
329
330static void sdi_uninit_output(struct sdi_device *sdi)
331{
332	omapdss_device_unregister(&sdi->output);
333	omapdss_device_cleanup_output(&sdi->output);
334
335	sdi_bridge_cleanup(sdi);
336}
337
338int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
339		  struct device_node *port)
340{
341	struct sdi_device *sdi;
342	struct device_node *ep;
343	u32 datapairs;
344	int r;
345
346	sdi = devm_drm_bridge_alloc(&pdev->dev, struct sdi_device, bridge, &sdi_bridge_funcs);
347	if (IS_ERR(sdi))
348		return PTR_ERR(sdi);
349
350	ep = of_graph_get_next_port_endpoint(port, NULL);
351	if (!ep)
352		return 0;
353
354	r = of_property_read_u32(ep, "datapairs", &datapairs);
355	of_node_put(ep);
356	if (r) {
357		DSSERR("failed to parse datapairs\n");
358		return r;
359	}
360
361	sdi->datapairs = datapairs;
362	sdi->dss = dss;
363
364	sdi->pdev = pdev;
365	port->data = sdi;
366
367	sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi");
368	if (IS_ERR(sdi->vdds_sdi_reg)) {
369		r = PTR_ERR(sdi->vdds_sdi_reg);
370		if (r != -EPROBE_DEFER)
371			DSSERR("can't get VDDS_SDI regulator\n");
372		return r;
373	}
374
375	r = sdi_init_output(sdi);
376	if (r)
377		return r;
378
379	return 0;
380}
381
382void sdi_uninit_port(struct device_node *port)
383{
384	struct sdi_device *sdi = port->data;
385
386	if (!sdi)
387		return;
388
389	sdi_uninit_output(sdi);
390}