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host.fuc

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linux-6.19.14/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/host.fuc PLAIN TEXT
  1/*
  2 * Copyright 2013 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs
 23 */
 24
 25#ifdef INCLUDE_PROC
 26process(PROC_HOST, #host_init, #host_recv)
 27#endif
 28
 29/******************************************************************************
 30 * HOST data segment
 31 *****************************************************************************/
 32#ifdef INCLUDE_DATA
 33// HOST (R)FIFO packet format
 34.equ #fifo_process 0x00
 35.equ #fifo_message 0x04
 36.equ #fifo_data0   0x08
 37.equ #fifo_data1   0x0c
 38
 39// HOST HOST->PWR queue description
 40.equ #fifo_qlen 4 // log2(size of queue entry in bytes)
 41.equ #fifo_qnum 3 // log2(max number of entries in queue)
 42.equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue
 43.equ #fifo_qmaskp (#fifo_qmaskb - 1)
 44.equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1)
 45.equ #fifo_qsize  (1 << (#fifo_qlen + #fifo_qnum))
 46fifo_queue: .skip 128 // #fifo_qsize
 47
 48// HOST PWR->HOST queue description
 49.equ #rfifo_qlen 4 // log2(size of queue entry in bytes)
 50.equ #rfifo_qnum 3 // log2(max number of entries in queue)
 51.equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue
 52.equ #rfifo_qmaskp (#rfifo_qmaskb - 1)
 53.equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1)
 54.equ #rfifo_qsize  (1 << (#rfifo_qlen + #rfifo_qnum))
 55rfifo_queue: .skip 128 // #rfifo_qsize
 56#endif
 57
 58/******************************************************************************
 59 * HOST code segment
 60 *****************************************************************************/
 61#ifdef INCLUDE_CODE
 62// HOST->PWR comms - dequeue message(s) for process(es) from FIFO
 63//
 64// $r15 - current (host)
 65// $r0  - zero
 66host_send:
 67	nv_iord($r1, NV_PPWR_FIFO_GET(0))
 68	nv_iord($r2, NV_PPWR_FIFO_PUT(0))
 69	cmp b32 $r1 $r2
 70	bra e #host_send_done
 71		// calculate address of message
 72		and $r14 $r1 #fifo_qmaskp
 73		shl b32 $r14 $r14 #fifo_qlen
 74		add b32 $r14 #fifo_queue
 75
 76		// read message data, and pass to appropriate process
 77		ld b32 $r11 D[$r14 + #fifo_data1]
 78		ld b32 $r12 D[$r14 + #fifo_data0]
 79		ld b32 $r13 D[$r14 + #fifo_message]
 80		ld b32 $r14 D[$r14 + #fifo_process]
 81		call(send)
 82
 83		// increment GET
 84		add b32 $r1 0x1
 85		and $r14 $r1 #fifo_qmaskf
 86		nv_iowr(NV_PPWR_FIFO_GET(0), $r14)
 87		bra #host_send
 88	host_send_done:
 89	ret
 90
 91// PWR->HOST comms - enqueue message for HOST to RFIFO
 92//
 93// $r15 - current (host)
 94// $r14 - process
 95// $r13 - message
 96// $r12 - message data 0
 97// $r11 - message data 1
 98// $r0  - zero
 99host_recv:
100	// message from intr handler == HOST->PWR comms pending
101	imm32($r1, PROC_KERN)
102	cmp b32 $r14 $r1
103	bra e #host_send
104
105	// wait for space in RFIFO
106	host_recv_wait:
107	nv_iord($r1, NV_PPWR_RFIFO_GET)
108	nv_iord($r2, NV_PPWR_RFIFO_PUT)
109	xor $r1 #rfifo_qmaskb
110	cmp b32 $r1 $r2
111	bra e #host_recv_wait
112
113	and $r3 $r2 #rfifo_qmaskp
114	shl b32 $r3 #rfifo_qlen
115	add b32 $r3 #rfifo_queue
116
117	// enqueue message
118	st b32 D[$r3 + #fifo_data1] $r11
119	st b32 D[$r3 + #fifo_data0] $r12
120	st b32 D[$r3 + #fifo_message] $r13
121	st b32 D[$r3 + #fifo_process] $r14
122
123	add b32 $r2 0x1
124	and $r2 #rfifo_qmaskf
125	nv_iowr(NV_PPWR_RFIFO_PUT, $r2)
126
127	// notify host of pending message
128	mov $r2 NV_PPWR_INTR_TRIGGER_USER0
129	nv_iowr(NV_PPWR_INTR_TRIGGER, $r2)
130	ret
131
132// $r15 - current (host)
133// $r0  - zero
134host_init:
135	// store each fifo's base/size in H2D/D2H scratch regs
136	mov $r1 #fifo_qsize
137	shl b32 $r1 16
138	or $r1 #fifo_queue
139	nv_iowr(NV_PPWR_H2D, $r1);
140
141	mov $r1 #rfifo_qsize
142	shl b32 $r1 16
143	or $r1 #rfifo_queue
144	nv_iowr(NV_PPWR_D2H, $r1);
145
146	// enable fifo subintr for first fifo
147	mov $r1 1
148	nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1)
149	ret
150#endif
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