gsp.h

  1/* SPDX-License-Identifier: MIT */
  2
  3/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
  4
  5#ifndef __NVRM_GSP_H__
  6#define __NVRM_GSP_H__
  7#include <nvrm/nvtypes.h>
  8
  9/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/570.144 */
 10
 11#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U
 12
 13#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES           17U
 14
 15typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
 16
 17typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO {
 18    NV_DECLARE_ALIGNED(NvU64 base, 8);
 19    NV_DECLARE_ALIGNED(NvU64 limit, 8);
 20    NV_DECLARE_ALIGNED(NvU64 reserved, 8);
 21    NvU32                                                  performance;
 22    NvBool                                                 supportCompressed;
 23    NvBool                                                 supportISO;
 24    NvBool                                                 bProtected;
 25    NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG blackList;
 26} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO;
 27
 28typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS {
 29    NvU32 numFBRegions;
 30    NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8);
 31} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS;
 32
 33#define NV0080_CTRL_GR_CAPS_TBL_SIZE            23
 34
 35#define NV2080_GPU_MAX_GID_LENGTH             (0x000000100ULL)
 36
 37typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
 38    NvU32 index;
 39    NvU32 flags;
 40    NvU32 length;
 41    NvU8  data[NV2080_GPU_MAX_GID_LENGTH];
 42} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS;
 43
 44typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
 45    NvU32 BoardID;
 46    char  chipSKU[9];
 47    char  chipSKUMod[5];
 48    NvU32 skuConfigVersion;
 49    char  project[5];
 50    char  projectSKU[5];
 51    char  CDP[6];
 52    char  projectSKUMod[2];
 53    NvU32 businessCycle;
 54} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS;
 55
 56#define MAX_GPC_COUNT           32
 57
 58typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
 59    NvU32  totalVFs;
 60    NvU32  firstVfOffset;
 61    NvU32  vfFeatureMask;
 62    NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8);
 63    NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8);
 64    NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8);
 65    NV_DECLARE_ALIGNED(NvU64 bar0Size, 8);
 66    NV_DECLARE_ALIGNED(NvU64 bar1Size, 8);
 67    NV_DECLARE_ALIGNED(NvU64 bar2Size, 8);
 68    NvBool b64bitBar0;
 69    NvBool b64bitBar1;
 70    NvBool b64bitBar2;
 71    NvBool bSriovEnabled;
 72    NvBool bSriovHeavyEnabled;
 73    NvBool bEmulateVFBar0TlbInvalidationRegister;
 74    NvBool bClientRmAllocatedCtxBuffer;
 75    NvBool bNonPowerOf2ChannelCountSupported;
 76    NvBool bVfResizableBAR1Supported;
 77} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
 78
 79#include "engine.h"
 80
 81#define NVGPU_ENGINE_CAPS_MASK_BITS                32
 82
 83#define NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX           ((RM_ENGINE_TYPE_LAST-1)/NVGPU_ENGINE_CAPS_MASK_BITS + 1)
 84
 85#define NV2080_GPU_MAX_NAME_STRING_LENGTH                  (0x0000040U)
 86
 87typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS 
 88{
 89    NvU32 numHeads;
 90    NvU32 maxNumHeads;
 91} VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS;
 92
 93typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS 
 94{
 95    NvU32 headIndex;
 96    NvU32 maxHResolution;
 97    NvU32 maxVResolution;
 98} VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS;
 99
100#define MAX_GROUP_COUNT 2
101
102typedef struct
103{
104    NvU32 ecidLow;
105    NvU32 ecidHigh;
106    NvU32 ecidExtended;
107} EcidManufacturingInfo;
108
109typedef struct
110{
111    NvU64 nonWprHeapOffset;
112    NvU64 frtsOffset;
113} FW_WPR_LAYOUT_OFFSET;
114
115typedef struct GspStaticConfigInfo_t
116{
117    NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE];
118    NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo;
119    NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
120    NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
121
122    NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps;
123    NvU32 sriovMaxGfid;
124
125    NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
126
127    NvBool poisonFuseEnabled;
128
129    NvU64 fb_length;
130    NvU64 fbio_mask;
131    NvU32 fb_bus_width;
132    NvU32 fb_ram_type;
133    NvU64 fbp_mask;
134    NvU32 l2_cache_size;
135
136    NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
137    NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
138    NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
139    NvBool bGpuInternalSku;
140    NvBool bIsQuadroGeneric;
141    NvBool bIsQuadroAd;
142    NvBool bIsNvidiaNvs;
143    NvBool bIsVgx;
144    NvBool bGeforceSmb;
145    NvBool bIsTitan;
146    NvBool bIsTesla;
147    NvBool bIsMobile;
148    NvBool bIsGc6Rtd3Allowed;
149    NvBool bIsGc8Rtd3Allowed;
150    NvBool bIsGcOffRtd3Allowed;
151    NvBool bIsGcoffLegacyAllowed;
152    NvBool bIsMigSupported;
153
154    /* "Total Board Power" refers to power requirement of GPU,
155     * while in GC6 state. Majority of this power will be used
156     * to keep V-RAM active to preserve its content.
157     * Some energy maybe consumed by Always-on components on GPU chip.
158     * This power will be provided by 3.3v voltage rail.
159     */
160    NvU16  RTD3GC6TotalBoardPower;
161
162    /* PERST# (i.e. PCI Express Reset) is a sideband signal
163     * generated by the PCIe Host to indicate the PCIe devices,
164     * that the power-rails and the reference-clock are stable.
165     * The endpoint device typically uses this signal as a global reset.
166     */
167    NvU16  RTD3GC6PerstDelay;
168
169    NvU64 bar1PdeBase;
170    NvU64 bar2PdeBase;
171
172    NvBool bVbiosValid;
173    NvU32 vbiosSubVendor;
174    NvU32 vbiosSubDevice;
175
176    NvBool bPageRetirementSupported;
177
178    NvBool bSplitVasBetweenServerClientRm;
179
180    NvBool bClRootportNeedsNosnoopWAR;
181
182    VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
183    VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
184    NvU64 displaylessMaxPixels;
185
186    // Client handle for internal RMAPI control.
187    NvHandle hInternalClient;
188
189    // Device handle for internal RMAPI control.
190    NvHandle hInternalDevice;
191
192    // Subdevice handle for internal RMAPI control.
193    NvHandle hInternalSubdevice;
194
195    NvBool bSelfHostedMode;
196    NvBool bAtsSupported;
197
198    NvBool bIsGpuUefi;
199    NvBool bIsEfiInit;
200
201    EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
202
203    FW_WPR_LAYOUT_OFFSET fwWprLayoutOffset;
204} GspStaticConfigInfo;
205
206typedef struct
207{
208    NvU16               deviceID;           // deviceID
209    NvU16               vendorID;           // vendorID
210    NvU16               subdeviceID;        // subsystem deviceID
211    NvU16               subvendorID;        // subsystem vendorID
212    NvU8                revisionID;         // revision ID
213} BUSINFO;
214
215#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS             (16U)
216
217typedef struct DOD_METHOD_DATA
218{
219    NV_STATUS status;
220    NvU32     acpiIdListLen;
221    NvU32     acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
222} DOD_METHOD_DATA;
223
224typedef struct JT_METHOD_DATA
225{
226    NV_STATUS status;
227    NvU32     jtCaps;
228    NvU16     jtRevId;
229    NvBool    bSBIOSCaps;
230} JT_METHOD_DATA;
231
232typedef struct MUX_METHOD_DATA_ELEMENT
233{
234    NvU32       acpiId;
235    NvU32       mode;
236    NV_STATUS   status;
237} MUX_METHOD_DATA_ELEMENT;
238
239#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS             (16U)
240
241typedef struct MUX_METHOD_DATA
242{
243    NvU32                       tableLen;
244    MUX_METHOD_DATA_ELEMENT     acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
245    MUX_METHOD_DATA_ELEMENT     acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
246    MUX_METHOD_DATA_ELEMENT     acpiIdMuxStateTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];    
247} MUX_METHOD_DATA;
248
249typedef struct CAPS_METHOD_DATA
250{
251    NV_STATUS status;
252    NvU32     optimusCaps;
253} CAPS_METHOD_DATA;
254
255typedef struct ACPI_METHOD_DATA
256{
257    NvBool                                               bValid;
258    DOD_METHOD_DATA                                      dodMethodData;
259    JT_METHOD_DATA                                       jtMethodData;
260    MUX_METHOD_DATA                                      muxMethodData;
261    CAPS_METHOD_DATA                                     capsMethodData;
262} ACPI_METHOD_DATA;
263
264typedef struct GSP_VF_INFO
265{
266    NvU32  totalVFs;
267    NvU32  firstVFOffset;
268    NvU64  FirstVFBar0Address;
269    NvU64  FirstVFBar1Address;
270    NvU64  FirstVFBar2Address;
271    NvBool b64bitBar0;
272    NvBool b64bitBar1;
273    NvBool b64bitBar2;
274} GSP_VF_INFO;
275
276typedef struct
277{
278    // Link capabilities
279    NvU32 linkCap;
280} GSP_PCIE_CONFIG_REG;
281
282typedef struct GspSystemInfo
283{
284    NvU64 gpuPhysAddr;
285    NvU64 gpuPhysFbAddr;
286    NvU64 gpuPhysInstAddr;
287    NvU64 gpuPhysIoAddr;
288    NvU64 nvDomainBusDeviceFunc;
289    NvU64 simAccessBufPhysAddr;
290    NvU64 notifyOpSharedSurfacePhysAddr;
291    NvU64 pcieAtomicsOpMask;
292    NvU64 consoleMemSize;
293    NvU64 maxUserVa;
294    NvU32 pciConfigMirrorBase;
295    NvU32 pciConfigMirrorSize;
296    NvU32 PCIDeviceID;
297    NvU32 PCISubDeviceID;
298    NvU32 PCIRevisionID;
299    NvU32 pcieAtomicsCplDeviceCapMask;
300    NvU8 oorArch;
301    NvU64 clPdbProperties;
302    NvU32 Chipset;
303    NvBool bGpuBehindBridge;
304    NvBool bFlrSupported;
305    NvBool b64bBar0Supported;
306    NvBool bMnocAvailable;
307    NvU32  chipsetL1ssEnable;
308    NvBool bUpstreamL0sUnsupported;
309    NvBool bUpstreamL1Unsupported;
310    NvBool bUpstreamL1PorSupported;
311    NvBool bUpstreamL1PorMobileOnly;
312    NvBool bSystemHasMux;
313    NvU8   upstreamAddressValid;
314    BUSINFO FHBBusInfo;
315    BUSINFO chipsetIDInfo;
316    ACPI_METHOD_DATA acpiMethodData;
317    NvU32 hypervisorType;
318    NvBool bIsPassthru;
319    NvU64 sysTimerOffsetNs;
320    GSP_VF_INFO gspVFInfo;
321    NvBool bIsPrimary;
322    NvBool isGridBuild;
323    GSP_PCIE_CONFIG_REG pcieConfigReg;
324    NvU32 gridBuildCsp;
325    NvBool bPreserveVideoMemoryAllocations;
326    NvBool bTdrEventSupported;
327    NvBool bFeatureStretchVblankCapable;
328    NvBool bEnableDynamicGranularityPageArrays;
329    NvBool bClockBoostSupported;
330    NvBool bRouteDispIntrsToCPU;
331    NvU64  hostPageSize;
332} GspSystemInfo;
333
334typedef struct rpc_os_error_log_v17_00
335{
336    NvU32      exceptType;
337    NvU32      runlistId;
338    NvU32      chid;
339    char       errString[0x100];
340    NvU32      preemptiveRemovalPreviousXid;
341} rpc_os_error_log_v17_00;
342
343typedef struct
344{
345    // Magic
346    // BL to use for verification (i.e. Booter locked it in WPR2)
347    NvU64 magic; // = 0xdc3aae21371a60b3;
348
349    // Revision number of Booter-BL-Sequencer handoff interface
350    // Bumped up when we change this interface so it is not backward compatible.
351    // Bumped up when we revoke GSP-RM ucode
352    NvU64 revision; // = 1;
353
354    // ---- Members regarding data in SYSMEM ----------------------------
355    // Consumed by Booter for DMA
356
357    NvU64 sysmemAddrOfRadix3Elf;
358    NvU64 sizeOfRadix3Elf;
359
360    NvU64 sysmemAddrOfBootloader;
361    NvU64 sizeOfBootloader;
362
363    // Offsets inside bootloader image needed by Booter
364    NvU64 bootloaderCodeOffset;
365    NvU64 bootloaderDataOffset;
366    NvU64 bootloaderManifestOffset;
367
368    union
369    {
370        // Used only at initial boot
371        struct
372        {
373            NvU64 sysmemAddrOfSignature;
374            NvU64 sizeOfSignature;
375        };
376
377        //
378        // Used at suspend/resume to read GspFwHeapFreeList
379        // Offset relative to GspFwWprMeta FBMEM PA (gspFwWprStart)
380        //
381        struct
382        {
383            NvU32 gspFwHeapFreeListWprOffset;
384            NvU32 unused0;
385            NvU64 unused1;
386        };
387    };
388
389    // ---- Members describing FB layout --------------------------------
390    NvU64 gspFwRsvdStart;
391
392    NvU64 nonWprHeapOffset;
393    NvU64 nonWprHeapSize;
394
395    NvU64 gspFwWprStart;
396
397    // GSP-RM to use to setup heap.
398    NvU64 gspFwHeapOffset;
399    NvU64 gspFwHeapSize;
400
401    // BL to use to find ELF for jump
402    NvU64 gspFwOffset;
403    // Size is sizeOfRadix3Elf above.
404
405    NvU64 bootBinOffset;
406    // Size is sizeOfBootloader above.
407
408    NvU64 frtsOffset;
409    NvU64 frtsSize;
410
411    NvU64 gspFwWprEnd;
412
413    // GSP-RM to use for fbRegionInfo?
414    NvU64 fbSize;
415
416    // ---- Other members -----------------------------------------------
417
418    // GSP-RM to use for fbRegionInfo?
419    NvU64 vgaWorkspaceOffset;
420    NvU64 vgaWorkspaceSize;
421
422    // Boot count.  Used to determine whether to load the firmware image.
423    NvU64 bootCount;
424
425    // This union is organized the way it is to start at an 8-byte boundary and achieve natural
426    // packing of the internal struct fields.
427    union
428    {
429        struct
430        {
431            // TODO: the partitionRpc* fields below do not really belong in this
432            //       structure. The values are patched in by the partition bootstrapper
433            //       when GSP-RM is booted in a partition, and this structure was a
434            //       convenient place for the bootstrapper to access them. These should
435            //       be moved to a different comm. mechanism between the bootstrapper
436            //       and the GSP-RM tasks.
437
438            // Shared partition RPC memory (physical address)
439            NvU64 partitionRpcAddr;
440
441            // Offsets relative to partitionRpcAddr
442            NvU16 partitionRpcRequestOffset;
443            NvU16 partitionRpcReplyOffset;
444
445            // Code section and dataSection offset and size.
446            NvU32 elfCodeOffset;
447            NvU32 elfDataOffset;
448            NvU32 elfCodeSize;
449            NvU32 elfDataSize;
450
451            // Used during GSP-RM resume to check for revocation
452            NvU32 lsUcodeVersion;
453        };
454
455        struct
456        {
457            // Pad for the partitionRpc* fields, plus 4 bytes
458            NvU32 partitionRpcPadding[4];
459
460            // CrashCat (contiguous) buffer size/location - occupies same bytes as the
461            // elf(Code|Data)(Offset|Size) fields above.
462            // TODO: move to GSP_FMC_INIT_PARAMS
463            NvU64 sysmemAddrOfCrashReportQueue;
464            NvU32 sizeOfCrashReportQueue;
465
466            // Pad for the lsUcodeVersion field
467            NvU32 lsUcodeVersionPadding[1];
468        };
469    };
470
471    // Number of VF partitions allocating sub-heaps from the WPR heap
472    // Used during boot to ensure the heap is adequately sized
473    NvU8 gspFwHeapVfPartitionCount;
474
475    // Flags to help decide GSP-FW flow.
476    NvU8 flags;
477
478    // Pad structure to exactly 256 bytes.  Can replace padding with additional
479    // fields without incrementing revision.  Padding initialized to 0.
480    NvU8 padding[2];
481
482    //
483    // Starts at gspFwWprEnd+frtsSize b/c FRTS is positioned
484    // to end where this allocation starts (when RM requests FSP to create
485    // FRTS).
486    //
487    NvU32 pmuReservedSize;
488
489    // BL to use for verification (i.e. Booter says OK to boot)
490    NvU64 verified;  // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified
491} GspFwWprMeta;
492
493#define GSP_FW_WPR_META_MAGIC     0xdc3aae21371a60b3ULL
494
495#define GSP_FW_WPR_META_REVISION  1
496
497typedef struct {
498    NvU64 sharedMemPhysAddr;
499    NvU32 pageTableEntryCount;
500    NvLength cmdQueueOffset;
501    NvLength statQueueOffset;
502} MESSAGE_QUEUE_INIT_ARGUMENTS;
503
504typedef struct {
505    NvU32 oldLevel;
506    NvU32 flags;
507    NvBool bInPMTransition;
508} GSP_SR_INIT_ARGUMENTS;
509
510typedef struct
511{
512    MESSAGE_QUEUE_INIT_ARGUMENTS      messageQueueInitArguments;
513    GSP_SR_INIT_ARGUMENTS             srInitArguments;
514    NvU32                             gpuInstance;
515    NvBool                            bDmemStack;
516
517    struct
518    {
519        NvU64                         pa;
520        NvU64                         size;
521    } profilerArgs;
522} GSP_ARGUMENTS_CACHED;
523
524#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3            (0x00000003U)
525
526typedef struct
527{
528    // Magic for verification by secure ucode
529    NvU64 magic;  // = GSP_FW_SR_META_MAGIC;
530
531    //
532    // Revision number
533    // Bumped up when we change this interface so it is not backward compatible.
534    //
535    NvU64 revision;  // = GSP_FW_SR_META_MAGIC_REVISION;
536
537    // Members regarding data in SYSMEM
538    NvU64 sysmemAddrOfSuspendResumeData;
539    NvU64 sizeOfSuspendResumeData;
540
541    //
542    // Internal members for use by secure ucode
543    // Must be exactly GSP_FW_SR_META_INTERNAL_SIZE bytes.
544    //
545    NvU32 internal[32];
546
547    // Same as flags of GspFwWprMeta
548    NvU32 flags;
549
550    // Subrevision number used by secure ucode
551    NvU32 subrevision;
552
553    //
554    // Pad structure to exactly 256 bytes (1 DMA chunk).
555    // Padding initialized to zero.
556    //
557    NvU32 padding[22];
558} GspFwSRMeta;
559
560#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2                   (0 << 20)   // No FB heap usage
561
562#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL        (22 << 20)
563
564#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X               (8 << 20)   // Turing thru Ada
565
566#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB                (64u)
567
568#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA         (12u)
569
570#define BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA    (70u)
571
572#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB \
573                                    (88u + (BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA) + \
574                                    (BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
575
576typedef struct GSP_FMC_INIT_PARAMS
577{
578    // CC initialization "registry keys"
579    NvU32 regkeys;
580} GSP_FMC_INIT_PARAMS;
581
582typedef enum {
583    GSP_DMA_TARGET_LOCAL_FB,
584    GSP_DMA_TARGET_COHERENT_SYSTEM,
585    GSP_DMA_TARGET_NONCOHERENT_SYSTEM,
586    GSP_DMA_TARGET_COUNT
587} GSP_DMA_TARGET;
588
589typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS
590{
591    // Physical memory aperture through which gspRmDescPa is accessed
592    GSP_DMA_TARGET target;
593    // Size in bytes of the GSP-RM descriptor structure
594    NvU32          gspRmDescSize;
595    // Physical offset in the target aperture of the GSP-RM descriptor structure
596    NvU64          gspRmDescOffset;
597    // Physical offset in FB to set the start of the WPR containing GSP-RM
598    NvU64          wprCarveoutOffset;
599    // Size in bytes of the WPR containing GSP-RM
600    NvU32          wprCarveoutSize;
601    // Whether to boot GSP-RM or GSP-Proxy through ACR
602    NvBool         bIsGspRmBoot;
603} GSP_ACR_BOOT_GSP_RM_PARAMS;
604
605typedef struct GSP_RM_PARAMS
606{
607    // Physical memory aperture through which bootArgsOffset is accessed
608    GSP_DMA_TARGET target;
609    // Physical offset in the memory aperture that will be passed to GSP-RM
610    NvU64          bootArgsOffset;
611} GSP_RM_PARAMS;
612
613typedef struct GSP_SPDM_PARAMS
614{
615    // Physical Memory Aperture through which all addresses are accessed
616    GSP_DMA_TARGET target;
617
618    // Physical offset in the memory aperture where SPDM payload is stored
619    NvU64 payloadBufferOffset;
620
621    // Size of the above payload buffer
622    NvU32 payloadBufferSize;
623} GSP_SPDM_PARAMS;
624
625typedef struct GSP_FMC_BOOT_PARAMS
626{
627    GSP_FMC_INIT_PARAMS         initParams;
628    GSP_ACR_BOOT_GSP_RM_PARAMS  bootGspRmParams;
629    GSP_RM_PARAMS               gspRmParams;
630    GSP_SPDM_PARAMS             gspSpdmParams;
631} GSP_FMC_BOOT_PARAMS;
632
633#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100              (14 << 20)   // Hopper+
634#endif