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fifo.h
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linux-6.19.14/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/fifo.h
1/* SPDX-License-Identifier: MIT */ 2 3/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 4 5#ifndef __NVRM_FIFO_H__ 6#define __NVRM_FIFO_H__ 7#include <nvrm/nvtypes.h> 8 9/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/570.144 */ 10 11#define NV_MAX_SUBDEVICES 8 12 13typedef struct NV_MEMORY_DESC_PARAMS { 14 NV_DECLARE_ALIGNED(NvU64 base, 8); 15 NV_DECLARE_ALIGNED(NvU64 size, 8); 16 NvU32 addressSpace; 17 NvU32 cacheAttrib; 18} NV_MEMORY_DESC_PARAMS; 19 20#define CC_CHAN_ALLOC_IV_SIZE_DWORD 3U 21 22#define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U 23 24typedef struct NV_CHANNEL_ALLOC_PARAMS { 25 26 NvHandle hObjectError; // error context DMA 27 NvHandle hObjectBuffer; // no longer used 28 NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO 29 NvU32 gpFifoEntries; // number of GP FIFO entries 30 31 NvU32 flags; 32 33 34 NvHandle hContextShare; // context share handle 35 NvHandle hVASpace; // VASpace for the channel 36 37 // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 38 NvHandle hUserdMemory[NV_MAX_SUBDEVICES]; 39 40 // offset to beginning of UserD within hUserdMemory[x] 41 NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8); 42 43 // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated 44 NvU32 engineType; 45 // Channel identifier that is unique for the duration of a RM session 46 NvU32 cid; 47 // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods 48 NvU32 subDeviceId; 49 NvHandle hObjectEccError; // ECC error context DMA 50 51 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); 52 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); 53 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); 54 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8); 55 56 NvHandle hPhysChannelGroup; // reserved 57 NvU32 internalFlags; // reserved 58 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved 59 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved 60 NvU32 ProcessID; // reserved 61 NvU32 SubProcessID; // reserved 62 63 // IV used for CPU-side encryption / GPU-side decryption. 64 NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved 65 // IV used for CPU-side decryption / GPU-side encryption. 66 NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved 67 // Nonce used CPU-side signing / GPU-side signature verification. 68 NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved 69 NvU32 tpcConfigID; // TPC Configuration Id as supported by DTD-PG Feature 70} NV_CHANNEL_ALLOC_PARAMS; 71 72typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; 73 74#define NVOS04_FLAGS_CHANNEL_TYPE 1:0 75#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 76#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE 77#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE 78#define NVOS04_FLAGS_VPR 2:2 79#define NVOS04_FLAGS_VPR_FALSE 0x00000000 80#define NVOS04_FLAGS_VPR_TRUE 0x00000001 81#define NVOS04_FLAGS_CC_SECURE 2:2 82#define NVOS04_FLAGS_CC_SECURE_FALSE 0x00000000 83#define NVOS04_FLAGS_CC_SECURE_TRUE 0x00000001 84#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 85#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 86#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 87#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 88#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 89#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 90#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 91#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 92#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 93#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 94#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 95#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 96#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 97#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 98#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 99#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 100#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 101#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 102#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 103#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 104#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 105#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 106#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 107#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 108#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 109#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 110#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 111#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 112#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 113#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 114#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 115#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 116#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 117#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 118#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 119#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 120#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 121#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 122#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 123#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 124#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 125#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 126#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 127#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 128#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 129#define NVOS04_FLAGS_MAP_CHANNEL 30:30 130#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 131#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 132#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 133#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 134#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 135 136typedef enum { 137 /*! 138 * Initial state as passed in NV_CHANNEL_ALLOC_PARAMS by 139 * kernel CPU-RM clients. 140 */ 141 ERROR_NOTIFIER_TYPE_UNKNOWN = 0, 142 /*! @brief Error notifier is explicitly not set. 143 * 144 * The corresponding hErrorContext or hEccErrorContext must be 145 * NV01_NULL_OBJECT. 146 */ 147 ERROR_NOTIFIER_TYPE_NONE, 148 /*! @brief Error notifier is a ContextDma */ 149 ERROR_NOTIFIER_TYPE_CTXDMA, 150 /*! @brief Error notifier is a NvNotification array in sysmem/vidmem */ 151 ERROR_NOTIFIER_TYPE_MEMORY 152} ErrorNotifierType; 153 154#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE 1:0 155#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_USER 0x0 156#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_ADMIN 0x1 157#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_KERNEL 0x2 158#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE 3:2 159#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_UNKNOWN ERROR_NOTIFIER_TYPE_UNKNOWN 160#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_NONE ERROR_NOTIFIER_TYPE_NONE 161#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_CTXDMA ERROR_NOTIFIER_TYPE_CTXDMA 162#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_MEMORY ERROR_NOTIFIER_TYPE_MEMORY 163#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE 5:4 164#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_UNKNOWN ERROR_NOTIFIER_TYPE_UNKNOWN 165#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_NONE ERROR_NOTIFIER_TYPE_NONE 166#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_CTXDMA ERROR_NOTIFIER_TYPE_CTXDMA 167#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_MEMORY ERROR_NOTIFIER_TYPE_MEMORY 168#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_GSP_OWNED 6:6 169#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_GSP_OWNED_NO 0x0 170#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_GSP_OWNED_YES 0x1 171#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_UVM_OWNED 7:7 172#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_UVM_OWNED_NO 0x0 173#define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_UVM_OWNED_YES 0x1 174 175typedef struct rpc_rc_triggered_v17_02 176{ 177 NvU32 nv2080EngineType; 178 NvU32 chid; 179 NvU32 gfid; 180 NvU32 exceptLevel; 181 NvU32 exceptType; 182 NvU32 scope; 183 NvU16 partitionAttributionId; 184 NvU32 mmuFaultAddrLo; 185 NvU32 mmuFaultAddrHi; 186 NvU32 mmuFaultType; 187 NvBool bCallbackNeeded; 188 NvU32 rcJournalBufferSize; 189 NvU8 rcJournalBuffer[]; 190} rpc_rc_triggered_v17_02; 191 192#define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS 0x40 193 194typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO { 195 NvU32 engDesc; 196 NvU32 ctxAttr; 197 NvU32 ctxBufferSize; 198 NvU32 addrSpaceList; 199 NvU32 registerBase; 200} NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO; 201 202#define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ 203typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS { 204 NvU32 numConstructedFalcons; 205 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS]; 206} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS; 207 208typedef struct NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS { 209 NvBool bDisableActiveChannels; 210} NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS; 211 212#define NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID" */ 213#endif
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