FILE
disp.h
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linux-6.19.14/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/disp.h
1/* SPDX-License-Identifier: MIT */ 2 3/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 4 5#ifndef __NVRM_DISP_H__ 6#define __NVRM_DISP_H__ 7#include <nvrm/nvtypes.h> 8 9/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/570.144 */ 10 11#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 12typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { 13 NvU32 feHwSysCap; 14 NvU32 windowPresentMask; 15 NvBool bFbRemapperEnabled; 16 NvU32 numHeads; 17 NvU32 i2cPort; 18 NvU32 internalDispActiveMask; 19 NvU32 embeddedDisplayPortMask; 20 NvBool bExternalMuxSupported; 21 NvBool bInternalMuxSupported; 22 NvU32 numDispChannels; 23} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; 24 25#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730107U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */ 26typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS { 27 NvU32 subDeviceInstance; 28 NvU32 displayMask; 29 NvU32 displayMaskDDC; 30} NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS; 31 32#define NV0073_CTRL_MAX_CONNECTORS 4U 33 34#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */ 35typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS { 36 NvU32 subDeviceInstance; 37 NvU32 displayId; 38 NvU32 flags; 39 NvU32 DDCPartners; 40 NvU32 count; 41 struct { 42 NvU32 index; 43 NvU32 type; 44 NvU32 location; 45 } data[NV0073_CTRL_MAX_CONNECTORS]; 46 NvU32 platform; 47} NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS; 48 49#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ 50 51typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS { 52 NvBool bDscSupported; 53 NvU32 encoderColorFormatMask; 54 NvU32 lineBufferSizeKB; 55 NvU32 rateBufferSizeKB; 56 NvU32 bitsPerPixelPrecision; 57 NvU32 maxNumHztSlices; 58 NvU32 lineBufferBitDepth; 59} NV0073_CTRL_CMD_DSC_CAP_PARAMS; 60 61typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { 62 NvU32 subDeviceInstance; 63 NvU32 sorIndex; 64 NvU32 maxLinkRate; 65 NvU32 dpVersionsSupported; 66 NvU32 UHBRSupportedByGpu; 67 NvU32 minPClkForCompressed; 68 NvBool bIsMultistreamSupported; 69 NvBool bIsSCEnabled; 70 NvBool bHasIncreasedWatermarkLimits; 71 NvBool bIsPC2Disabled; 72 NvBool isSingleHeadMSTSupported; 73 NvBool bFECSupported; 74 NvBool bIsTrainPhyRepeater; 75 NvBool bOverrideLinkBw; 76 NvBool bUseRgFlushSequence; 77 NvBool bSupportDPDownSpread; 78 NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; 79} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; 80 81#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ 82#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) 83#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 84#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) 85#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) 86#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 87#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) 88#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) 89#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0 2:2 90#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0_NO (0x00000000U) 91#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0_YES (0x00000001U) 92#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 93#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) 94#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) 95#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U) 96#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) 97#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) 98#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0 0:0 99#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0_NO (0x00000000U) 100#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0_YES (0x00000001U) 101#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5 1:1 102#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5_NO (0x00000000U) 103#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5_YES (0x00000001U) 104#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0 2:2 105#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0_NO (0x00000000U) 106#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0_YES (0x00000001U) 107#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) 108#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) 109#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) 110#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U) 111#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U) 112#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U) 113#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U) 114#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) 115#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) 116 117#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730108U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */ 118typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS { 119 NvU32 subDeviceInstance; 120 NvU32 flags; 121 NvU32 displayMask; 122 NvU32 retryTimeMs; 123} NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS; 124 125#define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ 126typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { 127 NvU32 subDeviceInstance; 128 NvU32 displayId; 129 NvU32 flags; 130 NvU32 UHBRSupportedByDfp; 131} NV0073_CTRL_DFP_GET_INFO_PARAMS; 132 133#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 134#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) 135#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) 136#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) 137#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) 138#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) 139#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) 140#define NV0073_CTRL_DFP_FLAGS_LANE 5:3 141#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) 142#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) 143#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) 144#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) 145#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) 146#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 147#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) 148#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) 149#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 150#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) 151#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) 152#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 153#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) 154#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) 155#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 156#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) 157#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) 158#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 159#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) 160#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) 161#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 162#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) 163#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) 164#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 165#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) 166#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) 167#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR 13:13 168#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_FALSE (0x00000000U) 169#define NV0073_CTRL_DFP_FLAGS_TYPE_C_TO_DP_CONNECTOR_TRUE (0x00000001U) 170#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 171#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) 172#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) 173#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 174#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) 175#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) 176#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 177#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) 178#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) 179#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 180#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) 181#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) 182#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) 183#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) 184#define NV0073_CTRL_DFP_FLAGS_LINK 21:20 185#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) 186#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) 187#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) 188#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 189#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) 190#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) 191#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 192#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) 193#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) 194#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) 195#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) 196#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 197#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) 198#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) 199#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 200#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 201#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) 202#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) 203#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS 0:0 204#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS_FALSE (0x00000000U) 205#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS_TRUE (0x00000001U) 206#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS 1:1 207#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS_FALSE (0x00000000U) 208#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS_TRUE (0x00000001U) 209#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS 2:2 210#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS_FALSE (0x00000000U) 211#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS_TRUE (0x00000001U) 212 213#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x73010cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */ 214typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS { 215 NvU32 subDeviceInstance; 216 NvU32 head; 217 NvU32 flags; 218 NvU32 displayId; 219} NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS; 220 221#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ 222 223#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ 224 225typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { 226 NvU32 subDeviceInstance; 227 NvU32 displayId; 228 NvU32 brightness; 229 NvBool bUncalibrated; 230 NvU8 brightnessType; 231} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; 232 233#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */ 234 235#define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U 236 237typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { 238 // In 239 NvU32 subDeviceInstance; 240 NvU32 displayId; 241 NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; 242 243 // Out 244 NvU16 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; 245 NvU8 linkBwCount; 246} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; 247 248#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */ 249typedef struct NV0073_CTRL_DP_CTRL_PARAMS { 250 NvU32 subDeviceInstance; 251 NvU32 displayId; 252 NvU32 cmd; 253 NvU32 data; 254 NvU32 err; 255 NvU32 retryTimeMs; 256 NvU32 eightLaneDpcdBaseAddr; 257} NV0073_CTRL_DP_CTRL_PARAMS; 258 259typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { 260 NvU32 subDeviceInstance; 261 NvU32 head; 262 NvU32 sorIndex; 263 NvU32 dpLink; 264 265 NvBool bEnableOverride; 266 NvBool bMST; 267 NvU32 singleHeadMultistreamMode; 268 NvU32 hBlankSym; 269 NvU32 vBlankSym; 270 NvU32 colorFormat; 271 NvBool bEnableTwoHeadOneOr; 272 273 struct { 274 NvU32 slotStart; 275 NvU32 slotEnd; 276 NvU32 PBN; 277 NvU32 Timeslice; 278 NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT 279 NvU32 singleHeadMSTPipeline; 280 NvBool bEnableAudioOverRightPanel; 281 } MST; 282 283 struct { 284 NvBool bEnhancedFraming; 285 NvU32 tuSize; 286 NvU32 waterMark; 287 NvBool bEnableAudioOverRightPanel; 288 } SST; 289} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS; 290 291#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ 292typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS { 293 NvU32 subDeviceInstance; 294 NvU32 displayId; 295 NvU32 mute; 296} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS; 297 298#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ 299typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { 300 NvU32 addressSpace; 301 NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); 302 NV_DECLARE_ALIGNED(NvU64 limit, 8); 303 NvU32 cacheSnoop; 304 NvU32 hclass; 305 NvU32 channelInstance; 306 NvBool valid; 307 NvU32 pbTargetAperture; 308 NvU32 channelPBSize; 309 NvU32 subDeviceId; 310} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; 311 312#define ADDR_SYSMEM (1) 313 314#define ADDR_FBMEM 2 // Frame buffer memory space 315 316typedef enum 317{ 318 PB_SIZE_4KB = 0, 319 PB_SIZE_8KB, 320 PB_SIZE_16KB, 321 PB_SIZE_32KB, 322 PB_SIZE_64KB 323} ChannelPBSize; 324 325typedef struct 326{ 327 NvV32 channelInstance; // One of the n channel instances of a given channel type. 328 // Note that core channel has only one instance 329 // while all others have two (one per head). 330 NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer 331 NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications 332 NvU32 offset; // Initial offset for put/get, usually zero. 333 NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs 334 335 NvU32 flags; 336 ChannelPBSize channelPBSize; // Size of Push Buffer requested by client (allowed values in enum) 337#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 338#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 339#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 340 341 NvU32 subDeviceId; // One-hot encoded subDeviceId (i.e. SDM) that will be used to address the channel in the pushbuffer stream (via SSDM method) 342} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; 343 344#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT100 1 345#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT1000 2 346#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_NITS 3 347 348typedef enum 349{ 350 IOVA, 351 PHYS_NVM, 352 PHYS_PCI, 353 PHYS_PCI_COHERENT 354} PBTARGETAPERTURE; 355#endif
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