fifo.c

  1/* SPDX-License-Identifier: MIT
  2 *
  3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
  4 */
  5#include <rm/rm.h>
  6
  7#include <subdev/mmu.h>
  8#include <engine/fifo/priv.h>
  9#include <engine/fifo/chan.h>
 10#include <engine/fifo/runl.h>
 11
 12#include "nvhw/drf.h"
 13
 14#include "nvrm/fifo.h"
 15#include "nvrm/engine.h"
 16
 17#define CHID_PER_USERD 8
 18
 19static int
 20r570_chan_alloc(struct nvkm_gsp_device *device, u32 handle, u32 nv2080_engine_type, u8 runq,
 21	        bool priv, int chid, u64 inst_addr, u64 userd_addr, u64 mthdbuf_addr,
 22		struct nvkm_vmm *vmm, u64 gpfifo_offset, u32 gpfifo_length,
 23		struct nvkm_gsp_object *chan)
 24{
 25	struct nvkm_gsp *gsp = device->object.client->gsp;
 26	struct nvkm_fifo *fifo = gsp->subdev.device->fifo;
 27	const int userd_p = chid / CHID_PER_USERD;
 28	const int userd_i = chid % CHID_PER_USERD;
 29	NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *args;
 30
 31	args = nvkm_gsp_rm_alloc_get(&device->object, handle,
 32				     fifo->func->chan.user.oclass, sizeof(*args), chan);
 33	if (WARN_ON(IS_ERR(args)))
 34		return PTR_ERR(args);
 35
 36	args->gpFifoOffset = gpfifo_offset;
 37	args->gpFifoEntries = gpfifo_length / 8;
 38
 39	args->flags  = NVDEF(NVOS04, FLAGS, CHANNEL_TYPE, PHYSICAL);
 40	args->flags |= NVDEF(NVOS04, FLAGS, VPR, FALSE);
 41	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_MAP_REFCOUNTING, FALSE);
 42	args->flags |= NVVAL(NVOS04, FLAGS, GROUP_CHANNEL_RUNQUEUE, runq);
 43	if (!priv)
 44		args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, FALSE);
 45	else
 46		args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, TRUE);
 47	args->flags |= NVDEF(NVOS04, FLAGS, DELAY_CHANNEL_SCHEDULING, FALSE);
 48	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_PHYSICAL_MODE_CE, FALSE);
 49
 50	args->flags |= NVVAL(NVOS04, FLAGS, CHANNEL_USERD_INDEX_VALUE, userd_i);
 51	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_FIXED, FALSE);
 52	args->flags |= NVVAL(NVOS04, FLAGS, CHANNEL_USERD_INDEX_PAGE_VALUE, userd_p);
 53	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_PAGE_FIXED, TRUE);
 54
 55	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_AUTH_LEVEL_PRIV, FALSE);
 56	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_SCRUBBER, FALSE);
 57	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_CLIENT_MAP_FIFO, FALSE);
 58	args->flags |= NVDEF(NVOS04, FLAGS, SET_EVICT_LAST_CE_PREFETCH_CHANNEL, FALSE);
 59	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_VGPU_PLUGIN_CONTEXT, FALSE);
 60	args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_PBDMA_ACQUIRE_TIMEOUT, FALSE);
 61	args->flags |= NVDEF(NVOS04, FLAGS, GROUP_CHANNEL_THREAD, DEFAULT);
 62	args->flags |= NVDEF(NVOS04, FLAGS, MAP_CHANNEL, FALSE);
 63	args->flags |= NVDEF(NVOS04, FLAGS, SKIP_CTXBUFFER_ALLOC, FALSE);
 64
 65	args->hVASpace = vmm->rm.object.handle;
 66	args->engineType = nv2080_engine_type;
 67
 68	args->instanceMem.base = inst_addr;
 69	args->instanceMem.size = fifo->func->chan.func->inst->size;
 70	args->instanceMem.addressSpace = 2;
 71	args->instanceMem.cacheAttrib = 1;
 72
 73	args->userdMem.base = userd_addr;
 74	args->userdMem.size = fifo->func->chan.func->userd->size;
 75	args->userdMem.addressSpace = 2;
 76	args->userdMem.cacheAttrib = 1;
 77
 78	args->ramfcMem.base = inst_addr;
 79	args->ramfcMem.size = 0x200;
 80	args->ramfcMem.addressSpace = 2;
 81	args->ramfcMem.cacheAttrib = 1;
 82
 83	args->mthdbufMem.base = mthdbuf_addr;
 84	args->mthdbufMem.size = fifo->rm.mthdbuf_size;
 85	args->mthdbufMem.addressSpace = 1;
 86	args->mthdbufMem.cacheAttrib = 0;
 87
 88	if (!priv)
 89		args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, USER);
 90	else
 91		args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, ADMIN);
 92	args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ERROR_NOTIFIER_TYPE, NONE);
 93	args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ECC_ERROR_NOTIFIER_TYPE, NONE);
 94
 95	return nvkm_gsp_rm_alloc_wr(chan, args);
 96}
 97
 98static int
 99r570_fifo_rc_triggered(void *priv, u32 fn, void *repv, u32 repc)
100{
101	rpc_rc_triggered_v17_02 *msg = repv;
102	struct nvkm_gsp *gsp = priv;
103
104	if (WARN_ON(repc < sizeof(*msg)))
105		return -EINVAL;
106
107	nvkm_error(&gsp->subdev, "rc engn:%08x chid:%d gfid:%d level:%d type:%d scope:%d part:%d "
108				 "fault_addr:%08x%08x fault_type:%08x\n",
109		   msg->nv2080EngineType, msg->chid, msg->gfid, msg->exceptLevel, msg->exceptType,
110		   msg->scope, msg->partitionAttributionId,
111		   msg->mmuFaultAddrHi, msg->mmuFaultAddrLo, msg->mmuFaultType);
112
113	r535_fifo_rc_chid(gsp->subdev.device->fifo, msg->chid);
114	return 0;
115}
116
117static int
118r570_fifo_ectx_size(struct nvkm_fifo *fifo)
119{
120	NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *ctrl;
121	struct nvkm_gsp *gsp = fifo->engine.subdev.device->gsp;
122	struct nvkm_runl *runl;
123	struct nvkm_engn *engn;
124
125	ctrl = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice,
126				   NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO,
127				   sizeof(*ctrl));
128	if (WARN_ON(IS_ERR(ctrl)))
129		return PTR_ERR(ctrl);
130
131	for (int i = 0; i < ctrl->numConstructedFalcons; i++) {
132		nvkm_runl_foreach(runl, fifo) {
133			nvkm_runl_foreach_engn(engn, runl) {
134				if (engn->rm.desc == ctrl->constructedFalconsTable[i].engDesc) {
135					engn->rm.size =
136						ctrl->constructedFalconsTable[i].ctxBufferSize;
137					break;
138				}
139			}
140		}
141	}
142
143	nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
144	return 0;
145}
146
147static int
148r570_fifo_xlat_rm_engine_type(u32 rm, enum nvkm_subdev_type *ptype, int *p2080)
149{
150#define RM_ENGINE_TYPE(RM,NVKM,INST)              \
151	RM_ENGINE_TYPE_##RM:                      \
152		*ptype = NVKM_ENGINE_##NVKM;      \
153		*p2080 = NV2080_ENGINE_TYPE_##RM; \
154		return INST
155
156	switch (rm) {
157	case RM_ENGINE_TYPE(    GR0,    GR, 0);
158	case RM_ENGINE_TYPE(  COPY0,    CE, 0);
159	case RM_ENGINE_TYPE(  COPY1,    CE, 1);
160	case RM_ENGINE_TYPE(  COPY2,    CE, 2);
161	case RM_ENGINE_TYPE(  COPY3,    CE, 3);
162	case RM_ENGINE_TYPE(  COPY4,    CE, 4);
163	case RM_ENGINE_TYPE(  COPY5,    CE, 5);
164	case RM_ENGINE_TYPE(  COPY6,    CE, 6);
165	case RM_ENGINE_TYPE(  COPY7,    CE, 7);
166	case RM_ENGINE_TYPE(  COPY8,    CE, 8);
167	case RM_ENGINE_TYPE(  COPY9,    CE, 9);
168	case RM_ENGINE_TYPE( COPY10,    CE, 10);
169	case RM_ENGINE_TYPE( COPY11,    CE, 11);
170	case RM_ENGINE_TYPE( COPY12,    CE, 12);
171	case RM_ENGINE_TYPE( COPY13,    CE, 13);
172	case RM_ENGINE_TYPE( COPY14,    CE, 14);
173	case RM_ENGINE_TYPE( COPY15,    CE, 15);
174	case RM_ENGINE_TYPE( COPY16,    CE, 16);
175	case RM_ENGINE_TYPE( COPY17,    CE, 17);
176	case RM_ENGINE_TYPE( COPY18,    CE, 18);
177	case RM_ENGINE_TYPE( COPY19,    CE, 19);
178	case RM_ENGINE_TYPE( NVDEC0, NVDEC, 0);
179	case RM_ENGINE_TYPE( NVDEC1, NVDEC, 1);
180	case RM_ENGINE_TYPE( NVDEC2, NVDEC, 2);
181	case RM_ENGINE_TYPE( NVDEC3, NVDEC, 3);
182	case RM_ENGINE_TYPE( NVDEC4, NVDEC, 4);
183	case RM_ENGINE_TYPE( NVDEC5, NVDEC, 5);
184	case RM_ENGINE_TYPE( NVDEC6, NVDEC, 6);
185	case RM_ENGINE_TYPE( NVDEC7, NVDEC, 7);
186	case RM_ENGINE_TYPE( NVENC0, NVENC, 0);
187	case RM_ENGINE_TYPE( NVENC1, NVENC, 1);
188	case RM_ENGINE_TYPE( NVENC2, NVENC, 2);
189	case RM_ENGINE_TYPE( NVENC3, NVENC, 3);
190	case RM_ENGINE_TYPE(NVJPEG0, NVJPG, 0);
191	case RM_ENGINE_TYPE(NVJPEG1, NVJPG, 1);
192	case RM_ENGINE_TYPE(NVJPEG2, NVJPG, 2);
193	case RM_ENGINE_TYPE(NVJPEG3, NVJPG, 3);
194	case RM_ENGINE_TYPE(NVJPEG4, NVJPG, 4);
195	case RM_ENGINE_TYPE(NVJPEG5, NVJPG, 5);
196	case RM_ENGINE_TYPE(NVJPEG6, NVJPG, 6);
197	case RM_ENGINE_TYPE(NVJPEG7, NVJPG, 7);
198	case RM_ENGINE_TYPE(     SW,    SW, 0);
199	case RM_ENGINE_TYPE(   SEC2,  SEC2, 0);
200	case RM_ENGINE_TYPE(   OFA0,   OFA, 0);
201	case RM_ENGINE_TYPE(   OFA1,   OFA, 1);
202	default:
203		return -EINVAL;
204	}
205#undef RM_ENGINE_TYPE
206}
207
208const struct nvkm_rm_api_fifo
209r570_fifo = {
210	.xlat_rm_engine_type = r570_fifo_xlat_rm_engine_type,
211	.ectx_size = r570_fifo_ectx_size,
212	.rsvd_chids = 1,
213	.rc_triggered = r570_fifo_rc_triggered,
214	.chan = {
215		.alloc = r570_chan_alloc,
216	},
217};