rm.c

 1/* SPDX-License-Identifier: MIT
 2 *
 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
 4 */
 5#include <rm/rm.h>
 6
 7#include "nvrm/gsp.h"
 8
 9static const struct nvkm_rm_wpr
10r535_wpr_libos2 = {
11	.os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2,
12	.base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X,
13	.heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB,
14};
15
16static const struct nvkm_rm_wpr
17r535_wpr_libos3 = {
18	.os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3,
19	.base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X,
20	.heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB,
21};
22
23static const struct nvkm_rm_api
24r535_api = {
25	.gsp = &r535_gsp,
26	.rpc = &r535_rpc,
27	.ctrl = &r535_ctrl,
28	.alloc = &r535_alloc,
29	.client = &r535_client,
30	.device = &r535_device,
31	.fbsr = &r535_fbsr,
32	.disp = &r535_disp,
33	.fifo = &r535_fifo,
34	.ce = &r535_ce,
35	.gr = &r535_gr,
36	.nvdec = &r535_nvdec,
37	.nvenc = &r535_nvenc,
38	.nvjpg = &r535_nvjpg,
39	.ofa = &r535_ofa,
40};
41
42const struct nvkm_rm_impl
43r535_rm_tu102 = {
44	.wpr = &r535_wpr_libos2,
45	.api = &r535_api,
46};
47
48const struct nvkm_rm_impl
49r535_rm_ga102 = {
50	.wpr = &r535_wpr_libos3,
51	.api = &r535_api,
52};