rpcfn.h

  1/* SPDX-License-Identifier: MIT */
  2
  3/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
  4
  5#ifndef __NVRM_RPCFN_H__
  6#define __NVRM_RPCFN_H__
  7#include <nvrm/nvtypes.h>
  8
  9/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
 10
 11#ifndef X
 12#    define X(UNIT, RPC) NV_VGPU_MSG_FUNCTION_##RPC,
 13#    define DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
 14enum {
 15#endif
 16    X(RM, NOP)                             // 0
 17    X(RM, SET_GUEST_SYSTEM_INFO)           // 1
 18    X(RM, ALLOC_ROOT)                      // 2
 19    X(RM, ALLOC_DEVICE)                    // 3 deprecated
 20    X(RM, ALLOC_MEMORY)                    // 4
 21    X(RM, ALLOC_CTX_DMA)                   // 5
 22    X(RM, ALLOC_CHANNEL_DMA)               // 6
 23    X(RM, MAP_MEMORY)                      // 7
 24    X(RM, BIND_CTX_DMA)                    // 8 deprecated
 25    X(RM, ALLOC_OBJECT)                    // 9
 26    X(RM, FREE)                            //10
 27    X(RM, LOG)                             //11
 28    X(RM, ALLOC_VIDMEM)                    //12
 29    X(RM, UNMAP_MEMORY)                    //13
 30    X(RM, MAP_MEMORY_DMA)                  //14
 31    X(RM, UNMAP_MEMORY_DMA)                //15
 32    X(RM, GET_EDID)                        //16
 33    X(RM, ALLOC_DISP_CHANNEL)              //17
 34    X(RM, ALLOC_DISP_OBJECT)               //18
 35    X(RM, ALLOC_SUBDEVICE)                 //19
 36    X(RM, ALLOC_DYNAMIC_MEMORY)            //20
 37    X(RM, DUP_OBJECT)                      //21
 38    X(RM, IDLE_CHANNELS)                   //22
 39    X(RM, ALLOC_EVENT)                     //23
 40    X(RM, SEND_EVENT)                      //24
 41    X(RM, REMAPPER_CONTROL)                //25 deprecated
 42    X(RM, DMA_CONTROL)                     //26
 43    X(RM, DMA_FILL_PTE_MEM)                //27
 44    X(RM, MANAGE_HW_RESOURCE)              //28
 45    X(RM, BIND_ARBITRARY_CTX_DMA)          //29 deprecated
 46    X(RM, CREATE_FB_SEGMENT)               //30
 47    X(RM, DESTROY_FB_SEGMENT)              //31
 48    X(RM, ALLOC_SHARE_DEVICE)              //32
 49    X(RM, DEFERRED_API_CONTROL)            //33
 50    X(RM, REMOVE_DEFERRED_API)             //34
 51    X(RM, SIM_ESCAPE_READ)                 //35
 52    X(RM, SIM_ESCAPE_WRITE)                //36
 53    X(RM, SIM_MANAGE_DISPLAY_CONTEXT_DMA)  //37
 54    X(RM, FREE_VIDMEM_VIRT)                //38
 55    X(RM, PERF_GET_PSTATE_INFO)            //39  deprecated for vGPU, used by GSP
 56    X(RM, PERF_GET_PERFMON_SAMPLE)         //40
 57    X(RM, PERF_GET_VIRTUAL_PSTATE_INFO)    //41  deprecated
 58    X(RM, PERF_GET_LEVEL_INFO)             //42
 59    X(RM, MAP_SEMA_MEMORY)                 //43
 60    X(RM, UNMAP_SEMA_MEMORY)               //44
 61    X(RM, SET_SURFACE_PROPERTIES)          //45
 62    X(RM, CLEANUP_SURFACE)                 //46
 63    X(RM, UNLOADING_GUEST_DRIVER)          //47
 64    X(RM, TDR_SET_TIMEOUT_STATE)           //48
 65    X(RM, SWITCH_TO_VGA)                   //49
 66    X(RM, GPU_EXEC_REG_OPS)                //50
 67    X(RM, GET_STATIC_INFO)                 //51
 68    X(RM, ALLOC_VIRTMEM)                   //52
 69    X(RM, UPDATE_PDE_2)                    //53
 70    X(RM, SET_PAGE_DIRECTORY)              //54
 71    X(RM, GET_STATIC_PSTATE_INFO)          //55
 72    X(RM, TRANSLATE_GUEST_GPU_PTES)        //56
 73    X(RM, RESERVED_57)                     //57
 74    X(RM, RESET_CURRENT_GR_CONTEXT)        //58
 75    X(RM, SET_SEMA_MEM_VALIDATION_STATE)   //59
 76    X(RM, GET_ENGINE_UTILIZATION)          //60
 77    X(RM, UPDATE_GPU_PDES)                 //61
 78    X(RM, GET_ENCODER_CAPACITY)            //62
 79    X(RM, VGPU_PF_REG_READ32)              //63
 80    X(RM, SET_GUEST_SYSTEM_INFO_EXT)       //64
 81    X(GSP, GET_GSP_STATIC_INFO)            //65
 82    X(RM, RMFS_INIT)                       //66
 83    X(RM, RMFS_CLOSE_QUEUE)                //67
 84    X(RM, RMFS_CLEANUP)                    //68
 85    X(RM, RMFS_TEST)                       //69
 86    X(RM, UPDATE_BAR_PDE)                  //70
 87    X(RM, CONTINUATION_RECORD)             //71
 88    X(RM, GSP_SET_SYSTEM_INFO)             //72
 89    X(RM, SET_REGISTRY)                    //73
 90    X(GSP, GSP_INIT_POST_OBJGPU)           //74 deprecated
 91    X(RM, SUBDEV_EVENT_SET_NOTIFICATION)   //75 deprecated
 92    X(GSP, GSP_RM_CONTROL)                 //76
 93    X(RM, GET_STATIC_INFO2)                //77
 94    X(RM, DUMP_PROTOBUF_COMPONENT)         //78
 95    X(RM, UNSET_PAGE_DIRECTORY)            //79
 96    X(RM, GET_CONSOLIDATED_STATIC_INFO)    //80
 97    X(RM, GMMU_REGISTER_FAULT_BUFFER)      //81 deprecated
 98    X(RM, GMMU_UNREGISTER_FAULT_BUFFER)    //82 deprecated
 99    X(RM, GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER)   //83 deprecated
100    X(RM, GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER) //84 deprecated
101    X(RM, CTRL_SET_VGPU_FB_USAGE)          //85
102    X(RM, CTRL_NVFBC_SW_SESSION_UPDATE_INFO)    //86
103    X(RM, CTRL_NVENC_SW_SESSION_UPDATE_INFO)    //87
104    X(RM, CTRL_RESET_CHANNEL)                   //88
105    X(RM, CTRL_RESET_ISOLATED_CHANNEL)          //89
106    X(RM, CTRL_GPU_HANDLE_VF_PRI_FAULT)         //90
107    X(RM, CTRL_CLK_GET_EXTENDED_INFO)           //91
108    X(RM, CTRL_PERF_BOOST)                      //92
109    X(RM, CTRL_PERF_VPSTATES_GET_CONTROL)       //93
110    X(RM, CTRL_GET_ZBC_CLEAR_TABLE)             //94
111    X(RM, CTRL_SET_ZBC_COLOR_CLEAR)             //95
112    X(RM, CTRL_SET_ZBC_DEPTH_CLEAR)             //96
113    X(RM, CTRL_GPFIFO_SCHEDULE)                 //97
114    X(RM, CTRL_SET_TIMESLICE)                   //98
115    X(RM, CTRL_PREEMPT)                         //99
116    X(RM, CTRL_FIFO_DISABLE_CHANNELS)           //100
117    X(RM, CTRL_SET_TSG_INTERLEAVE_LEVEL)        //101
118    X(RM, CTRL_SET_CHANNEL_INTERLEAVE_LEVEL)    //102
119    X(GSP, GSP_RM_ALLOC)                        //103
120    X(RM, CTRL_GET_P2P_CAPS_V2)                 //104
121    X(RM, CTRL_CIPHER_AES_ENCRYPT)              //105
122    X(RM, CTRL_CIPHER_SESSION_KEY)              //106
123    X(RM, CTRL_CIPHER_SESSION_KEY_STATUS)       //107
124    X(RM, CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES)   //108
125    X(RM, CTRL_DBG_READ_ALL_SM_ERROR_STATES)    //109
126    X(RM, CTRL_DBG_SET_EXCEPTION_MASK)          //110
127    X(RM, CTRL_GPU_PROMOTE_CTX)                 //111
128    X(RM, CTRL_GR_CTXSW_PREEMPTION_BIND)        //112
129    X(RM, CTRL_GR_SET_CTXSW_PREEMPTION_MODE)    //113
130    X(RM, CTRL_GR_CTXSW_ZCULL_BIND)             //114
131    X(RM, CTRL_GPU_INITIALIZE_CTX)              //115
132    X(RM, CTRL_VASPACE_COPY_SERVER_RESERVED_PDES)    //116
133    X(RM, CTRL_FIFO_CLEAR_FAULTED_BIT)          //117
134    X(RM, CTRL_GET_LATEST_ECC_ADDRESSES)        //118
135    X(RM, CTRL_MC_SERVICE_INTERRUPTS)           //119
136    X(RM, CTRL_DMA_SET_DEFAULT_VASPACE)         //120
137    X(RM, CTRL_GET_CE_PCE_MASK)                 //121
138    X(RM, CTRL_GET_ZBC_CLEAR_TABLE_ENTRY)       //122
139    X(RM, CTRL_GET_NVLINK_PEER_ID_MASK)         //123
140    X(RM, CTRL_GET_NVLINK_STATUS)               //124
141    X(RM, CTRL_GET_P2P_CAPS)                    //125
142    X(RM, CTRL_GET_P2P_CAPS_MATRIX)             //126
143    X(RM, RESERVED_0)                           //127
144    X(RM, CTRL_RESERVE_PM_AREA_SMPC)            //128
145    X(RM, CTRL_RESERVE_HWPM_LEGACY)             //129
146    X(RM, CTRL_B0CC_EXEC_REG_OPS)               //130
147    X(RM, CTRL_BIND_PM_RESOURCES)               //131
148    X(RM, CTRL_DBG_SUSPEND_CONTEXT)             //132
149    X(RM, CTRL_DBG_RESUME_CONTEXT)              //133
150    X(RM, CTRL_DBG_EXEC_REG_OPS)                //134
151    X(RM, CTRL_DBG_SET_MODE_MMU_DEBUG)          //135
152    X(RM, CTRL_DBG_READ_SINGLE_SM_ERROR_STATE)  //136
153    X(RM, CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE) //137
154    X(RM, CTRL_DBG_SET_MODE_ERRBAR_DEBUG)       //138
155    X(RM, CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE)  //139
156    X(RM, CTRL_ALLOC_PMA_STREAM)                //140
157    X(RM, CTRL_PMA_STREAM_UPDATE_GET_PUT)       //141
158    X(RM, CTRL_FB_GET_INFO_V2)                  //142
159    X(RM, CTRL_FIFO_SET_CHANNEL_PROPERTIES)     //143
160    X(RM, CTRL_GR_GET_CTX_BUFFER_INFO)          //144
161    X(RM, CTRL_KGR_GET_CTX_BUFFER_PTES)         //145
162    X(RM, CTRL_GPU_EVICT_CTX)                   //146
163    X(RM, CTRL_FB_GET_FS_INFO)                  //147
164    X(RM, CTRL_GRMGR_GET_GR_FS_INFO)            //148
165    X(RM, CTRL_STOP_CHANNEL)                    //149
166    X(RM, CTRL_GR_PC_SAMPLING_MODE)             //150
167    X(RM, CTRL_PERF_RATED_TDP_GET_STATUS)       //151
168    X(RM, CTRL_PERF_RATED_TDP_SET_CONTROL)      //152
169    X(RM, CTRL_FREE_PMA_STREAM)                 //153
170    X(RM, CTRL_TIMER_SET_GR_TICK_FREQ)          //154
171    X(RM, CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB) //155
172    X(RM, GET_CONSOLIDATED_GR_STATIC_INFO)      //156
173    X(RM, CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP)   //157
174    X(RM, CTRL_GR_GET_TPC_PARTITION_MODE)       //158
175    X(RM, CTRL_GR_SET_TPC_PARTITION_MODE)       //159
176    X(UVM, UVM_PAGING_CHANNEL_ALLOCATE)         //160
177    X(UVM, UVM_PAGING_CHANNEL_DESTROY)          //161
178    X(UVM, UVM_PAGING_CHANNEL_MAP)              //162
179    X(UVM, UVM_PAGING_CHANNEL_UNMAP)            //163
180    X(UVM, UVM_PAGING_CHANNEL_PUSH_STREAM)      //164
181    X(UVM, UVM_PAGING_CHANNEL_SET_HANDLES)      //165
182    X(UVM, UVM_METHOD_STREAM_GUEST_PAGES_OPERATION)  //166
183    X(RM, CTRL_INTERNAL_QUIESCE_PMA_CHANNEL)    //167
184    X(RM, DCE_RM_INIT)                          //168
185    X(RM, REGISTER_VIRTUAL_EVENT_BUFFER)        //169
186    X(RM, CTRL_EVENT_BUFFER_UPDATE_GET)         //170
187    X(RM, GET_PLCABLE_ADDRESS_KIND)             //171
188    X(RM, CTRL_PERF_LIMITS_SET_STATUS_V2)       //172
189    X(RM, CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM)    //173
190    X(RM, CTRL_GET_MMU_DEBUG_MODE)              //174
191    X(RM, CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS) //175
192    X(RM, CTRL_FLCN_GET_CTX_BUFFER_SIZE)        //176
193    X(RM, CTRL_FLCN_GET_CTX_BUFFER_INFO)        //177
194    X(RM, DISABLE_CHANNELS)                     //178
195    X(RM, CTRL_FABRIC_MEMORY_DESCRIBE)          //179
196    X(RM, CTRL_FABRIC_MEM_STATS)                //180
197    X(RM, SAVE_HIBERNATION_DATA)                //181
198    X(RM, RESTORE_HIBERNATION_DATA)             //182
199    X(RM, CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED) //183
200    X(RM, CTRL_EXEC_PARTITIONS_CREATE)          //184
201    X(RM, CTRL_EXEC_PARTITIONS_DELETE)          //185
202    X(RM, CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN)    //186
203    X(RM, CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX) //187
204    X(RM, PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION)  //188
205    X(RM, CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK)    //189
206    X(RM, SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER)  //190
207    X(RM, CTRL_SUBDEVICE_GET_P2P_CAPS)          // 191
208    X(RM, CTRL_BUS_SET_P2P_MAPPING)             // 192
209    X(RM, CTRL_BUS_UNSET_P2P_MAPPING)           // 193
210    X(RM, CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK)    // 194
211    X(RM, CTRL_GPU_MIGRATABLE_OPS)              // 195
212    X(RM, CTRL_GET_TOTAL_HS_CREDITS)            // 196
213    X(RM, CTRL_GET_HS_CREDITS)                  // 197
214    X(RM, CTRL_SET_HS_CREDITS)                  // 198
215    X(RM, CTRL_PM_AREA_PC_SAMPLER)              // 199
216    X(RM, INVALIDATE_TLB)                       // 200
217    X(RM, RESERVED_201)                         // 201
218    X(RM, ECC_NOTIFIER_WRITE_ACK)               // 202
219    X(RM, NUM_FUNCTIONS)                        //END
220#ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
221};
222#   undef X
223#   undef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
224#endif
225#endif