gsp.h

  1/* SPDX-License-Identifier: MIT */
  2
  3/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
  4
  5#ifndef __NVRM_GSP_H__
  6#define __NVRM_GSP_H__
  7#include <nvrm/nvtypes.h>
  8
  9/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
 10
 11#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U
 12
 13#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES   17U
 14
 15typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
 16
 17typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO {
 18    NV_DECLARE_ALIGNED(NvU64 base, 8);
 19    NV_DECLARE_ALIGNED(NvU64 limit, 8);
 20    NV_DECLARE_ALIGNED(NvU64 reserved, 8);
 21    NvU32                                                  performance;
 22    NvBool                                                 supportCompressed;
 23    NvBool                                                 supportISO;
 24    NvBool                                                 bProtected;
 25    NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG blackList;
 26} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO;
 27
 28typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS {
 29    NvU32 numFBRegions;
 30    NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8);
 31} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS;
 32
 33#define NV0080_CTRL_GR_CAPS_TBL_SIZE            23
 34
 35#define NV2080_GPU_MAX_GID_LENGTH             (0x000000100ULL)
 36
 37typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
 38    NvU32 index;
 39    NvU32 flags;
 40    NvU32 length;
 41    NvU8  data[NV2080_GPU_MAX_GID_LENGTH];
 42} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS;
 43
 44typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS {
 45    NvU32 gpcMask;
 46} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS;
 47
 48typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS {
 49    NvU32 gpcId;
 50    NvU32 tpcMask;
 51} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS;
 52
 53typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS {
 54    NvU32 gpcId;
 55    NvU32 zcullMask;
 56} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS;
 57
 58typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
 59    NvU32 BoardID;
 60    char  chipSKU[4];
 61    char  chipSKUMod[2];
 62    char  project[5];
 63    char  projectSKU[5];
 64    char  CDP[6];
 65    char  projectSKUMod[2];
 66    NvU32 businessCycle;
 67} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS;
 68
 69typedef enum
 70{
 71    COMPUTE_BRANDING_TYPE_NONE,
 72    COMPUTE_BRANDING_TYPE_TESLA,
 73} COMPUTE_BRANDING_TYPE;
 74
 75#define MAX_GPC_COUNT           32
 76
 77typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
 78    NvU32  totalVFs;
 79    NvU32  firstVfOffset;
 80    NvU32  vfFeatureMask;
 81    NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8);
 82    NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8);
 83    NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8);
 84    NV_DECLARE_ALIGNED(NvU64 bar0Size, 8);
 85    NV_DECLARE_ALIGNED(NvU64 bar1Size, 8);
 86    NV_DECLARE_ALIGNED(NvU64 bar2Size, 8);
 87    NvBool b64bitBar0;
 88    NvBool b64bitBar1;
 89    NvBool b64bitBar2;
 90    NvBool bSriovEnabled;
 91    NvBool bSriovHeavyEnabled;
 92    NvBool bEmulateVFBar0TlbInvalidationRegister;
 93    NvBool bClientRmAllocatedCtxBuffer;
 94} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
 95
 96#include "engine.h"
 97
 98#define NVGPU_ENGINE_CAPS_MASK_BITS                32
 99
100#define NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX           ((RM_ENGINE_TYPE_LAST-1)/NVGPU_ENGINE_CAPS_MASK_BITS + 1)
101
102typedef struct GspSMInfo_t
103{
104    NvU32 version;
105    NvU32 regBankCount;
106    NvU32 regBankRegCount;
107    NvU32 maxWarpsPerSM;
108    NvU32 maxThreadsPerWarp;
109    NvU32 geomGsObufEntries;
110    NvU32 geomXbufEntries;
111    NvU32 maxSPPerSM;
112    NvU32 rtCoreCount;
113} GspSMInfo;
114
115typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
116    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0,
117    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1,
118    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2,
119    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3,
120    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4,
121    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5,
122    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6,
123    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7,
124    NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 8,
125} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS;
126
127#define NV2080_GPU_MAX_NAME_STRING_LENGTH                  (0x0000040U)
128
129typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS 
130{
131    NvU32 numHeads;
132    NvU32 maxNumHeads;
133} VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS;
134
135typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS 
136{
137    NvU32 headIndex;
138    NvU32 maxHResolution;
139    NvU32 maxVResolution;
140} VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS;
141
142typedef struct GspStaticConfigInfo_t
143{
144    NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE];
145    NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo;
146    NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS gpcInfo;
147    NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS tpcInfo[MAX_GPC_COUNT];
148    NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS zcullInfo[MAX_GPC_COUNT];
149    NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
150    NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
151    COMPUTE_BRANDING_TYPE computeBranding;
152
153    NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps;
154    NvU32 sriovMaxGfid;
155
156    NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
157
158    GspSMInfo SM_info;
159
160    NvBool poisonFuseEnabled;
161
162    NvU64 fb_length;
163    NvU32 fbio_mask;
164    NvU32 fb_bus_width;
165    NvU32 fb_ram_type;
166    NvU32 fbp_mask;
167    NvU32 l2_cache_size;
168
169    NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL];
170    NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL];
171
172    NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
173    NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
174    NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
175    NvBool bGpuInternalSku;
176    NvBool bIsQuadroGeneric;
177    NvBool bIsQuadroAd;
178    NvBool bIsNvidiaNvs;
179    NvBool bIsVgx;
180    NvBool bGeforceSmb;
181    NvBool bIsTitan;
182    NvBool bIsTesla;
183    NvBool bIsMobile;
184    NvBool bIsGc6Rtd3Allowed;
185    NvBool bIsGcOffRtd3Allowed;
186    NvBool bIsGcoffLegacyAllowed;
187
188    NvU64 bar1PdeBase;
189    NvU64 bar2PdeBase;
190
191    NvBool bVbiosValid;
192    NvU32 vbiosSubVendor;
193    NvU32 vbiosSubDevice;
194
195    NvBool bPageRetirementSupported;
196
197    NvBool bSplitVasBetweenServerClientRm;
198
199    NvBool bClRootportNeedsNosnoopWAR;
200
201    VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
202    VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
203    NvU64 displaylessMaxPixels;
204
205    // Client handle for internal RMAPI control.
206    NvHandle hInternalClient;
207
208    // Device handle for internal RMAPI control.
209    NvHandle hInternalDevice;
210
211    // Subdevice handle for internal RMAPI control.
212    NvHandle hInternalSubdevice;
213
214    NvBool bSelfHostedMode;
215    NvBool bAtsSupported;
216
217    NvBool bIsGpuUefi;
218} GspStaticConfigInfo;
219
220typedef struct rpc_unloading_guest_driver_v1F_07
221{
222    NvBool     bInPMTransition;
223    NvBool     bGc6Entering;
224    NvU32      newLevel;
225} rpc_unloading_guest_driver_v1F_07;
226
227typedef struct PACKED_REGISTRY_ENTRY
228{
229    NvU32                   nameOffset;
230    NvU8                    type;
231    NvU32                   data;
232    NvU32                   length;
233} PACKED_REGISTRY_ENTRY;
234
235typedef struct PACKED_REGISTRY_TABLE
236{
237    NvU32                   size;
238    NvU32                   numEntries;
239    PACKED_REGISTRY_ENTRY   entries[] __counted_by(numEntries);
240} PACKED_REGISTRY_TABLE;
241
242typedef struct
243{
244    NvU16               deviceID;           // deviceID
245    NvU16               vendorID;           // vendorID
246    NvU16               subdeviceID;        // subsystem deviceID
247    NvU16               subvendorID;        // subsystem vendorID
248    NvU8                revisionID;         // revision ID
249} BUSINFO;
250
251#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS             (16U)
252
253typedef struct DOD_METHOD_DATA
254{
255    NV_STATUS status;
256    NvU32     acpiIdListLen;
257    NvU32     acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
258} DOD_METHOD_DATA;
259
260typedef struct JT_METHOD_DATA
261{
262    NV_STATUS status;
263    NvU32     jtCaps;
264    NvU16     jtRevId;
265    NvBool    bSBIOSCaps;
266} JT_METHOD_DATA;
267
268typedef struct MUX_METHOD_DATA_ELEMENT
269{
270    NvU32       acpiId;
271    NvU32       mode;
272    NV_STATUS   status;
273} MUX_METHOD_DATA_ELEMENT;
274
275#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS             (16U)
276
277typedef struct MUX_METHOD_DATA
278{
279    NvU32                       tableLen;
280    MUX_METHOD_DATA_ELEMENT     acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
281    MUX_METHOD_DATA_ELEMENT     acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
282} MUX_METHOD_DATA;
283
284typedef struct CAPS_METHOD_DATA
285{
286    NV_STATUS status;
287    NvU32     optimusCaps;
288} CAPS_METHOD_DATA;
289
290typedef struct ACPI_METHOD_DATA
291{
292    NvBool                                               bValid;
293    DOD_METHOD_DATA                                      dodMethodData;
294    JT_METHOD_DATA                                       jtMethodData;
295    MUX_METHOD_DATA                                      muxMethodData;
296    CAPS_METHOD_DATA                                     capsMethodData;
297} ACPI_METHOD_DATA;
298
299typedef struct GSP_VF_INFO
300{
301    NvU32  totalVFs;
302    NvU32  firstVFOffset;
303    NvU64  FirstVFBar0Address;
304    NvU64  FirstVFBar1Address;
305    NvU64  FirstVFBar2Address;
306    NvBool b64bitBar0;
307    NvBool b64bitBar1;
308    NvBool b64bitBar2;
309} GSP_VF_INFO;
310
311typedef struct GspSystemInfo
312{
313    NvU64 gpuPhysAddr;
314    NvU64 gpuPhysFbAddr;
315    NvU64 gpuPhysInstAddr;
316    NvU64 nvDomainBusDeviceFunc;
317    NvU64 simAccessBufPhysAddr;
318    NvU64 pcieAtomicsOpMask;
319    NvU64 consoleMemSize;
320    NvU64 maxUserVa;
321    NvU32 pciConfigMirrorBase;
322    NvU32 pciConfigMirrorSize;
323    NvU8 oorArch;
324    NvU64 clPdbProperties;
325    NvU32 Chipset;
326    NvBool bGpuBehindBridge;
327    NvBool bMnocAvailable;
328    NvBool bUpstreamL0sUnsupported;
329    NvBool bUpstreamL1Unsupported;
330    NvBool bUpstreamL1PorSupported;
331    NvBool bUpstreamL1PorMobileOnly;
332    NvU8   upstreamAddressValid;
333    BUSINFO FHBBusInfo;
334    BUSINFO chipsetIDInfo;
335    ACPI_METHOD_DATA acpiMethodData;
336    NvU32 hypervisorType;
337    NvBool bIsPassthru;
338    NvU64 sysTimerOffsetNs;
339    GSP_VF_INFO gspVFInfo;
340} GspSystemInfo;
341
342typedef struct rpc_os_error_log_v17_00
343{
344    NvU32      exceptType;
345    NvU32      runlistId;
346    NvU32      chid;
347    char       errString[0x100];
348} rpc_os_error_log_v17_00;
349
350typedef struct rpc_run_cpu_sequencer_v17_00
351{
352    NvU32      bufferSizeDWord;
353    NvU32      cmdIndex;
354    NvU32      regSaveArea[8];
355    NvU32      commandBuffer[];
356} rpc_run_cpu_sequencer_v17_00;
357
358typedef enum GSP_SEQ_BUF_OPCODE
359{
360    GSP_SEQ_BUF_OPCODE_REG_WRITE = 0,
361    GSP_SEQ_BUF_OPCODE_REG_MODIFY,
362    GSP_SEQ_BUF_OPCODE_REG_POLL,
363    GSP_SEQ_BUF_OPCODE_DELAY_US,
364    GSP_SEQ_BUF_OPCODE_REG_STORE,
365    GSP_SEQ_BUF_OPCODE_CORE_RESET,
366    GSP_SEQ_BUF_OPCODE_CORE_START,
367    GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT,
368    GSP_SEQ_BUF_OPCODE_CORE_RESUME,
369} GSP_SEQ_BUF_OPCODE;
370
371typedef struct
372{
373    NvU32 addr;
374    NvU32 val;
375} GSP_SEQ_BUF_PAYLOAD_REG_WRITE;
376
377typedef struct
378{
379    NvU32 addr;
380    NvU32 mask;
381    NvU32 val;
382} GSP_SEQ_BUF_PAYLOAD_REG_MODIFY;
383
384typedef struct
385{
386    NvU32 addr;
387    NvU32 mask;
388    NvU32 val;
389    NvU32 timeout;
390    NvU32 error;
391} GSP_SEQ_BUF_PAYLOAD_REG_POLL;
392
393typedef struct
394{
395    NvU32 val;
396} GSP_SEQ_BUF_PAYLOAD_DELAY_US;
397
398typedef struct
399{
400    NvU32 addr;
401    NvU32 index;
402} GSP_SEQ_BUF_PAYLOAD_REG_STORE;
403
404typedef struct GSP_SEQUENCER_BUFFER_CMD
405{
406    GSP_SEQ_BUF_OPCODE opCode;
407    union
408    {
409        GSP_SEQ_BUF_PAYLOAD_REG_WRITE regWrite;
410        GSP_SEQ_BUF_PAYLOAD_REG_MODIFY regModify;
411        GSP_SEQ_BUF_PAYLOAD_REG_POLL regPoll;
412        GSP_SEQ_BUF_PAYLOAD_DELAY_US delayUs;
413        GSP_SEQ_BUF_PAYLOAD_REG_STORE regStore;
414    } payload;
415} GSP_SEQUENCER_BUFFER_CMD;
416
417typedef struct
418{
419    // Magic
420    // BL to use for verification (i.e. Booter locked it in WPR2)
421    NvU64 magic; // = 0xdc3aae21371a60b3;
422
423    // Revision number of Booter-BL-Sequencer handoff interface
424    // Bumped up when we change this interface so it is not backward compatible.
425    // Bumped up when we revoke GSP-RM ucode
426    NvU64 revision; // = 1;
427
428    // ---- Members regarding data in SYSMEM ----------------------------
429    // Consumed by Booter for DMA
430
431    NvU64 sysmemAddrOfRadix3Elf;
432    NvU64 sizeOfRadix3Elf;
433
434    NvU64 sysmemAddrOfBootloader;
435    NvU64 sizeOfBootloader;
436
437    // Offsets inside bootloader image needed by Booter
438    NvU64 bootloaderCodeOffset;
439    NvU64 bootloaderDataOffset;
440    NvU64 bootloaderManifestOffset;
441
442    union
443    {
444        // Used only at initial boot
445        struct
446        {
447            NvU64 sysmemAddrOfSignature;
448            NvU64 sizeOfSignature;
449        };
450
451        //
452        // Used at suspend/resume to read GspFwHeapFreeList
453        // Offset relative to GspFwWprMeta FBMEM PA (gspFwWprStart)
454        //
455        struct
456        {
457            NvU32 gspFwHeapFreeListWprOffset;
458            NvU32 unused0;
459            NvU64 unused1;
460        };
461    };
462
463    // ---- Members describing FB layout --------------------------------
464    NvU64 gspFwRsvdStart;
465
466    NvU64 nonWprHeapOffset;
467    NvU64 nonWprHeapSize;
468
469    NvU64 gspFwWprStart;
470
471    // GSP-RM to use to setup heap.
472    NvU64 gspFwHeapOffset;
473    NvU64 gspFwHeapSize;
474
475    // BL to use to find ELF for jump
476    NvU64 gspFwOffset;
477    // Size is sizeOfRadix3Elf above.
478
479    NvU64 bootBinOffset;
480    // Size is sizeOfBootloader above.
481
482    NvU64 frtsOffset;
483    NvU64 frtsSize;
484
485    NvU64 gspFwWprEnd;
486
487    // GSP-RM to use for fbRegionInfo?
488    NvU64 fbSize;
489
490    // ---- Other members -----------------------------------------------
491
492    // GSP-RM to use for fbRegionInfo?
493    NvU64 vgaWorkspaceOffset;
494    NvU64 vgaWorkspaceSize;
495
496    // Boot count.  Used to determine whether to load the firmware image.
497    NvU64 bootCount;
498
499    // This union is organized the way it is to start at an 8-byte boundary and achieve natural
500    // packing of the internal struct fields.
501    union
502    {
503        struct
504        {
505            // TODO: the partitionRpc* fields below do not really belong in this
506            //       structure. The values are patched in by the partition bootstrapper
507            //       when GSP-RM is booted in a partition, and this structure was a
508            //       convenient place for the bootstrapper to access them. These should
509            //       be moved to a different comm. mechanism between the bootstrapper
510            //       and the GSP-RM tasks.
511
512            // Shared partition RPC memory (physical address)
513            NvU64 partitionRpcAddr;
514
515            // Offsets relative to partitionRpcAddr
516            NvU16 partitionRpcRequestOffset;
517            NvU16 partitionRpcReplyOffset;
518
519            // Code section and dataSection offset and size.
520            NvU32 elfCodeOffset;
521            NvU32 elfDataOffset;
522            NvU32 elfCodeSize;
523            NvU32 elfDataSize;
524
525            // Used during GSP-RM resume to check for revocation
526            NvU32 lsUcodeVersion;
527        };
528
529        struct
530        {
531            // Pad for the partitionRpc* fields, plus 4 bytes
532            NvU32 partitionRpcPadding[4];
533
534            // CrashCat (contiguous) buffer size/location - occupies same bytes as the
535            // elf(Code|Data)(Offset|Size) fields above.
536            // TODO: move to GSP_FMC_INIT_PARAMS
537            NvU64 sysmemAddrOfCrashReportQueue;
538            NvU32 sizeOfCrashReportQueue;
539
540            // Pad for the lsUcodeVersion field
541            NvU32 lsUcodeVersionPadding[1];
542        };
543    };
544
545    // Number of VF partitions allocating sub-heaps from the WPR heap
546    // Used during boot to ensure the heap is adequately sized
547    NvU8 gspFwHeapVfPartitionCount;
548
549    // Pad structure to exactly 256 bytes.  Can replace padding with additional
550    // fields without incrementing revision.  Padding initialized to 0.
551    NvU8 padding[7];
552
553    // BL to use for verification (i.e. Booter says OK to boot)
554    NvU64 verified;  // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified
555} GspFwWprMeta;
556
557#define GSP_FW_WPR_META_MAGIC     0xdc3aae21371a60b3ULL
558
559#define GSP_FW_WPR_META_REVISION  1
560
561typedef struct
562{
563    NvU32 version;   // queue version
564    NvU32 size;      // bytes, page aligned
565    NvU32 msgSize;   // entry size, bytes, must be power-of-2, 16 is minimum
566    NvU32 msgCount;  // number of entries in queue
567    NvU32 writePtr;  // message id of next slot
568    NvU32 flags;     // if set it means "i want to swap RX"
569    NvU32 rxHdrOff;  // Offset of msgqRxHeader from start of backing store.
570    NvU32 entryOff;  // Offset of entries from start of backing store.
571} msgqTxHeader;
572
573typedef struct
574{
575    NvU32 readPtr; // message id of last message read
576} msgqRxHeader;
577
578typedef struct {
579    RmPhysAddr sharedMemPhysAddr;
580    NvU32 pageTableEntryCount;
581    NvLength cmdQueueOffset;
582    NvLength statQueueOffset;
583    NvLength locklessCmdQueueOffset;
584    NvLength locklessStatQueueOffset;
585} MESSAGE_QUEUE_INIT_ARGUMENTS;
586
587typedef struct {
588    NvU32 oldLevel;
589    NvU32 flags;
590    NvBool bInPMTransition;
591} GSP_SR_INIT_ARGUMENTS;
592
593typedef struct
594{
595    MESSAGE_QUEUE_INIT_ARGUMENTS      messageQueueInitArguments;
596    GSP_SR_INIT_ARGUMENTS             srInitArguments;
597    NvU32                             gpuInstance;
598
599    struct
600    {
601        NvU64                         pa;
602        NvU64                         size;
603    } profilerArgs;
604} GSP_ARGUMENTS_CACHED;
605
606#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0            (0x00000000U)
607
608#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3            (0x00000003U)
609
610typedef NvU64 LibosAddress;
611
612typedef struct
613{
614    LibosAddress          id8;  // Id tag.
615    LibosAddress          pa;   // Physical address.
616    LibosAddress          size; // Size of memory area.
617    NvU8                  kind; // See LibosMemoryRegionKind above.
618    NvU8                  loc;  // See LibosMemoryRegionLoc above.
619} LibosMemoryRegionInitArgument;
620
621typedef enum {
622    LIBOS_MEMORY_REGION_NONE,
623    LIBOS_MEMORY_REGION_CONTIGUOUS,
624    LIBOS_MEMORY_REGION_RADIX3
625} LibosMemoryRegionKind;
626
627typedef enum {
628    LIBOS_MEMORY_REGION_LOC_NONE,
629    LIBOS_MEMORY_REGION_LOC_SYSMEM,
630    LIBOS_MEMORY_REGION_LOC_FB
631} LibosMemoryRegionLoc;
632
633typedef struct
634{
635    //
636    // Magic
637    // Use for verification by Booter
638    //
639    NvU64 magic;  // = GSP_FW_SR_META_MAGIC;
640
641    //
642    // Revision number
643    // Bumped up when we change this interface so it is not backward compatible.
644    // Bumped up when we revoke GSP-RM ucode
645    //
646    NvU64 revision;  // = GSP_FW_SR_META_MAGIC_REVISION;
647
648    //
649    // ---- Members regarding data in SYSMEM ----------------------------
650    // Consumed by Booter for DMA
651    //
652    NvU64 sysmemAddrOfSuspendResumeData;
653    NvU64 sizeOfSuspendResumeData;
654
655    // ---- Members for crypto ops across S/R ---------------------------
656
657    //
658    // HMAC over the entire GspFwSRMeta structure (including padding)
659    // with the hmac field itself zeroed.
660    //
661    NvU8 hmac[32];
662
663    // Hash over GspFwWprMeta structure
664    NvU8 wprMetaHash[32];
665
666    // Hash over GspFwHeapFreeList structure. All zeros signifies no free list.
667    NvU8 heapFreeListHash[32];
668
669    // Hash over data in WPR2 (skipping over free heap chunks; see Booter for details)
670    NvU8 dataHash[32];
671
672    //
673    // Pad structure to exactly 256 bytes (1 DMA chunk).
674    // Padding initialized to zero.
675    //
676    NvU32 padding[24];
677
678} GspFwSRMeta;
679
680#define GSP_FW_SR_META_MAGIC     0x8a3bb9e6c6c39d93ULL
681
682#define GSP_FW_SR_META_REVISION  2
683
684#define GSP_SEQUENCER_PAYLOAD_SIZE_DWORDS(opcode)                       \
685    ((opcode == GSP_SEQ_BUF_OPCODE_REG_WRITE)  ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_WRITE)  / sizeof(NvU32)) : \
686     (opcode == GSP_SEQ_BUF_OPCODE_REG_MODIFY) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_MODIFY) / sizeof(NvU32)) : \
687     (opcode == GSP_SEQ_BUF_OPCODE_REG_POLL)   ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_POLL)   / sizeof(NvU32)) : \
688     (opcode == GSP_SEQ_BUF_OPCODE_DELAY_US)   ? (sizeof(GSP_SEQ_BUF_PAYLOAD_DELAY_US)   / sizeof(NvU32)) : \
689     (opcode == GSP_SEQ_BUF_OPCODE_REG_STORE)  ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_STORE)  / sizeof(NvU32)) : \
690    /* GSP_SEQ_BUF_OPCODE_CORE_RESET */                                 \
691    /* GSP_SEQ_BUF_OPCODE_CORE_START */                                 \
692    /* GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT */                         \
693    /* GSP_SEQ_BUF_OPCODE_CORE_RESUME */                                \
694    0)
695
696typedef struct {
697    //
698    // Version 1
699    // Version 2
700    // Version 3 = for Partition boot
701    // Version 4 = for eb riscv boot
702    // Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later.
703    //
704    NvU32  version;                         // structure version
705    NvU32  bootloaderOffset;
706    NvU32  bootloaderSize;
707    NvU32  bootloaderParamOffset;
708    NvU32  bootloaderParamSize;
709    NvU32  riscvElfOffset;
710    NvU32  riscvElfSize;
711    NvU32  appVersion;                      // Changelist number associated with the image
712    //
713    // Manifest contains information about Monitor and it is
714    // input to BR
715    //
716    NvU32  manifestOffset;
717    NvU32  manifestSize;
718    //
719    // Monitor Data offset within RISCV image and size
720    //
721    NvU32  monitorDataOffset;
722    NvU32  monitorDataSize;
723    //
724    // Monitor Code offset withtin RISCV image and size
725    //
726    NvU32  monitorCodeOffset;
727    NvU32  monitorCodeSize;
728    NvU32  bIsMonitorEnabled;
729    //
730    // Swbrom Code offset within RISCV image and size
731    //
732    NvU32  swbromCodeOffset;
733    NvU32  swbromCodeSize;
734    //
735    // Swbrom Data offset within RISCV image and size
736    //
737    NvU32  swbromDataOffset;
738    NvU32  swbromDataSize;
739    //
740    // Total size of FB carveout (image and reserved space).  
741    //
742    NvU32  fbReservedSize;
743    //
744    // Indicates whether the entire RISC-V image is signed as "code" in code section.
745    //
746    NvU32  bSignedAsCode;
747} RM_RISCV_UCODE_DESC;
748
749typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
750    NvU16 engineIdx;
751    NvU32 pmcIntrMask;
752    NvU32 vectorStall;
753    NvU32 vectorNonStall;
754} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY;
755
756typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
757    NvU8 subtreeStart;
758    NvU8 subtreeEnd;
759} NV2080_INTR_CATEGORY_SUBTREE_MAP;
760
761#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE       128
762
763typedef enum NV2080_INTR_CATEGORY {
764    NV2080_INTR_CATEGORY_DEFAULT = 0,
765    NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
766    NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
767    NV2080_INTR_CATEGORY_RUNLIST = 3,
768    NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
769    NV2080_INTR_CATEGORY_UVM_OWNED = 5,
770    NV2080_INTR_CATEGORY_UVM_SHARED = 6,
771    NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
772} NV2080_INTR_CATEGORY;
773
774#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
775typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
776    NvU32                                            tableLen;
777    NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
778    NV2080_INTR_CATEGORY_SUBTREE_MAP                 subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
779} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
780
781#define GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB                  (96 << 10)   // All architectures
782
783#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE      ((48 << 10) * 2048)   // Support 2048 channels
784
785typedef union rpc_message_rpc_union_field_v03_00
786{
787    NvU32      spare;
788    NvU32      cpuRmGfid;
789} rpc_message_rpc_union_field_v03_00;
790
791typedef rpc_message_rpc_union_field_v03_00 rpc_message_rpc_union_field_v;
792
793typedef struct rpc_message_header_v03_00
794{
795    NvU32      header_version;
796    NvU32      signature;
797    NvU32      length;
798    NvU32      function;
799    NvU32      rpc_result;
800    NvU32      rpc_result_private;
801    NvU32      sequence;
802    rpc_message_rpc_union_field_v u;
803    rpc_generic_union rpc_message_data[];
804} rpc_message_header_v03_00;
805
806typedef rpc_message_header_v03_00 rpc_message_header_v;
807
808typedef struct GSP_MSG_QUEUE_ELEMENT
809{
810    NvU8  authTagBuffer[16];         // Authentication tag buffer.
811    NvU8  aadBuffer[16];             // AAD buffer.
812    NvU32 checkSum;                  // Set to value needed to make checksum always zero.
813    NvU32 seqNum;                    // Sequence number maintained by the message queue.
814    NvU32 elemCount;                 // Number of message queue elements this message has.
815    NV_DECLARE_ALIGNED(rpc_message_header_v rpc, 8);
816} GSP_MSG_QUEUE_ELEMENT;
817
818#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2                   (0 << 20)   // No FB heap usage
819#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3                  (20 << 20)
820
821#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X               (8 << 20)   // Turing thru Ada
822
823#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB                (64u)
824#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB      (84u)
825#endif