fbsr.h

  1/* SPDX-License-Identifier: MIT */
  2
  3/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
  4
  5#ifndef __NVRM_FBSR_H__
  6#define __NVRM_FBSR_H__
  7#include <nvrm/nvtypes.h>
  8
  9/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
 10
 11#define NV01_MEMORY_LIST_FBMEM  (0x00000082)
 12
 13#define NV01_MEMORY_LIST_SYSTEM (0x00000081)
 14
 15#define NVOS02_FLAGS_PHYSICALITY                                   7:4
 16#define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS                        (0x00000000)
 17#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS                     (0x00000001)
 18#define NVOS02_FLAGS_LOCATION                                      11:8
 19#define NVOS02_FLAGS_LOCATION_PCI                                  (0x00000000)
 20#define NVOS02_FLAGS_LOCATION_AGP                                  (0x00000001)
 21#define NVOS02_FLAGS_LOCATION_VIDMEM                               (0x00000002)
 22#define NVOS02_FLAGS_COHERENCY                                     15:12
 23#define NVOS02_FLAGS_COHERENCY_UNCACHED                            (0x00000000)
 24#define NVOS02_FLAGS_COHERENCY_CACHED                              (0x00000001)
 25#define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE                       (0x00000002)
 26#define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH                       (0x00000003)
 27#define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT                       (0x00000004)
 28#define NVOS02_FLAGS_COHERENCY_WRITE_BACK                          (0x00000005)
 29#define NVOS02_FLAGS_ALLOC                                         17:16
 30#define NVOS02_FLAGS_ALLOC_NONE                                    (0x00000001)
 31#define NVOS02_FLAGS_GPU_CACHEABLE                                 18:18
 32#define NVOS02_FLAGS_GPU_CACHEABLE_NO                              (0x00000000)
 33#define NVOS02_FLAGS_GPU_CACHEABLE_YES                             (0x00000001)
 34#define NVOS02_FLAGS_KERNEL_MAPPING                                19:19
 35#define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP                         (0x00000000)
 36#define NVOS02_FLAGS_KERNEL_MAPPING_MAP                            (0x00000001)
 37#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY                            20:20
 38#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO                         (0x00000000)
 39#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES                        (0x00000001)
 40#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY                          21:21
 41#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO                       (0x00000000)
 42#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES                      (0x00000001)
 43#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY                        22:22
 44#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO                     (0x00000000)
 45#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES                    (0x00000001)
 46#define NVOS02_FLAGS_PEER_MAP_OVERRIDE                             23:23
 47#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT                     (0x00000000)
 48#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED                    (0x00000001)
 49#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT                          24:24
 50#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE                 (0x00000001)
 51#define NVOS02_FLAGS_MEMORY_PROTECTION                             26:25
 52#define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT                     (0x00000000)
 53#define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED                   (0x00000001)
 54#define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED                 (0x00000002)
 55#define NVOS02_FLAGS_MAPPING                                       31:30
 56#define NVOS02_FLAGS_MAPPING_DEFAULT                               (0x00000000)
 57#define NVOS02_FLAGS_MAPPING_NO_MAP                                (0x00000001)
 58#define NVOS02_FLAGS_MAPPING_NEVER_MAP                             (0x00000002)
 59
 60struct pte_desc
 61{
 62    NvU32 idr:2;
 63    NvU32 reserved1:14;
 64    NvU32 length:16;
 65    union {
 66        NvU64 pte; // PTE when IDR==0; PDE when IDR > 0
 67        NvU64 pde; // PTE when IDR==0; PDE when IDR > 0
 68    } pte_pde[]  NV_ALIGN_BYTES(8); // PTE when IDR==0; PDE when IDR > 0
 69};
 70
 71typedef struct rpc_alloc_memory_v13_01
 72{
 73    NvHandle   hClient;
 74    NvHandle   hDevice;
 75    NvHandle   hMemory;
 76    NvU32      hClass;
 77    NvU32      flags;
 78    NvU32      pteAdjust;
 79    NvU32      format;
 80    NvU64      length NV_ALIGN_BYTES(8);
 81    NvU32      pageCount;
 82    struct pte_desc pteDesc;
 83} rpc_alloc_memory_v13_01;
 84
 85#define FBSR_TYPE_DMA                                 4   // Copy using DMA. Fastest.
 86
 87#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */
 88typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
 89    NvU32    fbsrType;
 90    NvU32    numRegions;
 91    NvHandle hClient;
 92    NvHandle hSysMem;
 93    NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
 94    NvBool   bEnteringGcoffState;
 95} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
 96
 97#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
 98typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS {
 99    NvU32    fbsrType;
100    NvHandle hClient;
101    NvHandle hVidMem;
102    NV_DECLARE_ALIGNED(NvU64 vidOffset, 8);
103    NV_DECLARE_ALIGNED(NvU64 sysOffset, 8);
104    NV_DECLARE_ALIGNED(NvU64 size, 8);
105} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS;
106#endif