FILE
disp.h
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linux-6.19.14/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/disp.h
1/* SPDX-License-Identifier: MIT */ 2 3/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 4 5#ifndef __NVRM_DISP_H__ 6#define __NVRM_DISP_H__ 7#include <nvrm/nvtypes.h> 8 9/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 10 11#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */ 12typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS { 13 NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8); 14 NV_DECLARE_ALIGNED(NvU64 instMemSize, 8); 15 NvU32 instMemAddrSpace; 16 NvU32 instMemCpuCacheAttr; 17} NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS; 18 19#define NV_MEMORY_WRITECOMBINED 2 20 21#define NV04_DISPLAY_COMMON (0x00000073) 22 23#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ 24typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { 25 NvU32 feHwSysCap; 26 NvU32 windowPresentMask; 27 NvBool bFbRemapperEnabled; 28 NvU32 numHeads; 29 NvBool bPrimaryVga; 30 NvU32 i2cPort; 31 NvU32 internalDispActiveMask; 32} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; 33 34#define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ 35 36#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ 37typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { 38 NvU32 status; 39 NvU16 backLightDataSize; 40 NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; 41} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; 42 43typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS { 44 NvU32 subDeviceInstance; 45} NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS; 46 47#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */ 48 49#define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ 50typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS { 51 NvU32 subDeviceInstance; 52 NvU32 flags; 53 NvU32 numHeads; 54} NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS; 55 56#define NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK (0x730287U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID" */ 57typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS { 58 NvU32 subDeviceInstance; 59 NvU32 headMask; 60} NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS; 61 62#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */ 63typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS { 64 NvU32 subDeviceInstance; 65 NvU32 displayMask; 66 NvU32 displayMaskDDC; 67} NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS; 68 69#define NV0073_CTRL_MAX_CONNECTORS 4U 70 71#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */ 72typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS { 73 NvU32 subDeviceInstance; 74 NvU32 displayId; 75 NvU32 flags; 76 NvU32 DDCPartners; 77 NvU32 count; 78 struct { 79 NvU32 index; 80 NvU32 type; 81 NvU32 location; 82 } data[NV0073_CTRL_MAX_CONNECTORS]; 83 NvU32 platform; 84} NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS; 85 86#define NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO (0x73028bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID" */ 87typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS { 88 NvU32 subDeviceInstance; 89 NvU32 displayId; 90 NvU32 index; 91 NvU32 type; 92 NvU32 protocol; 93 NvU32 ditherType; 94 NvU32 ditherAlgo; 95 NvU32 location; 96 NvU32 rootPortId; 97 NvU32 dcbIndex; 98 NV_DECLARE_ALIGNED(NvU64 vbiosAddress, 8); 99 NvBool bIsLitByVbios; 100 NvBool bIsDispDynamic; 101} NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS; 102 103#define NV0073_CTRL_SPECIFIC_OR_TYPE_NONE (0x00000000U) 104#define NV0073_CTRL_SPECIFIC_OR_TYPE_DAC (0x00000001U) 105#define NV0073_CTRL_SPECIFIC_OR_TYPE_SOR (0x00000002U) 106#define NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR (0x00000003U) 107#define NV0073_CTRL_SPECIFIC_OR_TYPE_DSI (0x00000005U) 108 109#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT (0x00000000U) 110#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000U) 111#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001U) 112#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002U) 113#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS (0x00000005U) 114#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A (0x00000008U) 115#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B (0x00000009U) 116#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DSI (0x00000010U) 117#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI (0x00000011U) 118#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC (0x00000000U) 119#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN (0xFFFFFFFFU) 120 121#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ 122 123typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS { 124 NvBool bDscSupported; 125 NvU32 encoderColorFormatMask; 126 NvU32 lineBufferSizeKB; 127 NvU32 rateBufferSizeKB; 128 NvU32 bitsPerPixelPrecision; 129 NvU32 maxNumHztSlices; 130 NvU32 lineBufferBitDepth; 131} NV0073_CTRL_CMD_DSC_CAP_PARAMS; 132 133typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { 134 NvU32 subDeviceInstance; 135 NvU32 sorIndex; 136 NvU32 maxLinkRate; 137 NvU32 dpVersionsSupported; 138 NvU32 UHBRSupported; 139 NvBool bIsMultistreamSupported; 140 NvBool bIsSCEnabled; 141 NvBool bHasIncreasedWatermarkLimits; 142 NvBool bIsPC2Disabled; 143 NvBool isSingleHeadMSTSupported; 144 NvBool bFECSupported; 145 NvBool bIsTrainPhyRepeater; 146 NvBool bOverrideLinkBw; 147 NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; 148} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; 149 150#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ 151#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) 152#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 153#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) 154#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) 155#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 156#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) 157#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) 158#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 159#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) 160#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) 161#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U) 162#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) 163#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) 164#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) 165#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) 166#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) 167#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U) 168#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U) 169#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U) 170#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U) 171#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) 172#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) 173 174#define NV2080_NOTIFIERS_HOTPLUG (1) 175 176typedef struct { 177 NvU32 plugDisplayMask; 178 NvU32 unplugDisplayMask; 179} Nv2080HotplugNotification; 180 181#define NV2080_NOTIFIERS_DP_IRQ (7) 182 183typedef struct Nv2080DpIrqNotificationRec { 184 NvU32 displayId; 185} Nv2080DpIrqNotification; 186 187#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730122U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */ 188typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS { 189 NvU32 subDeviceInstance; 190 NvU32 flags; 191 NvU32 displayMask; 192 NvU32 retryTimeMs; 193} NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS; 194 195#define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */ 196typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { 197 NvU32 subDeviceInstance; 198 NvU32 displayId; 199 NvU32 flags; 200 NvU32 flags2; 201} NV0073_CTRL_DFP_GET_INFO_PARAMS; 202 203#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0 204#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U) 205#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U) 206#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U) 207#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U) 208#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U) 209#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U) 210#define NV0073_CTRL_DFP_FLAGS_LANE 5:3 211#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U) 212#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U) 213#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U) 214#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U) 215#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U) 216#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6 217#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U) 218#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U) 219#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7 220#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U) 221#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U) 222#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8 223#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U) 224#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U) 225#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9 226#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U) 227#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U) 228#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10 229#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U) 230#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U) 231#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11 232#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U) 233#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U) 234#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12 235#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U) 236#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U) 237#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14 238#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U) 239#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U) 240#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15 241#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U) 242#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U) 243#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16 244#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U) 245#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U) 246#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17 247#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U) 248#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U) 249#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U) 250#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U) 251#define NV0073_CTRL_DFP_FLAGS_LINK 21:20 252#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U) 253#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U) 254#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U) 255#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22 256#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U) 257#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U) 258#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23 259#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U) 260#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U) 261#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U) 262#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U) 263#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25 264#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U) 265#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U) 266#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26 267#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30 268#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U) 269#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U) 270 271#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x730126U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */ 272typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS { 273 NvU32 subDeviceInstance; 274 NvU32 head; 275 NvU32 flags; 276 NvU32 displayId; 277} NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS; 278 279typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG; 280 281typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO { 282 NvU32 displayMask; 283 NvU32 sorType; 284} NV0073_CTRL_DFP_ASSIGN_SOR_INFO; 285 286#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U 287 288#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */ 289typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS { 290 NvU32 subDeviceInstance; 291 NvU32 displayId; 292 NvU8 sorExcludeMask; 293 NvU32 slaveDisplayId; 294 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig; 295 NvBool bIs2Head1Or; 296 NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; 297 NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS]; 298 NvU8 reservedSorMask; 299 NvU32 flags; 300} NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS; 301 302#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0 303#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U) 304#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U) 305#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1 306#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U) 307#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U) 308 309#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ 310 311#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */ 312 313typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { 314 NvU32 subDeviceInstance; 315 NvU32 displayId; 316 NvU32 brightness; 317 NvBool bUncalibrated; 318} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; 319 320#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */ 321 322#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U 323 324typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS { 325 NvU32 subDeviceInstance; 326 NvU32 displayId; 327 NvU32 numELDSize; 328 NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER]; 329 NvU32 maxFreqSupported; 330 NvU32 ctrl; 331 NvU32 deviceEntry; 332} NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS; 333 334#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0 335#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U) 336#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U) 337#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1 338#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U) 339#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U) 340 341#define NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES 2048U 342 343#define NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 (0x730245U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID" */ 344typedef struct NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS { 345 NvU32 subDeviceInstance; 346 NvU32 displayId; 347 NvU32 bufferSize; 348 NvU32 flags; 349 NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES]; 350} NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS; 351 352#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE (0x730273U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID" */ 353typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS { 354 NvU8 subDeviceInstance; 355 NvU32 displayId; 356 NvU8 enable; 357} NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS; 358 359#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */ 360typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS { 361 NvU32 subDeviceInstance; 362 NvU32 displayId; 363 NvU32 caps; 364} NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS; 365 366#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */ 367#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED 0:0 368#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_FALSE (0x00000000U) 369#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_TRUE (0x00000001U) 370#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED 1:1 371#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_FALSE (0x00000000U) 372#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_TRUE (0x00000001U) 373#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED 2:2 374#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_FALSE (0x00000000U) 375#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_TRUE (0x00000001U) 376#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED 5:3 377#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) 378#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) 379#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) 380#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) 381#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) 382#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) 383#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) 384#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED 6:6 385#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_FALSE (0x00000000U) 386#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_TRUE (0x00000001U) 387#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED 9:7 388#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U) 389#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U) 390#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U) 391#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U) 392#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U) 393#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U) 394#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U) 395 396#define NV0073_CTRL_SET_OD_MAX_PACKET_SIZE 36U 397 398#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET (0x730288U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID" */ 399typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS { 400 NvU32 subDeviceInstance; 401 NvU32 displayId; 402 NvU32 transmitControl; 403 NvU32 packetSize; 404 NvU32 targetHead; 405 NvBool bUsePsrHeadforSdp; 406 NvU8 aPacket[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE]; 407} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS; 408 409#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE 0:0 410#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO (0x0000000U) 411#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES (0x0000001U) 412#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME 1:1 413#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE (0x0000000U) 414#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE (0x0000001U) 415#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME 2:2 416#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE (0x0000000U) 417#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE (0x0000001U) 418#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK 3:3 419#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE (0x0000000U) 420#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE (0x0000001U) 421#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE 4:4 422#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_DISABLE (0x0000000U) 423#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_ENABLE (0x0000001U) 424#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT 5:5 425#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED (0x0000000U) 426#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED (0x0000001U) 427#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY 6:6 428#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE (0x0000000U) 429#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE (0x0000001U) 430#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING 7:7 431#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE (0x0000000U) 432#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE (0x0000001U) 433#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE 9:8 434#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME0 (0x0000000U) 435#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME1 (0x0000001U) 436#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE 31:31 437#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO (0x0000000U) 438#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES (0x0000001U) 439 440#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM (0x730275U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ 441 442typedef struct NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS { 443 NvU8 subDeviceInstance; 444 NvU32 displayId; 445 NvU8 mute; 446} NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS; 447 448#define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U 449 450#define NV0073_CTRL_CMD_DP_AUXCH_CTRL (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */ 451typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS { 452 NvU32 subDeviceInstance; 453 NvU32 displayId; 454 NvBool bAddrOnly; 455 NvU32 cmd; 456 NvU32 addr; 457 NvU8 data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE]; 458 NvU32 size; 459 NvU32 replyType; 460 NvU32 retryTimeMs; 461} NV0073_CTRL_DP_AUXCH_CTRL_PARAMS; 462 463#define NV0073_CTRL_DP_AUXCH_CMD_TYPE 3:3 464#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C (0x00000000U) 465#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX (0x00000001U) 466#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT 2:2 467#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE (0x00000000U) 468#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE (0x00000001U) 469#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE 1:0 470#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE (0x00000000U) 471#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ (0x00000001U) 472#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS (0x00000002U) 473 474#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */ 475 476#define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U 477 478typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { 479 // In 480 NvU32 subDeviceInstance; 481 NvU32 displayId; 482 NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; 483 484 // Out 485 NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; 486 NvU8 linkBwCount; 487} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; 488 489#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */ 490typedef struct NV0073_CTRL_DP_CTRL_PARAMS { 491 NvU32 subDeviceInstance; 492 NvU32 displayId; 493 NvU32 cmd; 494 NvU32 data; 495 NvU32 err; 496 NvU32 retryTimeMs; 497 NvU32 eightLaneDpcdBaseAddr; 498} NV0073_CTRL_DP_CTRL_PARAMS; 499 500#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT 0:0 501#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE (0x00000000U) 502#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE (0x00000001U) 503#define NV0073_CTRL_DP_CMD_SET_LINK_BW 1:1 504#define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE (0x00000000U) 505#define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE (0x00000001U) 506#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD 2:2 507#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE (0x00000000U) 508#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE (0x00000001U) 509#define NV0073_CTRL_DP_CMD_UNUSED 3:3 510#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE 4:4 511#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM (0x00000000U) 512#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM (0x00000001U) 513#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING 5:5 514#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO (0x00000000U) 515#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES (0x00000001U) 516#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING 6:6 517#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO (0x00000000U) 518#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES (0x00000001U) 519#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING 7:7 520#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE (0x00000000U) 521#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE (0x00000001U) 522#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING 8:8 523#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT (0x00000000U) 524#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE (0x00000001U) 525#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING 9:9 526#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) 527#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) 528#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED 10:10 529#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000U) 530#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001U) 531#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING 12:11 532#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) 533#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) 534#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) 535#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER 13:13 536#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO (0x00000000U) 537#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES (0x00000001U) 538#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG 14:14 539#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) 540#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) 541#define NV0073_CTRL_DP_CMD_ENABLE_FEC 15:15 542#define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE (0x00000000U) 543#define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE (0x00000001U) 544#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST 29:29 545#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO (0x00000000U) 546#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES (0x00000001U) 547#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE 30:30 548#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE (0x00000000U) 549#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE (0x00000001U) 550#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG 31:31 551#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE (0x00000000U) 552#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE (0x00000001U) 553#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE 3:0 554#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN (0x00000000U) 555#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U) 556#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK (0x00000002U) 557#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN (0x00000003U) 558#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE (0x00000004U) 559#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK (0x00000005U) 560#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR (0x00000006U) 561#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO (0x00000007U) 562#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO (0x00000008U) 563#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK (0x00000009U) 564#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK (0x00000000U) 565#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING (0x80000001U) 566#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR (0x80000002U) 567#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR (0x80000003U) 568#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR (0x80000004U) 569 570#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT 4:0 571#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 (0x00000000U) 572#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 (0x00000001U) 573#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 (0x00000002U) 574#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 (0x00000004U) 575#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 (0x00000008U) 576#define NV0073_CTRL_DP_DATA_SET_LINK_BW 15:8 577#define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS (0x00000006U) 578#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS (0x00000008U) 579#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS (0x00000009U) 580#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS (0x0000000AU) 581#define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS (0x0000000CU) 582#define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS (0x00000010U) 583#define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS (0x00000014U) 584#define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS (0x0000001EU) 585#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING 18:18 586#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO (0x00000000U) 587#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES (0x00000001U) 588#define NV0073_CTRL_DP_DATA_TARGET 22:19 589#define NV0073_CTRL_DP_DATA_TARGET_SINK (0x00000000U) 590#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0 (0x00000001U) 591#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1 (0x00000002U) 592#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2 (0x00000003U) 593#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3 (0x00000004U) 594#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4 (0x00000005U) 595#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5 (0x00000006U) 596#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6 (0x00000007U) 597#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7 (0x00000008U) 598 599#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */ 600 601#define NV0073_CTRL_MAX_LANES 8U 602 603typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { 604 NvU32 subDeviceInstance; 605 NvU32 displayId; 606 NvU32 numLanes; 607 NvU32 data[NV0073_CTRL_MAX_LANES]; 608} NV0073_CTRL_DP_LANE_DATA_PARAMS; 609 610#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS 1:0 611#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE (0x00000000U) 612#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 (0x00000001U) 613#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 (0x00000002U) 614#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 (0x00000003U) 615#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT 3:2 616#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U) 617#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U) 618#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U) 619#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U) 620 621#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */ 622 623typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS { 624 NvU32 subDeviceInstance; 625 NvU32 displayId; 626 NvU32 preferredDisplayId; 627 628 NvBool force; 629 NvBool useBFM; 630 631 NvU32 displayIdAssigned; 632 NvU32 allDisplayMask; 633} NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS; 634 635#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */ 636 637typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS { 638 NvU32 subDeviceInstance; 639 NvU32 displayId; 640} NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS; 641 642#define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */ 643 644typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { 645 NvU32 subDeviceInstance; 646 NvU32 head; 647 NvU32 sorIndex; 648 NvU32 dpLink; 649 650 NvBool bEnableOverride; 651 NvBool bMST; 652 NvU32 singleHeadMultistreamMode; 653 NvU32 hBlankSym; 654 NvU32 vBlankSym; 655 NvU32 colorFormat; 656 NvBool bEnableTwoHeadOneOr; 657 658 struct { 659 NvU32 slotStart; 660 NvU32 slotEnd; 661 NvU32 PBN; 662 NvU32 Timeslice; 663 NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT 664 NvU32 singleHeadMSTPipeline; 665 NvBool bEnableAudioOverRightPanel; 666 } MST; 667 668 struct { 669 NvBool bEnhancedFraming; 670 NvU32 tuSize; 671 NvU32 waterMark; 672 NvU32 actualPclkHz; // deprecated -Use MvidWarParams 673 NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams 674 NvBool bEnableAudioOverRightPanel; 675 struct { 676 NvU32 activeCnt; 677 NvU32 activeFrac; 678 NvU32 activePolarity; 679 NvBool mvidWarEnabled; 680 struct { 681 NvU32 actualPclkHz; 682 NvU32 linkClkFreqHz; 683 } MvidWarParams; 684 } Legacy; 685 } SST; 686} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS; 687 688#define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */ 689typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS { 690 NvU32 subDeviceInstance; 691 NvU32 displayId; 692 NvBool enable; 693} NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS; 694 695#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ 696typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS { 697 NvU32 subDeviceInstance; 698 NvU32 displayId; 699 NvU32 mute; 700} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS; 701 702#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ 703typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { 704 NvU32 addressSpace; 705 NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8); 706 NV_DECLARE_ALIGNED(NvU64 limit, 8); 707 NvU32 cacheSnoop; 708 NvU32 hclass; 709 NvU32 channelInstance; 710 NvBool valid; 711} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; 712 713#define ADDR_SYSMEM (1) // System memory (PCI) 714 715#define ADDR_FBMEM 2 // Frame buffer memory space 716 717typedef struct 718{ 719 NvV32 channelInstance; // One of the n channel instances of a given channel type. 720 // All PIO channels have two instances (one per head). 721 NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors. 722 NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel 723} NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS; 724 725typedef struct 726{ 727 NvV32 channelInstance; // One of the n channel instances of a given channel type. 728 // Note that core channel has only one instance 729 // while all others have two (one per head). 730 NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer 731 NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications 732 NvU32 offset; // Initial offset for put/get, usually zero. 733 NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs 734 735 NvU32 flags; 736#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1 737#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000 738#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001 739 740} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS; 741#endif
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