ga102.c

  1/*
  2 * Copyright 2021 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22#include "priv.h"
 23
 24#include <nvfw/flcn.h>
 25#include <nvfw/fw.h>
 26#include <nvfw/hs.h>
 27
 28int
 29ga102_gsp_reset(struct nvkm_gsp *gsp)
 30{
 31	int ret;
 32
 33	ret = gsp->falcon.func->reset_eng(&gsp->falcon);
 34	if (ret)
 35		return ret;
 36
 37	nvkm_falcon_mask(&gsp->falcon, 0x1668, 0x00000111, 0x00000111);
 38	return 0;
 39}
 40
 41int
 42ga102_gsp_booter_ctor(struct nvkm_gsp *gsp, const char *name, const struct firmware *blob,
 43		      struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw)
 44{
 45	struct nvkm_subdev *subdev = &gsp->subdev;
 46	const struct nvkm_falcon_fw_func *func = &ga102_flcn_fw;
 47	const struct nvfw_bin_hdr *hdr;
 48	const struct nvfw_hs_header_v2 *hshdr;
 49	const struct nvfw_hs_load_header_v2 *lhdr;
 50	u32 loc, sig, cnt, *meta;
 51	int ret;
 52
 53	hdr = nvfw_bin_hdr(subdev, blob->data);
 54	hshdr = nvfw_hs_header_v2(subdev, blob->data + hdr->header_offset);
 55	meta = (u32 *)(blob->data + hshdr->meta_data_offset);
 56	loc = *(u32 *)(blob->data + hshdr->patch_loc);
 57	sig = *(u32 *)(blob->data + hshdr->patch_sig);
 58	cnt = *(u32 *)(blob->data + hshdr->num_sig);
 59
 60	ret = nvkm_falcon_fw_ctor(func, name, subdev->device, true,
 61				  blob->data + hdr->data_offset, hdr->data_size, falcon, fw);
 62	if (ret)
 63		goto done;
 64
 65	ret = nvkm_falcon_fw_sign(fw, loc, hshdr->sig_prod_size / cnt, blob->data,
 66				  cnt, hshdr->sig_prod_offset + sig, 0, 0);
 67	if (ret)
 68		goto done;
 69
 70	lhdr = nvfw_hs_load_header_v2(subdev, blob->data + hshdr->header_offset);
 71
 72	fw->imem_base_img = lhdr->app[0].offset;
 73	fw->imem_base = 0;
 74	fw->imem_size = lhdr->app[0].size;
 75
 76	fw->dmem_base_img = lhdr->os_data_offset;
 77	fw->dmem_base = 0;
 78	fw->dmem_size = lhdr->os_data_size;
 79	fw->dmem_sign = loc - lhdr->os_data_offset;
 80
 81	fw->boot_addr = lhdr->app[0].offset;
 82
 83	fw->fuse_ver = meta[0];
 84	fw->engine_id = meta[1];
 85	fw->ucode_id = meta[2];
 86
 87done:
 88	if (ret)
 89		nvkm_falcon_fw_dtor(fw);
 90
 91	return ret;
 92}
 93
 94static int
 95ga102_gsp_fwsec_signature(struct nvkm_falcon_fw *fw, u32 *src_base_src)
 96{
 97	struct nvkm_falcon *falcon = fw->falcon;
 98	struct nvkm_device *device = falcon->owner->device;
 99	u32 sig_fuse_version = fw->fuse_ver;
100	u32 reg_fuse_version;
101	int idx = 0;
102
103	FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id);
104	FLCN_DBG(falcon, "sig_fuse_version: %08x", sig_fuse_version);
105
106	if (fw->engine_id & 0x00000400) {
107		reg_fuse_version = nvkm_rd32(device, 0x8241c0 + (fw->ucode_id - 1) * 4);
108	} else {
109		WARN_ON(1);
110		return -ENOSYS;
111	}
112
113	FLCN_DBG(falcon, "reg_fuse_version: %08x", reg_fuse_version);
114	reg_fuse_version = BIT(fls(reg_fuse_version));
115	FLCN_DBG(falcon, "reg_fuse_version: %08x", reg_fuse_version);
116	if (!(reg_fuse_version & fw->fuse_ver))
117		return -EINVAL;
118
119	while (!(reg_fuse_version & sig_fuse_version & 1)) {
120		idx += (sig_fuse_version & 1);
121		reg_fuse_version >>= 1;
122		sig_fuse_version >>= 1;
123	}
124
125	return idx;
126}
127
128const struct nvkm_falcon_fw_func
129ga102_gsp_fwsec = {
130	.signature = ga102_gsp_fwsec_signature,
131	.reset = gm200_flcn_fw_reset,
132	.load = ga102_flcn_fw_load,
133	.boot = ga102_flcn_fw_boot,
134};
135
136const struct nvkm_falcon_func
137ga102_gsp_flcn = {
138	.disable = gm200_flcn_disable,
139	.enable = gm200_flcn_enable,
140	.select = ga102_flcn_select,
141	.addr2 = 0x1000,
142	.riscv_irqmask = 0x528,
143	.reset_eng = gp102_flcn_reset_eng,
144	.reset_prep = ga102_flcn_reset_prep,
145	.reset_wait_mem_scrubbing = ga102_flcn_reset_wait_mem_scrubbing,
146	.imem_dma = &ga102_flcn_dma,
147	.dmem_dma = &ga102_flcn_dma,
148	.riscv_active = ga102_flcn_riscv_active,
149	.intr_retrigger = ga100_flcn_intr_retrigger,
150};
151
152static const struct nvkm_gsp_func
153ga102_gsp_r535 = {
154	.flcn = &ga102_gsp_flcn,
155	.fwsec = &ga102_gsp_fwsec,
156
157	.sig_section = ".fwsignature_ga10x",
158
159	.booter.ctor = ga102_gsp_booter_ctor,
160
161	.fwsec_sb.ctor = tu102_gsp_fwsec_sb_ctor,
162	.fwsec_sb.dtor = tu102_gsp_fwsec_sb_dtor,
163
164	.dtor = r535_gsp_dtor,
165	.oneinit = tu102_gsp_oneinit,
166	.init = tu102_gsp_init,
167	.fini = tu102_gsp_fini,
168	.reset = ga102_gsp_reset,
169
170	.rm.gpu = &ga1xx_gpu,
171};
172
173static const struct nvkm_gsp_func
174ga102_gsp = {
175	.flcn = &ga102_gsp_flcn,
176};
177
178static struct nvkm_gsp_fwif
179ga102_gsps[] = {
180	{  1, tu102_gsp_load, &ga102_gsp_r535, &r570_rm_ga102, "570.144" },
181	{  0, tu102_gsp_load, &ga102_gsp_r535, &r535_rm_ga102, "535.113.01" },
182	{ -1, gv100_gsp_nofw, &ga102_gsp },
183	{}
184};
185
186int
187ga102_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
188	      struct nvkm_gsp **pgsp)
189{
190	return nvkm_gsp_new_(ga102_gsps, device, type, inst, pgsp);
191}
192
193NVKM_GSP_FIRMWARE_BOOTER(ga102, 535.113.01);
194NVKM_GSP_FIRMWARE_BOOTER(ga103, 535.113.01);
195NVKM_GSP_FIRMWARE_BOOTER(ga104, 535.113.01);
196NVKM_GSP_FIRMWARE_BOOTER(ga106, 535.113.01);
197NVKM_GSP_FIRMWARE_BOOTER(ga107, 535.113.01);
198
199NVKM_GSP_FIRMWARE_BOOTER(ga102, 570.144);
200NVKM_GSP_FIRMWARE_BOOTER(ga103, 570.144);
201NVKM_GSP_FIRMWARE_BOOTER(ga104, 570.144);
202NVKM_GSP_FIRMWARE_BOOTER(ga106, 570.144);
203NVKM_GSP_FIRMWARE_BOOTER(ga107, 570.144);