ramgk104.c

   1/*
   2 * Copyright 2013 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#define gk104_ram(p) container_of((p), struct gk104_ram, base)
  25#include "ram.h"
  26#include "ramfuc.h"
  27
  28#include <core/option.h>
  29#include <subdev/bios.h>
  30#include <subdev/bios/init.h>
  31#include <subdev/bios/M0205.h>
  32#include <subdev/bios/M0209.h>
  33#include <subdev/bios/pll.h>
  34#include <subdev/bios/rammap.h>
  35#include <subdev/bios/timing.h>
  36#include <subdev/clk.h>
  37#include <subdev/clk/pll.h>
  38#include <subdev/gpio.h>
  39
  40struct gk104_ramfuc {
  41	struct ramfuc base;
  42
  43	struct nvbios_pll refpll;
  44	struct nvbios_pll mempll;
  45
  46	struct ramfuc_reg r_gpioMV;
  47	u32 r_funcMV[2];
  48	struct ramfuc_reg r_gpio2E;
  49	u32 r_func2E[2];
  50	struct ramfuc_reg r_gpiotrig;
  51
  52	struct ramfuc_reg r_0x132020;
  53	struct ramfuc_reg r_0x132028;
  54	struct ramfuc_reg r_0x132024;
  55	struct ramfuc_reg r_0x132030;
  56	struct ramfuc_reg r_0x132034;
  57	struct ramfuc_reg r_0x132000;
  58	struct ramfuc_reg r_0x132004;
  59	struct ramfuc_reg r_0x132040;
  60
  61	struct ramfuc_reg r_0x10f248;
  62	struct ramfuc_reg r_0x10f290;
  63	struct ramfuc_reg r_0x10f294;
  64	struct ramfuc_reg r_0x10f298;
  65	struct ramfuc_reg r_0x10f29c;
  66	struct ramfuc_reg r_0x10f2a0;
  67	struct ramfuc_reg r_0x10f2a4;
  68	struct ramfuc_reg r_0x10f2a8;
  69	struct ramfuc_reg r_0x10f2ac;
  70	struct ramfuc_reg r_0x10f2cc;
  71	struct ramfuc_reg r_0x10f2e8;
  72	struct ramfuc_reg r_0x10f250;
  73	struct ramfuc_reg r_0x10f24c;
  74	struct ramfuc_reg r_0x10fec4;
  75	struct ramfuc_reg r_0x10fec8;
  76	struct ramfuc_reg r_0x10f604;
  77	struct ramfuc_reg r_0x10f614;
  78	struct ramfuc_reg r_0x10f610;
  79	struct ramfuc_reg r_0x100770;
  80	struct ramfuc_reg r_0x100778;
  81	struct ramfuc_reg r_0x10f224;
  82
  83	struct ramfuc_reg r_0x10f870;
  84	struct ramfuc_reg r_0x10f698;
  85	struct ramfuc_reg r_0x10f694;
  86	struct ramfuc_reg r_0x10f6b8;
  87	struct ramfuc_reg r_0x10f808;
  88	struct ramfuc_reg r_0x10f670;
  89	struct ramfuc_reg r_0x10f60c;
  90	struct ramfuc_reg r_0x10f830;
  91	struct ramfuc_reg r_0x1373ec;
  92	struct ramfuc_reg r_0x10f800;
  93	struct ramfuc_reg r_0x10f82c;
  94
  95	struct ramfuc_reg r_0x10f978;
  96	struct ramfuc_reg r_0x10f910;
  97	struct ramfuc_reg r_0x10f914;
  98
  99	struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
 100
 101	struct ramfuc_reg r_0x62c000;
 102
 103	struct ramfuc_reg r_0x10f200;
 104
 105	struct ramfuc_reg r_0x10f210;
 106	struct ramfuc_reg r_0x10f310;
 107	struct ramfuc_reg r_0x10f314;
 108	struct ramfuc_reg r_0x10f318;
 109	struct ramfuc_reg r_0x10f090;
 110	struct ramfuc_reg r_0x10f69c;
 111	struct ramfuc_reg r_0x10f824;
 112	struct ramfuc_reg r_0x1373f0;
 113	struct ramfuc_reg r_0x1373f4;
 114	struct ramfuc_reg r_0x137320;
 115	struct ramfuc_reg r_0x10f65c;
 116	struct ramfuc_reg r_0x10f6bc;
 117	struct ramfuc_reg r_0x100710;
 118	struct ramfuc_reg r_0x100750;
 119};
 120
 121struct gk104_ram {
 122	struct nvkm_ram base;
 123	struct gk104_ramfuc fuc;
 124
 125	struct list_head cfg;
 126	u32 parts;
 127	u32 pmask;
 128	u32 pnuts;
 129
 130	struct nvbios_ramcfg diff;
 131	int from;
 132	int mode;
 133	int N1, fN1, M1, P1;
 134	int N2, M2, P2;
 135};
 136
 137/*******************************************************************************
 138 * GDDR5
 139 ******************************************************************************/
 140static void
 141gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data)
 142{
 143	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
 144	u32 addr = 0x110974, i;
 145
 146	ram_mask(fuc, 0x10f910, mask, data);
 147	ram_mask(fuc, 0x10f914, mask, data);
 148
 149	for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
 150		if (ram->pmask & (1 << i))
 151			continue;
 152		ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
 153	}
 154}
 155
 156static void
 157r1373f4_init(struct gk104_ramfuc *fuc)
 158{
 159	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
 160	const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
 161	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
 162	const u32 runk0 = ram->fN1 << 16;
 163	const u32 runk1 = ram->fN1;
 164
 165	if (ram->from == 2) {
 166		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
 167		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
 168	} else {
 169		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
 170	}
 171
 172	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
 173	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
 174
 175	/* (re)program refpll, if required */
 176	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
 177	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
 178		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
 179		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
 180		ram_wr32(fuc, 0x137320, 0x00000000);
 181		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
 182		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
 183		ram_wr32(fuc, 0x132024, rcoef);
 184		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
 185		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
 186		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
 187		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
 188	}
 189
 190	/* (re)program mempll, if required */
 191	if (ram->mode == 2) {
 192		ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
 193		ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
 194		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
 195		ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
 196		ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
 197		ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
 198		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
 199	} else {
 200		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
 201	}
 202
 203	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
 204}
 205
 206static void
 207r1373f4_fini(struct gk104_ramfuc *fuc)
 208{
 209	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
 210	struct nvkm_ram_data *next = ram->base.next;
 211	u8 v0 = next->bios.ramcfg_11_03_c0;
 212	u8 v1 = next->bios.ramcfg_11_03_30;
 213	u32 tmp;
 214
 215	tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
 216	ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
 217	ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
 218	if (ram->mode == 2) {
 219		ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000002);
 220		ram_mask(fuc, 0x1373f4, 0x00001100, 0x00000000);
 221	} else {
 222		ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
 223		ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
 224	}
 225	ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
 226}
 227
 228static void
 229gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
 230	       u32 _mask, u32 _data, u32 _copy)
 231{
 232	struct nvkm_fb *fb = ram->base.fb;
 233	struct ramfuc *fuc = &ram->fuc.base;
 234	struct nvkm_device *device = fb->subdev.device;
 235	u32 addr = 0x110000 + (reg->addr & 0xfff);
 236	u32 mask = _mask | _copy;
 237	u32 data = (_data & _mask) | (reg->data & _copy);
 238	u32 i;
 239
 240	for (i = 0; i < 16; i++, addr += 0x1000) {
 241		if (ram->pnuts & (1 << i)) {
 242			u32 prev = nvkm_rd32(device, addr);
 243			u32 next = (prev & ~mask) | data;
 244			nvkm_memx_wr32(fuc->memx, addr, next);
 245		}
 246	}
 247}
 248#define ram_nuts(s,r,m,d,c)                                                    \
 249	gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
 250
 251static int
 252gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq)
 253{
 254	struct gk104_ramfuc *fuc = &ram->fuc;
 255	struct nvkm_ram_data *next = ram->base.next;
 256	int vc = !next->bios.ramcfg_11_02_08;
 257	int mv = !next->bios.ramcfg_11_02_04;
 258	u32 mask, data;
 259
 260	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
 261	ram_block(fuc);
 262
 263	if (ram->base.fb->subdev.device->disp)
 264		ram_wr32(fuc, 0x62c000, 0x0f0f0000);
 265
 266	/* MR1: turn termination on early, for some reason.. */
 267	if ((ram->base.mr[1] & 0x03c) != 0x030) {
 268		ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
 269		ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
 270	}
 271
 272	if (vc == 1 && ram_have(fuc, gpio2E)) {
 273		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
 274		if (temp != ram_rd32(fuc, gpio2E)) {
 275			ram_wr32(fuc, gpiotrig, 1);
 276			ram_nsec(fuc, 20000);
 277		}
 278	}
 279
 280	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
 281
 282	gk104_ram_train(fuc, 0x01020000, 0x000c0000);
 283
 284	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
 285	ram_nsec(fuc, 1000);
 286	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
 287	ram_nsec(fuc, 1000);
 288
 289	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
 290	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
 291	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
 292	ram_wr32(fuc, 0x10f090, 0x00000061);
 293	ram_wr32(fuc, 0x10f090, 0xc000007f);
 294	ram_nsec(fuc, 1000);
 295
 296	ram_wr32(fuc, 0x10f698, 0x00000000);
 297	ram_wr32(fuc, 0x10f69c, 0x00000000);
 298
 299	/*XXX: there does appear to be some kind of condition here, simply
 300	 *     modifying these bits in the vbios from the default pl0
 301	 *     entries shows no change.  however, the data does appear to
 302	 *     be correct and may be required for the transition back
 303	 */
 304	mask = 0x800f07e0;
 305	data = 0x00030000;
 306	if (ram_rd32(fuc, 0x10f978) & 0x00800000)
 307		data |= 0x00040000;
 308
 309	if (1) {
 310		data |= 0x800807e0;
 311		switch (next->bios.ramcfg_11_03_c0) {
 312		case 3: data &= ~0x00000040; break;
 313		case 2: data &= ~0x00000100; break;
 314		case 1: data &= ~0x80000000; break;
 315		case 0: data &= ~0x00000400; break;
 316		}
 317
 318		switch (next->bios.ramcfg_11_03_30) {
 319		case 3: data &= ~0x00000020; break;
 320		case 2: data &= ~0x00000080; break;
 321		case 1: data &= ~0x00080000; break;
 322		case 0: data &= ~0x00000200; break;
 323		}
 324	}
 325
 326	if (next->bios.ramcfg_11_02_80)
 327		mask |= 0x03000000;
 328	if (next->bios.ramcfg_11_02_40)
 329		mask |= 0x00002000;
 330	if (next->bios.ramcfg_11_07_10)
 331		mask |= 0x00004000;
 332	if (next->bios.ramcfg_11_07_08)
 333		mask |= 0x00000003;
 334	else {
 335		mask |= 0x34000000;
 336		if (ram_rd32(fuc, 0x10f978) & 0x00800000)
 337			mask |= 0x40000000;
 338	}
 339	ram_mask(fuc, 0x10f824, mask, data);
 340
 341	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
 342
 343	if (ram->from == 2 && ram->mode != 2) {
 344		ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
 345		ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
 346		ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
 347		ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
 348		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
 349		r1373f4_init(fuc);
 350		ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
 351		r1373f4_fini(fuc);
 352		ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
 353	} else
 354	if (ram->from != 2 && ram->mode != 2) {
 355		r1373f4_init(fuc);
 356		r1373f4_fini(fuc);
 357	}
 358
 359	if (ram_have(fuc, gpioMV)) {
 360		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
 361		if (temp != ram_rd32(fuc, gpioMV)) {
 362			ram_wr32(fuc, gpiotrig, 1);
 363			ram_nsec(fuc, 64000);
 364		}
 365	}
 366
 367	if (next->bios.ramcfg_11_02_40 ||
 368	    next->bios.ramcfg_11_07_10) {
 369		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
 370		ram_nsec(fuc, 20000);
 371	}
 372
 373	if (ram->from != 2 && ram->mode == 2) {
 374		if (0 /*XXX: Titan */)
 375			ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
 376		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
 377		ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
 378		ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
 379		r1373f4_init(fuc);
 380		r1373f4_fini(fuc);
 381		ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
 382		ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
 383	} else
 384	if (ram->from == 2 && ram->mode == 2) {
 385		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
 386		r1373f4_init(fuc);
 387		r1373f4_fini(fuc);
 388	}
 389
 390	if (ram->mode != 2) /*XXX*/ {
 391		if (next->bios.ramcfg_11_07_40)
 392			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
 393	}
 394
 395	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
 396	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
 397	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
 398
 399	if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
 400		ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
 401		ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
 402	} else
 403	if (!next->bios.ramcfg_11_07_08) {
 404		ram_wr32(fuc, 0x10f698, 0x00000000);
 405		ram_wr32(fuc, 0x10f69c, 0x00000000);
 406	}
 407
 408	if (ram->mode != 2) {
 409		u32 data = 0x01000100 * next->bios.ramcfg_11_04;
 410		ram_nuke(fuc, 0x10f694);
 411		ram_mask(fuc, 0x10f694, 0xff00ff00, data);
 412	}
 413
 414	if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
 415		data = 0x00000080;
 416	else
 417		data = 0x00000000;
 418	ram_mask(fuc, 0x10f60c, 0x00000080, data);
 419
 420	mask = 0x00070000;
 421	data = 0x00000000;
 422	if (!next->bios.ramcfg_11_02_80)
 423		data |= 0x03000000;
 424	if (!next->bios.ramcfg_11_02_40)
 425		data |= 0x00002000;
 426	if (!next->bios.ramcfg_11_07_10)
 427		data |= 0x00004000;
 428	if (!next->bios.ramcfg_11_07_08)
 429		data |= 0x00000003;
 430	else
 431		data |= 0x74000000;
 432	ram_mask(fuc, 0x10f824, mask, data);
 433
 434	if (next->bios.ramcfg_11_01_08)
 435		data = 0x00000000;
 436	else
 437		data = 0x00001000;
 438	ram_mask(fuc, 0x10f200, 0x00001000, data);
 439
 440	if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
 441		ram_nsec(fuc, 10000);
 442		ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
 443	}
 444
 445	if (next->bios.ramcfg_11_08_01)
 446		data = 0x00100000;
 447	else
 448		data = 0x00000000;
 449	ram_mask(fuc, 0x10f82c, 0x00100000, data);
 450
 451	data = 0x00000000;
 452	if (next->bios.ramcfg_11_08_08)
 453		data |= 0x00002000;
 454	if (next->bios.ramcfg_11_08_04)
 455		data |= 0x00001000;
 456	if (next->bios.ramcfg_11_08_02)
 457		data |= 0x00004000;
 458	ram_mask(fuc, 0x10f830, 0x00007000, data);
 459
 460	/* PFB timing */
 461	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
 462	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
 463	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
 464	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
 465	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
 466	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
 467	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
 468	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
 469	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
 470	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
 471	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
 472
 473	data = mask = 0x00000000;
 474	if (ram->diff.ramcfg_11_08_20) {
 475		if (next->bios.ramcfg_11_08_20)
 476			data |= 0x01000000;
 477		mask |= 0x01000000;
 478	}
 479	ram_mask(fuc, 0x10f200, mask, data);
 480
 481	data = mask = 0x00000000;
 482	if (ram->diff.ramcfg_11_02_03) {
 483		data |= next->bios.ramcfg_11_02_03 << 8;
 484		mask |= 0x00000300;
 485	}
 486	if (ram->diff.ramcfg_11_01_10) {
 487		if (next->bios.ramcfg_11_01_10)
 488			data |= 0x70000000;
 489		mask |= 0x70000000;
 490	}
 491	ram_mask(fuc, 0x10f604, mask, data);
 492
 493	data = mask = 0x00000000;
 494	if (ram->diff.timing_20_30_07) {
 495		data |= next->bios.timing_20_30_07 << 28;
 496		mask |= 0x70000000;
 497	}
 498	if (ram->diff.ramcfg_11_01_01) {
 499		if (next->bios.ramcfg_11_01_01)
 500			data |= 0x00000100;
 501		mask |= 0x00000100;
 502	}
 503	ram_mask(fuc, 0x10f614, mask, data);
 504
 505	data = mask = 0x00000000;
 506	if (ram->diff.timing_20_30_07) {
 507		data |= next->bios.timing_20_30_07 << 28;
 508		mask |= 0x70000000;
 509	}
 510	if (ram->diff.ramcfg_11_01_02) {
 511		if (next->bios.ramcfg_11_01_02)
 512			data |= 0x00000100;
 513		mask |= 0x00000100;
 514	}
 515	ram_mask(fuc, 0x10f610, mask, data);
 516
 517	mask = 0x33f00000;
 518	data = 0x00000000;
 519	if (!next->bios.ramcfg_11_01_04)
 520		data |= 0x20200000;
 521	if (!next->bios.ramcfg_11_07_80)
 522		data |= 0x12800000;
 523	/*XXX: see note above about there probably being some condition
 524	 *     for the 10f824 stuff that uses ramcfg 3...
 525	 */
 526	if (next->bios.ramcfg_11_03_f0) {
 527		if (next->bios.rammap_11_08_0c) {
 528			if (!next->bios.ramcfg_11_07_80)
 529				mask |= 0x00000020;
 530			else
 531				data |= 0x00000020;
 532			mask |= 0x00000004;
 533		}
 534	} else {
 535		mask |= 0x40000020;
 536		data |= 0x00000004;
 537	}
 538
 539	ram_mask(fuc, 0x10f808, mask, data);
 540
 541	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
 542
 543	data = mask = 0x00000000;
 544	if (ram->diff.ramcfg_11_02_03) {
 545		data |= next->bios.ramcfg_11_02_03;
 546		mask |= 0x00000003;
 547	}
 548	if (ram->diff.ramcfg_11_01_10) {
 549		if (next->bios.ramcfg_11_01_10)
 550			data |= 0x00000004;
 551		mask |= 0x00000004;
 552	}
 553
 554	if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
 555		ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
 556		ram_wr32(fuc, 0x100710, 0x00000000);
 557		ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
 558	}
 559
 560	data = next->bios.timing_20_30_07 << 8;
 561	if (next->bios.ramcfg_11_01_01)
 562		data |= 0x80000000;
 563	ram_mask(fuc, 0x100778, 0x00000700, data);
 564
 565	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
 566	data = (next->bios.timing[10] & 0x7f000000) >> 24;
 567	if (data < next->bios.timing_20_2c_1fc0)
 568		data = next->bios.timing_20_2c_1fc0;
 569	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
 570	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
 571
 572	ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
 573					    next->bios.timing_20_31_0780 << 17 |
 574					    next->bios.timing_20_31_0078 << 8 |
 575					    next->bios.timing_20_31_0007);
 576	ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
 577					    next->bios.timing_20_31_7000);
 578
 579	ram_wr32(fuc, 0x10f090, 0x4000007e);
 580	ram_nsec(fuc, 2000);
 581	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
 582	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
 583	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
 584
 585	if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
 586		u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
 587		gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
 588		ram_nsec(fuc, 1000);
 589		ram_wr32(fuc, 0x10f294, temp);
 590	}
 591
 592	ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
 593	ram_wr32(fuc, mr[0], ram->base.mr[0]);
 594	ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
 595	ram_nsec(fuc, 1000);
 596	ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
 597	ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
 598	ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
 599	ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
 600
 601	if (vc == 0 && ram_have(fuc, gpio2E)) {
 602		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
 603		if (temp != ram_rd32(fuc, gpio2E)) {
 604			ram_wr32(fuc, gpiotrig, 1);
 605			ram_nsec(fuc, 20000);
 606		}
 607	}
 608
 609	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
 610	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
 611	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
 612	ram_nsec(fuc, 1000);
 613	ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
 614
 615	data  = ram_rd32(fuc, 0x10f978);
 616	data &= ~0x00046144;
 617	data |=  0x0000000b;
 618	if (!next->bios.ramcfg_11_07_08) {
 619		if (!next->bios.ramcfg_11_07_04)
 620			data |= 0x0000200c;
 621		else
 622			data |= 0x00000000;
 623	} else {
 624		data |= 0x00040044;
 625	}
 626	ram_wr32(fuc, 0x10f978, data);
 627
 628	if (ram->mode == 1) {
 629		data = ram_rd32(fuc, 0x10f830) | 0x00000001;
 630		ram_wr32(fuc, 0x10f830, data);
 631	}
 632
 633	if (!next->bios.ramcfg_11_07_08) {
 634		data = 0x88020000;
 635		if ( next->bios.ramcfg_11_07_04)
 636			data |= 0x10000000;
 637		if (!next->bios.rammap_11_08_10)
 638			data |= 0x00080000;
 639	} else {
 640		data = 0xa40e0000;
 641	}
 642	gk104_ram_train(fuc, 0xbc0f0000, data);
 643	if (1) /* XXX: not always? */
 644		ram_nsec(fuc, 1000);
 645
 646	if (ram->mode == 2) { /*XXX*/
 647		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
 648	}
 649
 650	/* LP3 */
 651	if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
 652		ram_nsec(fuc, 1000);
 653
 654	if (ram->mode != 2) {
 655		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
 656		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
 657	}
 658
 659	if (next->bios.ramcfg_11_07_02)
 660		gk104_ram_train(fuc, 0x80020000, 0x01000000);
 661
 662	ram_unblock(fuc);
 663
 664	if (ram->base.fb->subdev.device->disp)
 665		ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
 666
 667	if (next->bios.rammap_11_08_01)
 668		data = 0x00000800;
 669	else
 670		data = 0x00000000;
 671	ram_mask(fuc, 0x10f200, 0x00000800, data);
 672	ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
 673	return 0;
 674}
 675
 676/*******************************************************************************
 677 * DDR3
 678 ******************************************************************************/
 679
 680static void
 681nvkm_sddr3_dll_reset(struct gk104_ramfuc *fuc)
 682{
 683	ram_nuke(fuc, mr[0]);
 684	ram_mask(fuc, mr[0], 0x100, 0x100);
 685	ram_mask(fuc, mr[0], 0x100, 0x000);
 686}
 687
 688static void
 689nvkm_sddr3_dll_disable(struct gk104_ramfuc *fuc)
 690{
 691	u32 mr1_old = ram_rd32(fuc, mr[1]);
 692
 693	if (!(mr1_old & 0x1)) {
 694		ram_mask(fuc, mr[1], 0x1, 0x1);
 695		ram_nsec(fuc, 1000);
 696	}
 697}
 698
 699static int
 700gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq)
 701{
 702	struct gk104_ramfuc *fuc = &ram->fuc;
 703	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
 704	const u32 runk0 = ram->fN1 << 16;
 705	const u32 runk1 = ram->fN1;
 706	struct nvkm_ram_data *next = ram->base.next;
 707	int vc = !next->bios.ramcfg_11_02_08;
 708	int mv = !next->bios.ramcfg_11_02_04;
 709	u32 mask, data;
 710
 711	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
 712	ram_block(fuc);
 713
 714	if (ram->base.fb->subdev.device->disp)
 715		ram_wr32(fuc, 0x62c000, 0x0f0f0000);
 716
 717	if (vc == 1 && ram_have(fuc, gpio2E)) {
 718		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
 719		if (temp != ram_rd32(fuc, gpio2E)) {
 720			ram_wr32(fuc, gpiotrig, 1);
 721			ram_nsec(fuc, 20000);
 722		}
 723	}
 724
 725	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
 726	if (next->bios.ramcfg_11_03_f0)
 727		ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
 728
 729	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
 730
 731	if (next->bios.ramcfg_DLLoff)
 732		nvkm_sddr3_dll_disable(fuc);
 733
 734	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
 735	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
 736	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
 737	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
 738	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
 739	ram_nsec(fuc, 1000);
 740
 741	ram_wr32(fuc, 0x10f090, 0x00000060);
 742	ram_wr32(fuc, 0x10f090, 0xc000007e);
 743
 744	/*XXX: there does appear to be some kind of condition here, simply
 745	 *     modifying these bits in the vbios from the default pl0
 746	 *     entries shows no change.  however, the data does appear to
 747	 *     be correct and may be required for the transition back
 748	 */
 749	mask = 0x00010000;
 750	data = 0x00010000;
 751
 752	if (1) {
 753		mask |= 0x800807e0;
 754		data |= 0x800807e0;
 755		switch (next->bios.ramcfg_11_03_c0) {
 756		case 3: data &= ~0x00000040; break;
 757		case 2: data &= ~0x00000100; break;
 758		case 1: data &= ~0x80000000; break;
 759		case 0: data &= ~0x00000400; break;
 760		}
 761
 762		switch (next->bios.ramcfg_11_03_30) {
 763		case 3: data &= ~0x00000020; break;
 764		case 2: data &= ~0x00000080; break;
 765		case 1: data &= ~0x00080000; break;
 766		case 0: data &= ~0x00000200; break;
 767		}
 768	}
 769
 770	if (next->bios.ramcfg_11_02_80)
 771		mask |= 0x03000000;
 772	if (next->bios.ramcfg_11_02_40)
 773		mask |= 0x00002000;
 774	if (next->bios.ramcfg_11_07_10)
 775		mask |= 0x00004000;
 776	if (next->bios.ramcfg_11_07_08)
 777		mask |= 0x00000003;
 778	else
 779		mask |= 0x14000000;
 780	ram_mask(fuc, 0x10f824, mask, data);
 781
 782	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
 783
 784	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
 785	data  = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
 786	data |= next->bios.ramcfg_11_03_30 << 16;
 787	ram_wr32(fuc, 0x1373ec, data);
 788	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
 789	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
 790
 791	/* (re)program refpll, if required */
 792	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
 793	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
 794		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
 795		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
 796		ram_wr32(fuc, 0x137320, 0x00000000);
 797		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
 798		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
 799		ram_wr32(fuc, 0x132024, rcoef);
 800		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
 801		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
 802		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
 803		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
 804	}
 805
 806	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
 807	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
 808	ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
 809
 810	if (ram_have(fuc, gpioMV)) {
 811		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
 812		if (temp != ram_rd32(fuc, gpioMV)) {
 813			ram_wr32(fuc, gpiotrig, 1);
 814			ram_nsec(fuc, 64000);
 815		}
 816	}
 817
 818	if (next->bios.ramcfg_11_02_40 ||
 819	    next->bios.ramcfg_11_07_10) {
 820		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
 821		ram_nsec(fuc, 20000);
 822	}
 823
 824	if (ram->mode != 2) /*XXX*/ {
 825		if (next->bios.ramcfg_11_07_40)
 826			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
 827	}
 828
 829	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
 830	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
 831	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
 832
 833	mask = 0x00010000;
 834	data = 0x00000000;
 835	if (!next->bios.ramcfg_11_02_80)
 836		data |= 0x03000000;
 837	if (!next->bios.ramcfg_11_02_40)
 838		data |= 0x00002000;
 839	if (!next->bios.ramcfg_11_07_10)
 840		data |= 0x00004000;
 841	if (!next->bios.ramcfg_11_07_08)
 842		data |= 0x00000003;
 843	else
 844		data |= 0x14000000;
 845	ram_mask(fuc, 0x10f824, mask, data);
 846	ram_nsec(fuc, 1000);
 847
 848	if (next->bios.ramcfg_11_08_01)
 849		data = 0x00100000;
 850	else
 851		data = 0x00000000;
 852	ram_mask(fuc, 0x10f82c, 0x00100000, data);
 853
 854	/* PFB timing */
 855	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
 856	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
 857	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
 858	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
 859	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
 860	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
 861	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
 862	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
 863	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
 864	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
 865	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
 866
 867	mask = 0x33f00000;
 868	data = 0x00000000;
 869	if (!next->bios.ramcfg_11_01_04)
 870		data |= 0x20200000;
 871	if (!next->bios.ramcfg_11_07_80)
 872		data |= 0x12800000;
 873	/*XXX: see note above about there probably being some condition
 874	 *     for the 10f824 stuff that uses ramcfg 3...
 875	 */
 876	if (next->bios.ramcfg_11_03_f0) {
 877		if (next->bios.rammap_11_08_0c) {
 878			if (!next->bios.ramcfg_11_07_80)
 879				mask |= 0x00000020;
 880			else
 881				data |= 0x00000020;
 882			mask |= 0x08000004;
 883		}
 884		data |= 0x04000000;
 885	} else {
 886		mask |= 0x44000020;
 887		data |= 0x08000004;
 888	}
 889
 890	ram_mask(fuc, 0x10f808, mask, data);
 891
 892	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
 893
 894	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
 895
 896	data = (next->bios.timing[10] & 0x7f000000) >> 24;
 897	if (data < next->bios.timing_20_2c_1fc0)
 898		data = next->bios.timing_20_2c_1fc0;
 899	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
 900
 901	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
 902
 903	ram_wr32(fuc, 0x10f090, 0x4000007f);
 904	ram_nsec(fuc, 1000);
 905
 906	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
 907	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
 908	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
 909	ram_nsec(fuc, 1000);
 910
 911	if (!next->bios.ramcfg_DLLoff) {
 912		ram_mask(fuc, mr[1], 0x1, 0x0);
 913		nvkm_sddr3_dll_reset(fuc);
 914	}
 915
 916	ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]);
 917	ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]);
 918	ram_wr32(fuc, mr[0], ram->base.mr[0]);
 919	ram_nsec(fuc, 1000);
 920
 921	if (!next->bios.ramcfg_DLLoff) {
 922		nvkm_sddr3_dll_reset(fuc);
 923		ram_nsec(fuc, 1000);
 924	}
 925
 926	if (vc == 0 && ram_have(fuc, gpio2E)) {
 927		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
 928		if (temp != ram_rd32(fuc, gpio2E)) {
 929			ram_wr32(fuc, gpiotrig, 1);
 930			ram_nsec(fuc, 20000);
 931		}
 932	}
 933
 934	if (ram->mode != 2) {
 935		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
 936		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
 937	}
 938
 939	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
 940	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
 941	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
 942	ram_nsec(fuc, 1000);
 943
 944	ram_unblock(fuc);
 945
 946	if (ram->base.fb->subdev.device->disp)
 947		ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
 948
 949	if (next->bios.rammap_11_08_01)
 950		data = 0x00000800;
 951	else
 952		data = 0x00000000;
 953	ram_mask(fuc, 0x10f200, 0x00000800, data);
 954	return 0;
 955}
 956
 957/*******************************************************************************
 958 * main hooks
 959 ******************************************************************************/
 960
 961static int
 962gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data)
 963{
 964	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
 965	struct nvkm_ram_data *cfg;
 966	u32 mhz = khz / 1000;
 967
 968	list_for_each_entry(cfg, &ram->cfg, head) {
 969		if (mhz >= cfg->bios.rammap_min &&
 970		    mhz <= cfg->bios.rammap_max) {
 971			*data = *cfg;
 972			data->freq = khz;
 973			return 0;
 974		}
 975	}
 976
 977	nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz);
 978	return -EINVAL;
 979}
 980
 981static int
 982gk104_calc_pll_output(int fN, int M, int N, int P, int clk)
 983{
 984	return ((clk * N) + (((u16)(fN + 4096) * clk) >> 13)) / (M * P);
 985}
 986
 987static int
 988gk104_pll_calc_hiclk(int target_khz, int crystal,
 989		int *N1, int *fN1, int *M1, int *P1,
 990		int *N2, int *M2, int *P2)
 991{
 992	int best_err = target_khz, p_ref, n_ref;
 993	bool upper = false;
 994
 995	*M1 = 1;
 996	/* M has to be 1, otherwise it gets unstable */
 997	*M2 = 1;
 998	/* can be 1 or 2, sticking with 1 for simplicity */
 999	*P2 = 1;
1000
1001	for (p_ref = 0x7; p_ref >= 0x5; --p_ref) {
1002		for (n_ref = 0x25; n_ref <= 0x2b; ++n_ref) {
1003			int cur_N, cur_clk, cur_err;
1004
1005			cur_clk = gk104_calc_pll_output(0, 1, n_ref, p_ref, crystal);
1006			cur_N = target_khz / cur_clk;
1007			cur_err = target_khz
1008				- gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk);
1009
1010			/* we found a better combination */
1011			if (cur_err < best_err) {
1012				best_err = cur_err;
1013				*N2 = cur_N;
1014				*N1 = n_ref;
1015				*P1 = p_ref;
1016				upper = false;
1017			}
1018
1019			cur_N += 1;
1020			cur_err = gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk)
1021				- target_khz;
1022			if (cur_err < best_err) {
1023				best_err = cur_err;
1024				*N2 = cur_N;
1025				*N1 = n_ref;
1026				*P1 = p_ref;
1027				upper = true;
1028			}
1029		}
1030	}
1031
1032	/* adjust fN to get closer to the target clock */
1033	*fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal);
1034	if (upper)
1035		*fN1 = (u16)(1 - *fN1);
1036
1037	return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal);
1038}
1039
1040static int
1041gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next)
1042{
1043	struct gk104_ramfuc *fuc = &ram->fuc;
1044	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
1045	int refclk, i;
1046	int ret;
1047
1048	ret = ram_init(fuc, ram->base.fb);
1049	if (ret)
1050		return ret;
1051
1052	ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
1053	ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
1054
1055	/* XXX: this is *not* what nvidia do.  on fermi nvidia generally
1056	 * select, based on some unknown condition, one of the two possible
1057	 * reference frequencies listed in the vbios table for mempll and
1058	 * program refpll to that frequency.
1059	 *
1060	 * so far, i've seen very weird values being chosen by nvidia on
1061	 * kepler boards, no idea how/why they're chosen.
1062	 */
1063	refclk = next->freq;
1064	if (ram->mode == 2) {
1065		ret = gk104_pll_calc_hiclk(next->freq, subdev->device->crystal,
1066				&ram->N1, &ram->fN1, &ram->M1, &ram->P1,
1067				&ram->N2, &ram->M2, &ram->P2);
1068		fuc->mempll.refclk = ret;
1069		if (ret <= 0) {
1070			nvkm_error(subdev, "unable to calc plls\n");
1071			return -EINVAL;
1072		}
1073		nvkm_debug(subdev, "successfully calced PLLs for clock %i kHz"
1074				" (refclock: %i kHz)\n", next->freq, ret);
1075	} else {
1076		/* calculate refpll coefficients */
1077		ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1,
1078				     &ram->fN1, &ram->M1, &ram->P1);
1079		fuc->mempll.refclk = ret;
1080		if (ret <= 0) {
1081			nvkm_error(subdev, "unable to calc refpll\n");
1082			return -EINVAL;
1083		}
1084	}
1085
1086	for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1087		if (ram_have(fuc, mr[i]))
1088			ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1089	}
1090	ram->base.freq = next->freq;
1091
1092	switch (ram->base.type) {
1093	case NVKM_RAM_TYPE_DDR3:
1094		ret = nvkm_sddr3_calc(&ram->base);
1095		if (ret == 0)
1096			ret = gk104_ram_calc_sddr3(ram, next->freq);
1097		break;
1098	case NVKM_RAM_TYPE_GDDR5:
1099		ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0);
1100		if (ret == 0)
1101			ret = gk104_ram_calc_gddr5(ram, next->freq);
1102		break;
1103	default:
1104		ret = -ENOSYS;
1105		break;
1106	}
1107
1108	return ret;
1109}
1110
1111int
1112gk104_ram_calc(struct nvkm_ram *base, u32 freq)
1113{
1114	struct gk104_ram *ram = gk104_ram(base);
1115	struct nvkm_clk *clk = ram->base.fb->subdev.device->clk;
1116	struct nvkm_ram_data *xits = &ram->base.xition;
1117	struct nvkm_ram_data *copy;
1118	int ret;
1119
1120	if (ram->base.next == NULL) {
1121		ret = gk104_ram_calc_data(ram,
1122					  nvkm_clk_read(clk, nv_clk_src_mem),
1123					  &ram->base.former);
1124		if (ret)
1125			return ret;
1126
1127		ret = gk104_ram_calc_data(ram, freq, &ram->base.target);
1128		if (ret)
1129			return ret;
1130
1131		if (ram->base.target.freq < ram->base.former.freq) {
1132			*xits = ram->base.target;
1133			copy = &ram->base.former;
1134		} else {
1135			*xits = ram->base.former;
1136			copy = &ram->base.target;
1137		}
1138
1139		xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
1140		xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
1141		xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
1142
1143		ram->base.next = &ram->base.target;
1144		if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
1145			ram->base.next = &ram->base.xition;
1146	} else {
1147		BUG_ON(ram->base.next != &ram->base.xition);
1148		ram->base.next = &ram->base.target;
1149	}
1150
1151	return gk104_ram_calc_xits(ram, ram->base.next);
1152}
1153
1154static void
1155gk104_ram_prog_0(struct gk104_ram *ram, u32 freq)
1156{
1157	struct nvkm_device *device = ram->base.fb->subdev.device;
1158	struct nvkm_ram_data *cfg;
1159	u32 mhz = freq / 1000;
1160	u32 mask, data;
1161
1162	list_for_each_entry(cfg, &ram->cfg, head) {
1163		if (mhz >= cfg->bios.rammap_min &&
1164		    mhz <= cfg->bios.rammap_max)
1165			break;
1166	}
1167
1168	if (&cfg->head == &ram->cfg)
1169		return;
1170
1171	if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
1172		data |= cfg->bios.rammap_11_0a_03fe << 12;
1173		mask |= 0x001ff000;
1174	}
1175	if (ram->diff.rammap_11_09_01ff) {
1176		data |= cfg->bios.rammap_11_09_01ff;
1177		mask |= 0x000001ff;
1178	}
1179	nvkm_mask(device, 0x10f468, mask, data);
1180
1181	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
1182		data |= cfg->bios.rammap_11_0a_0400;
1183		mask |= 0x00000001;
1184	}
1185	nvkm_mask(device, 0x10f420, mask, data);
1186
1187	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
1188		data |= cfg->bios.rammap_11_0a_0800;
1189		mask |= 0x00000001;
1190	}
1191	nvkm_mask(device, 0x10f430, mask, data);
1192
1193	if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
1194		data |= cfg->bios.rammap_11_0b_01f0;
1195		mask |= 0x0000001f;
1196	}
1197	nvkm_mask(device, 0x10f400, mask, data);
1198
1199	if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
1200		data |= cfg->bios.rammap_11_0b_0200 << 9;
1201		mask |= 0x00000200;
1202	}
1203	nvkm_mask(device, 0x10f410, mask, data);
1204
1205	if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
1206		data |= cfg->bios.rammap_11_0d << 16;
1207		mask |= 0x00ff0000;
1208	}
1209	if (ram->diff.rammap_11_0f) {
1210		data |= cfg->bios.rammap_11_0f << 8;
1211		mask |= 0x0000ff00;
1212	}
1213	nvkm_mask(device, 0x10f440, mask, data);
1214
1215	if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
1216		data |= cfg->bios.rammap_11_0e << 8;
1217		mask |= 0x0000ff00;
1218	}
1219	if (ram->diff.rammap_11_0b_0800) {
1220		data |= cfg->bios.rammap_11_0b_0800 << 7;
1221		mask |= 0x00000080;
1222	}
1223	if (ram->diff.rammap_11_0b_0400) {
1224		data |= cfg->bios.rammap_11_0b_0400 << 5;
1225		mask |= 0x00000020;
1226	}
1227	nvkm_mask(device, 0x10f444, mask, data);
1228}
1229
1230int
1231gk104_ram_prog(struct nvkm_ram *base)
1232{
1233	struct gk104_ram *ram = gk104_ram(base);
1234	struct gk104_ramfuc *fuc = &ram->fuc;
1235	struct nvkm_device *device = ram->base.fb->subdev.device;
1236	struct nvkm_ram_data *next = ram->base.next;
1237
1238	if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) {
1239		ram_exec(fuc, false);
1240		return (ram->base.next == &ram->base.xition);
1241	}
1242
1243	gk104_ram_prog_0(ram, 1000);
1244	ram_exec(fuc, true);
1245	gk104_ram_prog_0(ram, next->freq);
1246
1247	return (ram->base.next == &ram->base.xition);
1248}
1249
1250void
1251gk104_ram_tidy(struct nvkm_ram *base)
1252{
1253	struct gk104_ram *ram = gk104_ram(base);
1254	ram->base.next = NULL;
1255	ram_exec(&ram->fuc, false);
1256}
1257
1258struct gk104_ram_train {
1259	u16 mask;
1260	struct nvbios_M0209S remap;
1261	struct nvbios_M0209S type00;
1262	struct nvbios_M0209S type01;
1263	struct nvbios_M0209S type04;
1264	struct nvbios_M0209S type06;
1265	struct nvbios_M0209S type07;
1266	struct nvbios_M0209S type08;
1267	struct nvbios_M0209S type09;
1268};
1269
1270static int
1271gk104_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg,
1272		     struct gk104_ram_train *train)
1273{
1274	struct nvkm_bios *bios = ram->fb->subdev.device->bios;
1275	struct nvbios_M0205E M0205E;
1276	struct nvbios_M0205S M0205S;
1277	struct nvbios_M0209E M0209E;
1278	struct nvbios_M0209S *remap = &train->remap;
1279	struct nvbios_M0209S *value;
1280	u8  ver, hdr, cnt, len;
1281	u32 data;
1282
1283	/* determine type of data for this index */
1284	if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
1285		return -ENOENT;
1286
1287	switch (M0205E.type) {
1288	case 0x00: value = &train->type00; break;
1289	case 0x01: value = &train->type01; break;
1290	case 0x04: value = &train->type04; break;
1291	case 0x06: value = &train->type06; break;
1292	case 0x07: value = &train->type07; break;
1293	case 0x08: value = &train->type08; break;
1294	case 0x09: value = &train->type09; break;
1295	default:
1296		return 0;
1297	}
1298
1299	/* training data index determined by ramcfg strap */
1300	if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
1301		return -EINVAL;
1302	i = M0205S.data;
1303
1304	/* training data format information */
1305	if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
1306		return -EINVAL;
1307
1308	/* ... and the raw data */
1309	if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
1310		return -EINVAL;
1311
1312	if (M0209E.v02_07 == 2) {
1313		/* of course! why wouldn't we have a pointer to another entry
1314		 * in the same table, and use the first one as an array of
1315		 * remap indices...
1316		 */
1317		if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
1318					    remap)))
1319			return -EINVAL;
1320
1321		for (i = 0; i < ARRAY_SIZE(value->data); i++)
1322			value->data[i] = remap->data[value->data[i]];
1323	} else
1324	if (M0209E.v02_07 != 1)
1325		return -EINVAL;
1326
1327	train->mask |= 1 << M0205E.type;
1328	return 0;
1329}
1330
1331static int
1332gk104_ram_train_init_0(struct nvkm_ram *ram, struct gk104_ram_train *train)
1333{
1334	struct nvkm_subdev *subdev = &ram->fb->subdev;
1335	struct nvkm_device *device = subdev->device;
1336	int i, j;
1337
1338	if ((train->mask & 0x03d3) != 0x03d3) {
1339		nvkm_warn(subdev, "missing link training data\n");
1340		return -EINVAL;
1341	}
1342
1343	for (i = 0; i < 0x30; i++) {
1344		for (j = 0; j < 8; j += 4) {
1345			nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8));
1346			nvkm_wr32(device, 0x10f920 + j, 0x00000000 |
1347						   train->type08.data[i] << 4 |
1348						   train->type06.data[i]);
1349			nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]);
1350			nvkm_wr32(device, 0x10f920 + j, 0x00000100 |
1351						   train->type09.data[i] << 4 |
1352						   train->type07.data[i]);
1353			nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]);
1354		}
1355	}
1356
1357	for (j = 0; j < 8; j += 4) {
1358		for (i = 0; i < 0x100; i++) {
1359			nvkm_wr32(device, 0x10f968 + j, i);
1360			nvkm_wr32(device, 0x10f900 + j, train->type04.data[i]);
1361		}
1362	}
1363
1364	return 0;
1365}
1366
1367static int
1368gk104_ram_train_init(struct nvkm_ram *ram)
1369{
1370	u8 ramcfg = nvbios_ramcfg_index(&ram->fb->subdev);
1371	struct gk104_ram_train *train;
1372	int ret, i;
1373
1374	if (!(train = kzalloc(sizeof(*train), GFP_KERNEL)))
1375		return -ENOMEM;
1376
1377	for (i = 0; i < 0x100; i++) {
1378		ret = gk104_ram_train_type(ram, i, ramcfg, train);
1379		if (ret && ret != -ENOENT)
1380			break;
1381	}
1382
1383	switch (ram->type) {
1384	case NVKM_RAM_TYPE_GDDR5:
1385		ret = gk104_ram_train_init_0(ram, train);
1386		break;
1387	default:
1388		ret = 0;
1389		break;
1390	}
1391
1392	kfree(train);
1393	return ret;
1394}
1395
1396int
1397gk104_ram_init(struct nvkm_ram *ram)
1398{
1399	struct nvkm_subdev *subdev = &ram->fb->subdev;
1400	struct nvkm_device *device = subdev->device;
1401	struct nvkm_bios *bios = device->bios;
1402	u8  ver, hdr, cnt, len, snr, ssz;
1403	u32 data, save;
1404	int i;
1405
1406	/* run a bunch of tables from rammap table.  there's actually
1407	 * individual pointers for each rammap entry too, but, nvidia
1408	 * seem to just run the last two entries' scripts early on in
1409	 * their init, and never again.. we'll just run 'em all once
1410	 * for now.
1411	 *
1412	 * i strongly suspect that each script is for a separate mode
1413	 * (likely selected by 0x10f65c's lower bits?), and the
1414	 * binary driver skips the one that's already been setup by
1415	 * the init tables.
1416	 */
1417	data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1418	if (!data || hdr < 0x15)
1419		return -EINVAL;
1420
1421	cnt  = nvbios_rd08(bios, data + 0x14); /* guess at count */
1422	data = nvbios_rd32(bios, data + 0x10); /* guess u32... */
1423	save = nvkm_rd32(device, 0x10f65c) & 0x000000f0;
1424	for (i = 0; i < cnt; i++, data += 4) {
1425		if (i != save >> 4) {
1426			nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4);
1427			nvbios_init(subdev, nvbios_rd32(bios, data));
1428		}
1429	}
1430	nvkm_mask(device, 0x10f65c, 0x000000f0, save);
1431	nvkm_mask(device, 0x10f584, 0x11000000, 0x00000000);
1432	nvkm_wr32(device, 0x10ecc0, 0xffffffff);
1433	nvkm_mask(device, 0x10f160, 0x00000010, 0x00000010);
1434
1435	return gk104_ram_train_init(ram);
1436}
1437
1438static int
1439gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i)
1440{
1441	struct nvkm_bios *bios = ram->base.fb->subdev.device->bios;
1442	struct nvkm_ram_data *cfg;
1443	struct nvbios_ramcfg *d = &ram->diff;
1444	struct nvbios_ramcfg *p, *n;
1445	u8  ver, hdr, cnt, len;
1446	u32 data;
1447	int ret;
1448
1449	if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL)))
1450		return -ENOMEM;
1451	p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios;
1452	n = &cfg->bios;
1453
1454	/* memory config data for a range of target frequencies */
1455	data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios);
1456	if (ret = -ENOENT, !data)
1457		goto done;
1458	if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12)
1459		goto done;
1460
1461	/* ... and a portion specific to the attached memory */
1462	data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg,
1463			       &ver, &hdr, &cfg->bios);
1464	if (ret = -EINVAL, !data)
1465		goto done;
1466	if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a)
1467		goto done;
1468
1469	/* lookup memory timings, if bios says they're present */
1470	if (cfg->bios.ramcfg_timing != 0xff) {
1471		data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing,
1472				       &ver, &hdr, &cnt, &len,
1473				       &cfg->bios);
1474		if (ret = -EINVAL, !data)
1475			goto done;
1476		if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33)
1477			goto done;
1478	}
1479
1480	list_add_tail(&cfg->head, &ram->cfg);
1481	if (ret = 0, i == 0)
1482		goto done;
1483
1484	d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe;
1485	d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff;
1486	d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400;
1487	d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800;
1488	d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0;
1489	d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200;
1490	d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d;
1491	d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f;
1492	d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e;
1493	d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800;
1494	d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400;
1495	d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01;
1496	d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02;
1497	d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10;
1498	d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03;
1499	d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20;
1500	d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07;
1501done:
1502	if (ret)
1503		kfree(cfg);
1504	return ret;
1505}
1506
1507void *
1508gk104_ram_dtor(struct nvkm_ram *base)
1509{
1510	struct gk104_ram *ram = gk104_ram(base);
1511	struct nvkm_ram_data *cfg, *tmp;
1512
1513	list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
1514		kfree(cfg);
1515	}
1516
1517	return ram;
1518}
1519
1520int
1521gk104_ram_new_(const struct nvkm_ram_func *func, struct nvkm_fb *fb,
1522	       struct nvkm_ram **pram)
1523{
1524	struct nvkm_subdev *subdev = &fb->subdev;
1525	struct nvkm_device *device = subdev->device;
1526	struct nvkm_bios *bios = device->bios;
1527	struct dcb_gpio_func gpio;
1528	struct gk104_ram *ram;
1529	int ret, i;
1530	u8  ramcfg = nvbios_ramcfg_index(subdev);
1531	u32 tmp;
1532
1533	if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
1534		return -ENOMEM;
1535	*pram = &ram->base;
1536
1537	ret = gf100_ram_ctor(func, fb, &ram->base);
1538	if (ret)
1539		return ret;
1540
1541	INIT_LIST_HEAD(&ram->cfg);
1542
1543	/* calculate a mask of differently configured memory partitions,
1544	 * because, of course reclocking wasn't complicated enough
1545	 * already without having to treat some of them differently to
1546	 * the others....
1547	 */
1548	ram->parts = nvkm_rd32(device, 0x022438);
1549	ram->pmask = nvkm_rd32(device, 0x022554);
1550	ram->pnuts = 0;
1551	for (i = 0, tmp = 0; i < ram->parts; i++) {
1552		if (!(ram->pmask & (1 << i))) {
1553			u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000));
1554			if (tmp && tmp != cfg1) {
1555				ram->pnuts |= (1 << i);
1556				continue;
1557			}
1558			tmp = cfg1;
1559		}
1560	}
1561
1562	/* parse bios data for all rammap table entries up-front, and
1563	 * build information on whether certain fields differ between
1564	 * any of the entries.
1565	 *
1566	 * the binary driver appears to completely ignore some fields
1567	 * when all entries contain the same value.  at first, it was
1568	 * hoped that these were mere optimisations and the bios init
1569	 * tables had configured as per the values here, but there is
1570	 * evidence now to suggest that this isn't the case and we do
1571	 * need to treat this condition as a "don't touch" indicator.
1572	 */
1573	for (i = 0; !ret; i++) {
1574		ret = gk104_ram_ctor_data(ram, ramcfg, i);
1575		if (ret && ret != -ENOENT) {
1576			nvkm_error(subdev, "failed to parse ramcfg data\n");
1577			return ret;
1578		}
1579	}
1580
1581	/* parse bios data for both pll's */
1582	ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1583	if (ret) {
1584		nvkm_error(subdev, "mclk refpll data not found\n");
1585		return ret;
1586	}
1587
1588	ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1589	if (ret) {
1590		nvkm_error(subdev, "mclk pll data not found\n");
1591		return ret;
1592	}
1593
1594	/* lookup memory voltage gpios */
1595	ret = nvkm_gpio_find(device->gpio, 0, 0x18, DCB_GPIO_UNUSED, &gpio);
1596	if (ret == 0) {
1597		ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (gpio.line * 0x04));
1598		ram->fuc.r_funcMV[0] = (gpio.log[0] ^ 2) << 12;
1599		ram->fuc.r_funcMV[1] = (gpio.log[1] ^ 2) << 12;
1600	}
1601
1602	ret = nvkm_gpio_find(device->gpio, 0, 0x2e, DCB_GPIO_UNUSED, &gpio);
1603	if (ret == 0) {
1604		ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (gpio.line * 0x04));
1605		ram->fuc.r_func2E[0] = (gpio.log[0] ^ 2) << 12;
1606		ram->fuc.r_func2E[1] = (gpio.log[1] ^ 2) << 12;
1607	}
1608
1609	ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1610
1611	ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1612	ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1613	ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1614	ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1615	ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1616	ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1617	ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1618	ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1619
1620	ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1621	ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1622	ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1623	ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1624	ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1625	ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1626	ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1627	ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1628	ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1629	ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1630	ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1631	ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1632	ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1633	ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1634	ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1635	ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1636	ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1637	ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1638	ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1639	ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1640	ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1641
1642	ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1643	ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1644	ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1645	ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1646	ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1647	ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1648	ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1649	ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1650	ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1651	ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1652	ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1653
1654	ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1655	ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1656	ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1657
1658	switch (ram->base.type) {
1659	case NVKM_RAM_TYPE_GDDR5:
1660		ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1661		ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1662		ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1663		ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1664		ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1665		ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1666		ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1667		ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1668		ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1669		ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1670		break;
1671	case NVKM_RAM_TYPE_DDR3:
1672		ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1673		ram->fuc.r_mr[1] = ramfuc_reg(0x10f304);
1674		ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1675		break;
1676	default:
1677		break;
1678	}
1679
1680	ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1681	ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1682	ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1683	ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1684	ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1685	ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1686	ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1687	ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1688	ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1689	ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1690	ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1691	ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1692	ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1693	ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1694	ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1695	ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1696	return 0;
1697}
1698
1699static const struct nvkm_ram_func
1700gk104_ram = {
1701	.upper = 0x0200000000ULL,
1702	.probe_fbp = gf100_ram_probe_fbp,
1703	.probe_fbp_amount = gf108_ram_probe_fbp_amount,
1704	.probe_fbpa_amount = gf100_ram_probe_fbpa_amount,
1705	.dtor = gk104_ram_dtor,
1706	.init = gk104_ram_init,
1707	.calc = gk104_ram_calc,
1708	.prog = gk104_ram_prog,
1709	.tidy = gk104_ram_tidy,
1710};
1711
1712int
1713gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
1714{
1715	return gk104_ram_new_(&gk104_ram, fb, pram);
1716}