nv50.c

  1/*
  2 * Copyright 2012 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs
 23 */
 24#include "nv50.h"
 25#include "ram.h"
 26
 27#include <core/client.h>
 28#include <core/enum.h>
 29#include <engine/fifo.h>
 30
 31static int
 32nv50_fb_ram_new(struct nvkm_fb *base, struct nvkm_ram **pram)
 33{
 34	struct nv50_fb *fb = nv50_fb(base);
 35	return fb->func->ram_new(&fb->base, pram);
 36}
 37
 38static const struct nvkm_enum vm_dispatch_subclients[] = {
 39	{ 0x00000000, "GRCTX" },
 40	{ 0x00000001, "NOTIFY" },
 41	{ 0x00000002, "QUERY" },
 42	{ 0x00000003, "COND" },
 43	{ 0x00000004, "M2M_IN" },
 44	{ 0x00000005, "M2M_OUT" },
 45	{ 0x00000006, "M2M_NOTIFY" },
 46	{}
 47};
 48
 49static const struct nvkm_enum vm_ccache_subclients[] = {
 50	{ 0x00000000, "CB" },
 51	{ 0x00000001, "TIC" },
 52	{ 0x00000002, "TSC" },
 53	{}
 54};
 55
 56static const struct nvkm_enum vm_prop_subclients[] = {
 57	{ 0x00000000, "RT0" },
 58	{ 0x00000001, "RT1" },
 59	{ 0x00000002, "RT2" },
 60	{ 0x00000003, "RT3" },
 61	{ 0x00000004, "RT4" },
 62	{ 0x00000005, "RT5" },
 63	{ 0x00000006, "RT6" },
 64	{ 0x00000007, "RT7" },
 65	{ 0x00000008, "ZETA" },
 66	{ 0x00000009, "LOCAL" },
 67	{ 0x0000000a, "GLOBAL" },
 68	{ 0x0000000b, "STACK" },
 69	{ 0x0000000c, "DST2D" },
 70	{}
 71};
 72
 73static const struct nvkm_enum vm_pfifo_subclients[] = {
 74	{ 0x00000000, "PUSHBUF" },
 75	{ 0x00000001, "SEMAPHORE" },
 76	{}
 77};
 78
 79static const struct nvkm_enum vm_bar_subclients[] = {
 80	{ 0x00000000, "FB" },
 81	{ 0x00000001, "IN" },
 82	{}
 83};
 84
 85static const struct nvkm_enum vm_client[] = {
 86	{ 0x00000000, "STRMOUT" },
 87	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
 88	{ 0x00000004, "PFIFO_WRITE" },
 89	{ 0x00000005, "CCACHE", vm_ccache_subclients },
 90	{ 0x00000006, "PMSPPP" },
 91	{ 0x00000007, "CLIPID" },
 92	{ 0x00000008, "PFIFO_READ" },
 93	{ 0x00000009, "VFETCH" },
 94	{ 0x0000000a, "TEXTURE" },
 95	{ 0x0000000b, "PROP", vm_prop_subclients },
 96	{ 0x0000000c, "PVP" },
 97	{ 0x0000000d, "PBSP" },
 98	{ 0x0000000e, "PCRYPT" },
 99	{ 0x0000000f, "PCOUNTER" },
100	{ 0x00000011, "PDAEMON" },
101	{}
102};
103
104static const struct nvkm_enum vm_engine[] = {
105	{ 0x00000000, "PGRAPH" },
106	{ 0x00000001, "PVP" },
107	{ 0x00000004, "PEEPHOLE" },
108	{ 0x00000005, "PFIFO", vm_pfifo_subclients },
109	{ 0x00000006, "BAR", vm_bar_subclients },
110	{ 0x00000008, "PMSPPP" },
111	{ 0x00000008, "PMPEG" },
112	{ 0x00000009, "PBSP" },
113	{ 0x0000000a, "PCRYPT" },
114	{ 0x0000000b, "PCOUNTER" },
115	{ 0x0000000c, "SEMAPHORE_BG" },
116	{ 0x0000000d, "PCE0" },
117	{ 0x0000000e, "PMU" },
118	{}
119};
120
121static const struct nvkm_enum vm_fault[] = {
122	{ 0x00000000, "PT_NOT_PRESENT" },
123	{ 0x00000001, "PT_TOO_SHORT" },
124	{ 0x00000002, "PAGE_NOT_PRESENT" },
125	{ 0x00000003, "PAGE_SYSTEM_ONLY" },
126	{ 0x00000004, "PAGE_READ_ONLY" },
127	{ 0x00000006, "NULL_DMAOBJ" },
128	{ 0x00000007, "WRONG_MEMTYPE" },
129	{ 0x0000000b, "VRAM_LIMIT" },
130	{ 0x0000000f, "DMAOBJ_LIMIT" },
131	{}
132};
133
134static void
135nv50_fb_intr(struct nvkm_fb *base)
136{
137	struct nv50_fb *fb = nv50_fb(base);
138	struct nvkm_subdev *subdev = &fb->base.subdev;
139	struct nvkm_device *device = subdev->device;
140	struct nvkm_chan *chan;
141	const struct nvkm_enum *en, *re, *cl, *sc;
142	u32 trap[6], idx, inst;
143	u8 st0, st1, st2, st3;
144	unsigned long flags;
145	int i;
146
147	idx = nvkm_rd32(device, 0x100c90);
148	if (!(idx & 0x80000000))
149		return;
150	idx &= 0x00ffffff;
151
152	for (i = 0; i < 6; i++) {
153		nvkm_wr32(device, 0x100c90, idx | i << 24);
154		trap[i] = nvkm_rd32(device, 0x100c94);
155	}
156	nvkm_wr32(device, 0x100c90, idx | 0x80000000);
157
158	/* decode status bits into something more useful */
159	if (device->chipset  < 0xa3 ||
160	    device->chipset == 0xaa || device->chipset == 0xac) {
161		st0 = (trap[0] & 0x0000000f) >> 0;
162		st1 = (trap[0] & 0x000000f0) >> 4;
163		st2 = (trap[0] & 0x00000f00) >> 8;
164		st3 = (trap[0] & 0x0000f000) >> 12;
165	} else {
166		st0 = (trap[0] & 0x000000ff) >> 0;
167		st1 = (trap[0] & 0x0000ff00) >> 8;
168		st2 = (trap[0] & 0x00ff0000) >> 16;
169		st3 = (trap[0] & 0xff000000) >> 24;
170	}
171	inst = ((trap[2] << 16) | trap[1]) << 12;
172
173	en = nvkm_enum_find(vm_engine, st0);
174	re = nvkm_enum_find(vm_fault , st1);
175	cl = nvkm_enum_find(vm_client, st2);
176	if      (cl && cl->data) sc = nvkm_enum_find(cl->data, st3);
177	else if (en && en->data) sc = nvkm_enum_find(en->data, st3);
178	else                     sc = NULL;
179
180	chan = nvkm_chan_get_inst(&device->fifo->engine, inst, &flags);
181	nvkm_error(subdev, "trapped %s at %02x%04x%04x on channel %d [%08x %s] "
182			   "engine %02x [%s] client %02x [%s] "
183			   "subclient %02x [%s] reason %08x [%s]\n",
184		   (trap[5] & 0x00000100) ? "read" : "write",
185		   trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
186		   chan ? chan->id : -1, inst,
187		   chan ? chan->name : "unknown",
188		   st0, en ? en->name : "",
189		   st2, cl ? cl->name : "", st3, sc ? sc->name : "",
190		   st1, re ? re->name : "");
191	nvkm_chan_put(&chan, flags);
192}
193
194static void
195nv50_fb_init(struct nvkm_fb *base)
196{
197	struct nv50_fb *fb = nv50_fb(base);
198	struct nvkm_device *device = fb->base.subdev.device;
199
200	/* This is needed to get meaningful information from 100c90
201	 * on traps. No idea what these values mean exactly. */
202	nvkm_wr32(device, 0x100c90, fb->func->trap);
203}
204
205static u32
206nv50_fb_tags(struct nvkm_fb *base)
207{
208	struct nv50_fb *fb = nv50_fb(base);
209	if (fb->func->tags)
210		return fb->func->tags(&fb->base);
211	return 0;
212}
213
214static void
215nv50_fb_sysmem_flush_page_init(struct nvkm_fb *fb)
216{
217	// Ensure that the address can actually fit in the register
218	WARN_ON(fb->sysmem.flush_page_addr > DMA_BIT_MASK(40));
219
220	nvkm_wr32(fb->subdev.device, 0x100c08, fb->sysmem.flush_page_addr >> 8);
221}
222
223static void *
224nv50_fb_dtor(struct nvkm_fb *base)
225{
226	struct nv50_fb *fb = nv50_fb(base);
227
228	return fb;
229}
230
231static const struct nvkm_fb_func
232nv50_fb_ = {
233	.dtor = nv50_fb_dtor,
234	.tags = nv50_fb_tags,
235	.init = nv50_fb_init,
236	.intr = nv50_fb_intr,
237	.sysmem.flush_page_init = nv50_fb_sysmem_flush_page_init,
238	.ram_new = nv50_fb_ram_new,
239};
240
241int
242nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device,
243	     enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
244{
245	struct nv50_fb *fb;
246
247	if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL)))
248		return -ENOMEM;
249	nvkm_fb_ctor(&nv50_fb_, device, type, inst, &fb->base);
250	fb->func = func;
251	*pfb = &fb->base;
252	return 0;
253}
254
255static const struct nv50_fb_func
256nv50_fb = {
257	.ram_new = nv50_ram_new,
258	.tags = nv20_fb_tags,
259	.trap = 0x000707ff,
260};
261
262int
263nv50_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
264{
265	return nv50_fb_new_(&nv50_fb, device, type, inst, pfb);
266}