timing.c

  1/*
  2 * Copyright 2013 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs
 23 */
 24#include <subdev/bios.h>
 25#include <subdev/bios/bit.h>
 26#include <subdev/bios/timing.h>
 27
 28u32
 29nvbios_timingTe(struct nvkm_bios *bios,
 30		u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
 31{
 32	struct bit_entry bit_P;
 33	u32 timing = 0;
 34
 35	if (!bit_entry(bios, 'P', &bit_P)) {
 36		if (bit_P.version == 1)
 37			timing = nvbios_rd32(bios, bit_P.offset + 4);
 38		else
 39		if (bit_P.version == 2)
 40			timing = nvbios_rd32(bios, bit_P.offset + 8);
 41
 42		if (timing) {
 43			*ver = nvbios_rd08(bios, timing + 0);
 44			switch (*ver) {
 45			case 0x10:
 46				*hdr = nvbios_rd08(bios, timing + 1);
 47				*cnt = nvbios_rd08(bios, timing + 2);
 48				*len = nvbios_rd08(bios, timing + 3);
 49				*snr = 0;
 50				*ssz = 0;
 51				return timing;
 52			case 0x20:
 53				*hdr = nvbios_rd08(bios, timing + 1);
 54				*cnt = nvbios_rd08(bios, timing + 5);
 55				*len = nvbios_rd08(bios, timing + 2);
 56				*snr = nvbios_rd08(bios, timing + 4);
 57				*ssz = nvbios_rd08(bios, timing + 3);
 58				return timing;
 59			default:
 60				break;
 61			}
 62		}
 63	}
 64
 65	return 0;
 66}
 67
 68u32
 69nvbios_timingEe(struct nvkm_bios *bios, int idx,
 70		u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
 71{
 72	u8  snr, ssz;
 73	u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
 74	if (timing && idx < *cnt) {
 75		timing += *hdr + idx * (*len + (snr * ssz));
 76		*hdr = *len;
 77		*cnt = snr;
 78		*len = ssz;
 79		return timing;
 80	}
 81	return 0;
 82}
 83
 84u32
 85nvbios_timingEp(struct nvkm_bios *bios, int idx,
 86		u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
 87{
 88	u32 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
 89	p->timing_ver = *ver;
 90	p->timing_hdr = *hdr;
 91	switch (!!data * *ver) {
 92	case 0x10:
 93		p->timing_10_WR    = nvbios_rd08(bios, data + 0x00);
 94		p->timing_10_WTR   = nvbios_rd08(bios, data + 0x01);
 95		p->timing_10_CL    = nvbios_rd08(bios, data + 0x02);
 96		p->timing_10_RC    = nvbios_rd08(bios, data + 0x03);
 97		p->timing_10_RFC   = nvbios_rd08(bios, data + 0x05);
 98		p->timing_10_RAS   = nvbios_rd08(bios, data + 0x07);
 99		p->timing_10_RP    = nvbios_rd08(bios, data + 0x09);
100		p->timing_10_RCDRD = nvbios_rd08(bios, data + 0x0a);
101		p->timing_10_RCDWR = nvbios_rd08(bios, data + 0x0b);
102		p->timing_10_RRD   = nvbios_rd08(bios, data + 0x0c);
103		p->timing_10_13    = nvbios_rd08(bios, data + 0x0d);
104		p->timing_10_ODT   = nvbios_rd08(bios, data + 0x0e) & 0x07;
105		if (p->ramcfg_ver >= 0x10)
106			p->ramcfg_RON = nvbios_rd08(bios, data + 0x0e) & 0x07;
107
108		p->timing_10_24  = 0xff;
109		p->timing_10_21  = 0;
110		p->timing_10_20  = 0;
111		p->timing_10_CWL = 0;
112		p->timing_10_18  = 0;
113		p->timing_10_16  = 0;
114
115		switch (min_t(u8, *hdr, 25)) {
116		case 25:
117			p->timing_10_24  = nvbios_rd08(bios, data + 0x18);
118			fallthrough;
119		case 24:
120		case 23:
121		case 22:
122			p->timing_10_21  = nvbios_rd08(bios, data + 0x15);
123			fallthrough;
124		case 21:
125			p->timing_10_20  = nvbios_rd08(bios, data + 0x14);
126			fallthrough;
127		case 20:
128			p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
129			fallthrough;
130		case 19:
131			p->timing_10_18  = nvbios_rd08(bios, data + 0x12);
132			fallthrough;
133		case 18:
134		case 17:
135			p->timing_10_16  = nvbios_rd08(bios, data + 0x10);
136		}
137
138		break;
139	case 0x20:
140		p->timing[0] = nvbios_rd32(bios, data + 0x00);
141		p->timing[1] = nvbios_rd32(bios, data + 0x04);
142		p->timing[2] = nvbios_rd32(bios, data + 0x08);
143		p->timing[3] = nvbios_rd32(bios, data + 0x0c);
144		p->timing[4] = nvbios_rd32(bios, data + 0x10);
145		p->timing[5] = nvbios_rd32(bios, data + 0x14);
146		p->timing[6] = nvbios_rd32(bios, data + 0x18);
147		p->timing[7] = nvbios_rd32(bios, data + 0x1c);
148		p->timing[8] = nvbios_rd32(bios, data + 0x20);
149		p->timing[9] = nvbios_rd32(bios, data + 0x24);
150		p->timing[10] = nvbios_rd32(bios, data + 0x28);
151		p->timing_20_2e_03 = (nvbios_rd08(bios, data + 0x2e) & 0x03) >> 0;
152		p->timing_20_2e_30 = (nvbios_rd08(bios, data + 0x2e) & 0x30) >> 4;
153		p->timing_20_2e_c0 = (nvbios_rd08(bios, data + 0x2e) & 0xc0) >> 6;
154		p->timing_20_2f_03 = (nvbios_rd08(bios, data + 0x2f) & 0x03) >> 0;
155		temp = nvbios_rd16(bios, data + 0x2c);
156		p->timing_20_2c_003f = (temp & 0x003f) >> 0;
157		p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
158		p->timing_20_30_07 = (nvbios_rd08(bios, data + 0x30) & 0x07) >> 0;
159		p->timing_20_30_f8 = (nvbios_rd08(bios, data + 0x30) & 0xf8) >> 3;
160		temp = nvbios_rd16(bios, data + 0x31);
161		p->timing_20_31_0007 = (temp & 0x0007) >> 0;
162		p->timing_20_31_0078 = (temp & 0x0078) >> 3;
163		p->timing_20_31_0780 = (temp & 0x0780) >> 7;
164		p->timing_20_31_0800 = (temp & 0x0800) >> 11;
165		p->timing_20_31_7000 = (temp & 0x7000) >> 12;
166		p->timing_20_31_8000 = (temp & 0x8000) >> 15;
167		break;
168	default:
169		data = 0;
170		break;
171	}
172	return data;
173}