tu102.c

  1/*
  2 * Copyright 2019 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22#include "priv.h"
 23
 24#include <core/firmware.h>
 25#include <core/memory.h>
 26#include <subdev/gsp.h>
 27#include <subdev/pmu.h>
 28#include <engine/sec2.h>
 29
 30#include <nvfw/acr.h>
 31
 32int
 33tu102_acr_init(struct nvkm_acr *acr)
 34{
 35	int ret = nvkm_acr_hsfw_boot(acr, "AHESASC");
 36	if (ret)
 37		return ret;
 38
 39	return nvkm_acr_hsfw_boot(acr, "ASB");
 40}
 41
 42static int
 43tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
 44{
 45	struct nvkm_acr_lsfw *lsfw;
 46	u32 offset = 0;
 47	int ret;
 48
 49	/*XXX: shared sub-WPR headers, fill terminator for now. */
 50	nvkm_wo32(acr->wpr, 0x200, 0xffffffff);
 51
 52	/* Fill per-LSF structures. */
 53	list_for_each_entry(lsfw, &acr->lsfw, head) {
 54		struct lsf_signature_v1 *sig = (void *)lsfw->sig->data;
 55		struct wpr_header_v1 hdr = {
 56			.falcon_id = lsfw->id,
 57			.lsb_offset = lsfw->offset.lsb,
 58			.bootstrap_owner = NVKM_ACR_LSF_GSPLITE,
 59			.lazy_bootstrap = 1,
 60			.bin_version = sig->version,
 61			.status = WPR_HEADER_V1_STATUS_COPY,
 62		};
 63
 64		/* Write WPR header. */
 65		nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
 66		offset += sizeof(hdr);
 67
 68		/* Write LSB header. */
 69		ret = gp102_acr_wpr_build_lsb(acr, lsfw);
 70		if (ret)
 71			return ret;
 72
 73		/* Write ucode image. */
 74		nvkm_wobj(acr->wpr, lsfw->offset.img,
 75				    lsfw->img.data,
 76				    lsfw->img.size);
 77
 78		/* Write bootloader data. */
 79		lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
 80	}
 81
 82	/* Finalise WPR. */
 83	nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID);
 84	return 0;
 85}
 86
 87static int
 88tu102_acr_hsfw_nofw(struct nvkm_acr *acr, const char *bl, const char *fw,
 89		    const char *name, int version,
 90		    const struct nvkm_acr_hsf_fwif *fwif)
 91{
 92	return 0;
 93}
 94
 95MODULE_FIRMWARE("nvidia/tu102/acr/unload_bl.bin");
 96MODULE_FIRMWARE("nvidia/tu102/acr/ucode_unload.bin");
 97
 98MODULE_FIRMWARE("nvidia/tu104/acr/unload_bl.bin");
 99MODULE_FIRMWARE("nvidia/tu104/acr/ucode_unload.bin");
100
101MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin");
102MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin");
103
104MODULE_FIRMWARE("nvidia/tu116/acr/unload_bl.bin");
105MODULE_FIRMWARE("nvidia/tu116/acr/ucode_unload.bin");
106
107MODULE_FIRMWARE("nvidia/tu117/acr/unload_bl.bin");
108MODULE_FIRMWARE("nvidia/tu117/acr/ucode_unload.bin");
109
110static const struct nvkm_acr_hsf_fwif
111tu102_acr_unload_fwif[] = {
112	{  0, gm200_acr_hsfw_ctor, &gp108_acr_hsfw_0, NVKM_ACR_HSF_PMU, 0, 0x00000000 },
113	{ -1, tu102_acr_hsfw_nofw },
114	{}
115};
116
117MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin");
118MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin");
119MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin");
120MODULE_FIRMWARE("nvidia/tu116/acr/ucode_asb.bin");
121MODULE_FIRMWARE("nvidia/tu117/acr/ucode_asb.bin");
122
123static const struct nvkm_acr_hsf_fwif
124tu102_acr_asb_fwif[] = {
125	{  0, gm200_acr_hsfw_ctor, &gp108_acr_hsfw_0, NVKM_ACR_HSF_GSP, 0, 0x00000000 },
126	{ -1, tu102_acr_hsfw_nofw },
127	{}
128};
129
130MODULE_FIRMWARE("nvidia/tu102/acr/bl.bin");
131MODULE_FIRMWARE("nvidia/tu102/acr/ucode_ahesasc.bin");
132
133MODULE_FIRMWARE("nvidia/tu104/acr/bl.bin");
134MODULE_FIRMWARE("nvidia/tu104/acr/ucode_ahesasc.bin");
135
136MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin");
137MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin");
138
139MODULE_FIRMWARE("nvidia/tu116/acr/bl.bin");
140MODULE_FIRMWARE("nvidia/tu116/acr/ucode_ahesasc.bin");
141
142MODULE_FIRMWARE("nvidia/tu117/acr/bl.bin");
143MODULE_FIRMWARE("nvidia/tu117/acr/ucode_ahesasc.bin");
144
145static const struct nvkm_acr_hsf_fwif
146tu102_acr_ahesasc_fwif[] = {
147	{  0, gm200_acr_hsfw_ctor, &gp108_acr_load_0, NVKM_ACR_HSF_SEC2, 0, 0x00000000 },
148	{ -1, tu102_acr_hsfw_nofw },
149	{}
150};
151
152static const struct nvkm_acr_func
153tu102_acr = {
154	.ahesasc = tu102_acr_ahesasc_fwif,
155	.asb = tu102_acr_asb_fwif,
156	.unload = tu102_acr_unload_fwif,
157	.wpr_parse = gp102_acr_wpr_parse,
158	.wpr_layout = gp102_acr_wpr_layout,
159	.wpr_alloc = gp102_acr_wpr_alloc,
160	.wpr_patch = gp102_acr_wpr_patch,
161	.wpr_build = tu102_acr_wpr_build,
162	.wpr_check = gm200_acr_wpr_check,
163	.init = tu102_acr_init,
164};
165
166static int
167tu102_acr_load(struct nvkm_acr *acr, int version,
168	       const struct nvkm_acr_fwif *fwif)
169{
170	struct nvkm_subdev *subdev = &acr->subdev;
171	const struct nvkm_acr_hsf_fwif *hsfwif;
172
173	hsfwif = nvkm_firmware_load(subdev, fwif->func->ahesasc, "AcrAHESASC",
174				    acr, "acr/bl", "acr/ucode_ahesasc",
175				    "AHESASC");
176	if (IS_ERR(hsfwif))
177		return PTR_ERR(hsfwif);
178
179	hsfwif = nvkm_firmware_load(subdev, fwif->func->asb, "AcrASB",
180				    acr, "acr/bl", "acr/ucode_asb", "ASB");
181	if (IS_ERR(hsfwif))
182		return PTR_ERR(hsfwif);
183
184	hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
185				    acr, "acr/unload_bl", "acr/ucode_unload",
186				    "unload");
187	if (IS_ERR(hsfwif))
188		return PTR_ERR(hsfwif);
189
190	return 0;
191}
192
193static const struct nvkm_acr_fwif
194tu102_acr_fwif[] = {
195	{  0, tu102_acr_load, &tu102_acr },
196	{ -1, gm200_acr_nofw, &gm200_acr },
197	{}
198};
199
200int
201tu102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
202	      struct nvkm_acr **pacr)
203{
204	if (nvkm_gsp_rm(device->gsp))
205		return -ENODEV;
206
207	return nvkm_acr_new_(tu102_acr_fwif, device, type, inst, pacr);
208}