gm200.c

  1/*
  2 * Copyright 2019 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22#include "priv.h"
 23
 24#include <core/falcon.h>
 25#include <core/firmware.h>
 26#include <core/memory.h>
 27#include <subdev/mc.h>
 28#include <subdev/mmu.h>
 29#include <subdev/pmu.h>
 30#include <subdev/timer.h>
 31
 32#include <nvfw/acr.h>
 33#include <nvfw/flcn.h>
 34
 35const struct nvkm_acr_func
 36gm200_acr = {
 37};
 38
 39int
 40gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
 41{
 42	nvkm_warn(&acr->subdev, "firmware unavailable\n");
 43	return 0;
 44}
 45
 46int
 47gm200_acr_init(struct nvkm_acr *acr)
 48{
 49	return nvkm_acr_hsfw_boot(acr, "load");
 50}
 51
 52void
 53gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit)
 54{
 55	struct nvkm_device *device = acr->subdev.device;
 56
 57	nvkm_wr32(device, 0x100cd4, 2);
 58	*start = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
 59	nvkm_wr32(device, 0x100cd4, 3);
 60	*limit = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
 61	*limit = *limit + 0x20000;
 62}
 63
 64int
 65gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
 66{
 67	struct nvkm_subdev *subdev = &acr->subdev;
 68	struct wpr_header hdr;
 69	struct lsb_header lsb;
 70	struct nvkm_acr_lsf *lsfw;
 71	u32 offset = 0;
 72
 73	do {
 74		nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
 75		wpr_header_dump(subdev, &hdr);
 76
 77		list_for_each_entry(lsfw, &acr->lsfw, head) {
 78			if (lsfw->id != hdr.falcon_id)
 79				continue;
 80
 81			nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
 82			lsb_header_dump(subdev, &lsb);
 83
 84			lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
 85			break;
 86		}
 87		offset += sizeof(hdr);
 88	} while (hdr.falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID);
 89
 90	return 0;
 91}
 92
 93void
 94gm200_acr_wpr_build_lsb_tail(struct nvkm_acr_lsfw *lsfw,
 95			     struct lsb_header_tail *hdr)
 96{
 97	hdr->ucode_off = lsfw->offset.img;
 98	hdr->ucode_size = lsfw->ucode_size;
 99	hdr->data_size = lsfw->data_size;
100	hdr->bl_code_size = lsfw->bootloader_size;
101	hdr->bl_imem_off = lsfw->bootloader_imem_offset;
102	hdr->bl_data_off = lsfw->offset.bld;
103	hdr->bl_data_size = lsfw->bl_data_size;
104	hdr->app_code_off = lsfw->app_start_offset +
105			   lsfw->app_resident_code_offset;
106	hdr->app_code_size = lsfw->app_resident_code_size;
107	hdr->app_data_off = lsfw->app_start_offset +
108			   lsfw->app_resident_data_offset;
109	hdr->app_data_size = lsfw->app_resident_data_size;
110	hdr->flags = lsfw->func->flags;
111}
112
113static int
114gm200_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
115{
116	struct lsb_header hdr;
117
118	if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature)))
119		return -EINVAL;
120
121	memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size);
122	gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail);
123
124	nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr));
125	return 0;
126}
127
128int
129gm200_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
130{
131	struct nvkm_acr_lsfw *lsfw;
132	u32 offset = 0;
133	int ret;
134
135	/* Fill per-LSF structures. */
136	list_for_each_entry(lsfw, &acr->lsfw, head) {
137		struct wpr_header hdr = {
138			.falcon_id = lsfw->id,
139			.lsb_offset = lsfw->offset.lsb,
140			.bootstrap_owner = NVKM_ACR_LSF_PMU,
141			.lazy_bootstrap = rtos && lsfw->id != rtos->id,
142			.status = WPR_HEADER_V0_STATUS_COPY,
143		};
144
145		/* Write WPR header. */
146		nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
147		offset += sizeof(hdr);
148
149		/* Write LSB header. */
150		ret = gm200_acr_wpr_build_lsb(acr, lsfw);
151		if (ret)
152			return ret;
153
154		/* Write ucode image. */
155		nvkm_wobj(acr->wpr, lsfw->offset.img,
156				    lsfw->img.data,
157				    lsfw->img.size);
158
159		/* Write bootloader data. */
160		lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
161	}
162
163	/* Finalise WPR. */
164	nvkm_wo32(acr->wpr, offset, WPR_HEADER_V0_FALCON_ID_INVALID);
165	return 0;
166}
167
168static int
169gm200_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
170{
171	int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST,
172				  ALIGN(wpr_size, 0x40000), 0x40000, true,
173				  &acr->wpr);
174	if (ret)
175		return ret;
176
177	acr->wpr_start = nvkm_memory_addr(acr->wpr);
178	acr->wpr_end = acr->wpr_start + nvkm_memory_size(acr->wpr);
179	return 0;
180}
181
182u32
183gm200_acr_wpr_layout(struct nvkm_acr *acr)
184{
185	struct nvkm_acr_lsfw *lsfw;
186	u32 wpr = 0;
187
188	wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header);
189
190	list_for_each_entry(lsfw, &acr->lsfw, head) {
191		wpr  = ALIGN(wpr, 256);
192		lsfw->offset.lsb = wpr;
193		wpr += sizeof(struct lsb_header);
194
195		wpr  = ALIGN(wpr, 4096);
196		lsfw->offset.img = wpr;
197		wpr += lsfw->img.size;
198
199		wpr  = ALIGN(wpr, 256);
200		lsfw->offset.bld = wpr;
201		lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256);
202		wpr += lsfw->bl_data_size;
203	}
204
205	return wpr;
206}
207
208int
209gm200_acr_wpr_parse(struct nvkm_acr *acr)
210{
211	const struct wpr_header *hdr = (void *)acr->wpr_fw->data;
212	struct nvkm_acr_lsfw *lsfw;
213
214	while (hdr->falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID) {
215		wpr_header_dump(&acr->subdev, hdr);
216		lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id);
217		if (IS_ERR(lsfw))
218			return PTR_ERR(lsfw);
219	}
220
221	return 0;
222}
223
224int
225gm200_acr_hsfw_load_bld(struct nvkm_falcon_fw *fw)
226{
227	struct flcn_bl_dmem_desc_v1 hsdesc = {
228		.ctx_dma = FALCON_DMAIDX_VIRT,
229		.code_dma_base = fw->vma->addr,
230		.non_sec_code_off = fw->nmem_base,
231		.non_sec_code_size = fw->nmem_size,
232		.sec_code_off = fw->imem_base,
233		.sec_code_size = fw->imem_size,
234		.code_entry_point = 0,
235		.data_dma_base = fw->vma->addr + fw->dmem_base_img,
236		.data_size = fw->dmem_size,
237	};
238
239	flcn_bl_dmem_desc_v1_dump(fw->falcon->user, &hsdesc);
240
241	return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);
242}
243
244int
245gm200_acr_hsfw_ctor(struct nvkm_acr *acr, const char *bl, const char *fw, const char *name, int ver,
246		    const struct nvkm_acr_hsf_fwif *fwif)
247{
248	struct nvkm_acr_hsfw *hsfw;
249
250	if (!(hsfw = kzalloc(sizeof(*hsfw), GFP_KERNEL)))
251		return -ENOMEM;
252
253	hsfw->falcon_id = fwif->falcon_id;
254	hsfw->boot_mbox0 = fwif->boot_mbox0;
255	hsfw->intr_clear = fwif->intr_clear;
256	list_add_tail(&hsfw->head, &acr->hsfw);
257
258	return nvkm_falcon_fw_ctor_hs(fwif->func, name, &acr->subdev, bl, fw, ver, NULL, &hsfw->fw);
259}
260
261const struct nvkm_falcon_fw_func
262gm200_acr_unload_0 = {
263	.signature = gm200_flcn_fw_signature,
264	.reset = gm200_flcn_fw_reset,
265	.load = gm200_flcn_fw_load,
266	.load_bld = gm200_acr_hsfw_load_bld,
267	.boot = gm200_flcn_fw_boot,
268};
269
270MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin");
271MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin");
272MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin");
273MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin");
274
275static const struct nvkm_acr_hsf_fwif
276gm200_acr_unload_fwif[] = {
277	{ 0, gm200_acr_hsfw_ctor, &gm200_acr_unload_0, NVKM_ACR_HSF_PMU, 0, 0x00000010 },
278	{}
279};
280
281static int
282gm200_acr_load_setup(struct nvkm_falcon_fw *fw)
283{
284	struct flcn_acr_desc *desc = (void *)&fw->fw.img[fw->dmem_base_img];
285	struct nvkm_acr *acr = fw->falcon->owner->device->acr;
286
287	desc->wpr_region_id = 1;
288	desc->regions.no_regions = 2;
289	desc->regions.region_props[0].start_addr = acr->wpr_start >> 8;
290	desc->regions.region_props[0].end_addr = acr->wpr_end >> 8;
291	desc->regions.region_props[0].region_id = 1;
292	desc->regions.region_props[0].read_mask = 0xf;
293	desc->regions.region_props[0].write_mask = 0xc;
294	desc->regions.region_props[0].client_mask = 0x2;
295	flcn_acr_desc_dump(&acr->subdev, desc);
296	return 0;
297}
298
299static const struct nvkm_falcon_fw_func
300gm200_acr_load_0 = {
301	.signature = gm200_flcn_fw_signature,
302	.reset = gm200_flcn_fw_reset,
303	.setup = gm200_acr_load_setup,
304	.load = gm200_flcn_fw_load,
305	.load_bld = gm200_acr_hsfw_load_bld,
306	.boot = gm200_flcn_fw_boot,
307};
308
309MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin");
310MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin");
311
312MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin");
313MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin");
314
315MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin");
316MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin");
317
318MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin");
319MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin");
320
321static const struct nvkm_acr_hsf_fwif
322gm200_acr_load_fwif[] = {
323	{ 0, gm200_acr_hsfw_ctor, &gm200_acr_load_0, NVKM_ACR_HSF_PMU, 0, 0x00000010 },
324	{}
325};
326
327static const struct nvkm_acr_func
328gm200_acr_0 = {
329	.load = gm200_acr_load_fwif,
330	.unload = gm200_acr_unload_fwif,
331	.wpr_parse = gm200_acr_wpr_parse,
332	.wpr_layout = gm200_acr_wpr_layout,
333	.wpr_alloc = gm200_acr_wpr_alloc,
334	.wpr_build = gm200_acr_wpr_build,
335	.wpr_patch = gm200_acr_wpr_patch,
336	.wpr_check = gm200_acr_wpr_check,
337	.init = gm200_acr_init,
338	.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
339			     BIT_ULL(NVKM_ACR_LSF_GPCCS),
340};
341
342static int
343gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
344{
345	struct nvkm_subdev *subdev = &acr->subdev;
346	const struct nvkm_acr_hsf_fwif *hsfwif;
347
348	hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
349				    acr, "acr/bl", "acr/ucode_load", "load");
350	if (IS_ERR(hsfwif))
351		return PTR_ERR(hsfwif);
352
353	hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
354				    acr, "acr/bl", "acr/ucode_unload",
355				    "unload");
356	if (IS_ERR(hsfwif))
357		return PTR_ERR(hsfwif);
358
359	return 0;
360}
361
362static const struct nvkm_acr_fwif
363gm200_acr_fwif[] = {
364	{  0, gm200_acr_load, &gm200_acr_0 },
365	{ -1, gm200_acr_nofw, &gm200_acr },
366	{}
367};
368
369int
370gm200_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
371	      struct nvkm_acr **pacr)
372{
373	return nvkm_acr_new_(gm200_acr_fwif, device, type, inst, pacr);
374}