nv30.c

  1// SPDX-License-Identifier: MIT
  2#include "nv20.h"
  3#include "regs.h"
  4
  5#include <core/gpuobj.h>
  6#include <engine/fifo.h>
  7#include <engine/fifo/chan.h>
  8#include <subdev/fb.h>
  9
 10/*******************************************************************************
 11 * PGRAPH context
 12 ******************************************************************************/
 13
 14static const struct nvkm_object_func
 15nv30_gr_chan = {
 16	.dtor = nv20_gr_chan_dtor,
 17	.init = nv20_gr_chan_init,
 18	.fini = nv20_gr_chan_fini,
 19};
 20
 21static int
 22nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
 23		 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
 24{
 25	struct nv20_gr *gr = nv20_gr(base);
 26	struct nv20_gr_chan *chan;
 27	int ret, i;
 28
 29	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 30		return -ENOMEM;
 31	nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object);
 32	chan->gr = gr;
 33	chan->chid = fifoch->id;
 34	*pobject = &chan->object;
 35
 36	ret = nvkm_memory_new(gr->base.engine.subdev.device,
 37			      NVKM_MEM_TARGET_INST, 0x5f48, 16, true,
 38			      &chan->inst);
 39	if (ret)
 40		return ret;
 41
 42	nvkm_kmap(chan->inst);
 43	nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
 44	nvkm_wo32(chan->inst, 0x0410, 0x00000101);
 45	nvkm_wo32(chan->inst, 0x0424, 0x00000111);
 46	nvkm_wo32(chan->inst, 0x0428, 0x00000060);
 47	nvkm_wo32(chan->inst, 0x0444, 0x00000080);
 48	nvkm_wo32(chan->inst, 0x0448, 0xffff0000);
 49	nvkm_wo32(chan->inst, 0x044c, 0x00000001);
 50	nvkm_wo32(chan->inst, 0x0460, 0x44400000);
 51	nvkm_wo32(chan->inst, 0x048c, 0xffff0000);
 52	for (i = 0x04e0; i < 0x04e8; i += 4)
 53		nvkm_wo32(chan->inst, i, 0x0fff0000);
 54	nvkm_wo32(chan->inst, 0x04ec, 0x00011100);
 55	for (i = 0x0508; i < 0x0548; i += 4)
 56		nvkm_wo32(chan->inst, i, 0x07ff0000);
 57	nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff);
 58	nvkm_wo32(chan->inst, 0x058c, 0x00000080);
 59	nvkm_wo32(chan->inst, 0x0590, 0x30201000);
 60	nvkm_wo32(chan->inst, 0x0594, 0x70605040);
 61	nvkm_wo32(chan->inst, 0x0598, 0xb8a89888);
 62	nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8);
 63	nvkm_wo32(chan->inst, 0x05b0, 0xb0000000);
 64	for (i = 0x0600; i < 0x0640; i += 4)
 65		nvkm_wo32(chan->inst, i, 0x00010588);
 66	for (i = 0x0640; i < 0x0680; i += 4)
 67		nvkm_wo32(chan->inst, i, 0x00030303);
 68	for (i = 0x06c0; i < 0x0700; i += 4)
 69		nvkm_wo32(chan->inst, i, 0x0008aae4);
 70	for (i = 0x0700; i < 0x0740; i += 4)
 71		nvkm_wo32(chan->inst, i, 0x01012000);
 72	for (i = 0x0740; i < 0x0780; i += 4)
 73		nvkm_wo32(chan->inst, i, 0x00080008);
 74	nvkm_wo32(chan->inst, 0x085c, 0x00040000);
 75	nvkm_wo32(chan->inst, 0x0860, 0x00010000);
 76	for (i = 0x0864; i < 0x0874; i += 4)
 77		nvkm_wo32(chan->inst, i, 0x00040004);
 78	for (i = 0x1f18; i <= 0x3088 ; i += 16) {
 79		nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
 80		nvkm_wo32(chan->inst, i + 4, 0x0436086c);
 81		nvkm_wo32(chan->inst, i + 8, 0x000c001b);
 82	}
 83	for (i = 0x30b8; i < 0x30c8; i += 4)
 84		nvkm_wo32(chan->inst, i, 0x0000ffff);
 85	nvkm_wo32(chan->inst, 0x344c, 0x3f800000);
 86	nvkm_wo32(chan->inst, 0x3808, 0x3f800000);
 87	nvkm_wo32(chan->inst, 0x381c, 0x3f800000);
 88	nvkm_wo32(chan->inst, 0x3848, 0x40000000);
 89	nvkm_wo32(chan->inst, 0x384c, 0x3f800000);
 90	nvkm_wo32(chan->inst, 0x3850, 0x3f000000);
 91	nvkm_wo32(chan->inst, 0x3858, 0x40000000);
 92	nvkm_wo32(chan->inst, 0x385c, 0x3f800000);
 93	nvkm_wo32(chan->inst, 0x3864, 0xbf800000);
 94	nvkm_wo32(chan->inst, 0x386c, 0xbf800000);
 95	nvkm_done(chan->inst);
 96	return 0;
 97}
 98
 99/*******************************************************************************
100 * PGRAPH engine/subdev functions
101 ******************************************************************************/
102
103int
104nv30_gr_init(struct nvkm_gr *base)
105{
106	struct nv20_gr *gr = nv20_gr(base);
107	struct nvkm_device *device = gr->base.engine.subdev.device;
108
109	nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
110			  nvkm_memory_addr(gr->ctxtab) >> 4);
111
112	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
113	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
114
115	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
116	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
117	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);
118	nvkm_wr32(device, 0x400890, 0x01b463ff);
119	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
120	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);
121	nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
122	nvkm_wr32(device, 0x400B80, 0x1003d888);
123	nvkm_wr32(device, 0x400B84, 0x0c000000);
124	nvkm_wr32(device, 0x400098, 0x00000000);
125	nvkm_wr32(device, 0x40009C, 0x0005ad00);
126	nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
127	nvkm_wr32(device, 0x4000a0, 0x00000000);
128	nvkm_wr32(device, 0x4000a4, 0x00000008);
129	nvkm_wr32(device, 0x4008a8, 0xb784a400);
130	nvkm_wr32(device, 0x400ba0, 0x002f8685);
131	nvkm_wr32(device, 0x400ba4, 0x00231f3f);
132	nvkm_wr32(device, 0x4008a4, 0x40000020);
133
134	if (device->chipset == 0x34) {
135		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
136		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201);
137		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
138		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008);
139		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
140		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032);
141		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
142		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002);
143	}
144
145	nvkm_wr32(device, 0x4000c0, 0x00000016);
146
147	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
148	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
149	nvkm_wr32(device, 0x0040075c             , 0x00000001);
150
151	/* begin RAM config */
152	/* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */
153	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
154	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
155	if (device->chipset != 0x34) {
156		nvkm_wr32(device, 0x400750, 0x00EA0000);
157		nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200));
158		nvkm_wr32(device, 0x400750, 0x00EA0004);
159		nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204));
160	}
161
162	return 0;
163}
164
165static const struct nvkm_gr_func
166nv30_gr = {
167	.dtor = nv20_gr_dtor,
168	.oneinit = nv20_gr_oneinit,
169	.init = nv30_gr_init,
170	.intr = nv20_gr_intr,
171	.tile = nv20_gr_tile,
172	.chan_new = nv30_gr_chan_new,
173	.sclass = {
174		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
175		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
176		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
177		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
178		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
179		{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
180		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
181		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
182		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
183		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
184		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
185		{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
186		{ -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
187		{ -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
188		{ -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
189		{ -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
190		{ -1, -1, 0x0397, &nv04_gr_object }, /* rankine */
191		{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
192		{}
193	}
194};
195
196int
197nv30_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
198{
199	return nv20_gr_new_(&nv30_gr, device, type, inst, pgr);
200}