gf117.c

  1/*
  2 * Copyright 2013 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs <bskeggs@redhat.com>
 23 */
 24#include "gf100.h"
 25#include "ctxgf100.h"
 26
 27#include <nvif/class.h>
 28
 29/*******************************************************************************
 30 * PGRAPH register lists
 31 ******************************************************************************/
 32
 33static const struct gf100_gr_init
 34gf117_gr_init_pe_0[] = {
 35	{ 0x41980c,   1, 0x04, 0x00000010 },
 36	{ 0x419844,   1, 0x04, 0x00000000 },
 37	{ 0x41984c,   1, 0x04, 0x00005bc8 },
 38	{ 0x419850,   3, 0x04, 0x00000000 },
 39	{}
 40};
 41
 42const struct gf100_gr_init
 43gf117_gr_init_pes_0[] = {
 44	{ 0x41be04,   1, 0x04, 0x00000000 },
 45	{ 0x41be08,   1, 0x04, 0x00000004 },
 46	{ 0x41be0c,   1, 0x04, 0x00000000 },
 47	{ 0x41be10,   1, 0x04, 0x003b8bc7 },
 48	{ 0x41be14,   2, 0x04, 0x00000000 },
 49	{}
 50};
 51
 52const struct gf100_gr_init
 53gf117_gr_init_wwdx_0[] = {
 54	{ 0x41bfd4,   1, 0x04, 0x00800000 },
 55	{ 0x41bfdc,   1, 0x04, 0x00000000 },
 56	{ 0x41bff8,   2, 0x04, 0x00000000 },
 57	{}
 58};
 59
 60const struct gf100_gr_init
 61gf117_gr_init_cbm_0[] = {
 62	{ 0x41becc,   1, 0x04, 0x00000000 },
 63	{ 0x41bee8,   2, 0x04, 0x00000000 },
 64	{}
 65};
 66
 67static const struct gf100_gr_pack
 68gf117_gr_pack_mmio[] = {
 69	{ gf100_gr_init_main_0 },
 70	{ gf100_gr_init_fe_0 },
 71	{ gf100_gr_init_pri_0 },
 72	{ gf100_gr_init_rstr2d_0 },
 73	{ gf119_gr_init_pd_0 },
 74	{ gf119_gr_init_ds_0 },
 75	{ gf100_gr_init_scc_0 },
 76	{ gf119_gr_init_prop_0 },
 77	{ gf108_gr_init_gpc_unk_0 },
 78	{ gf100_gr_init_setup_0 },
 79	{ gf100_gr_init_crstr_0 },
 80	{ gf108_gr_init_setup_1 },
 81	{ gf100_gr_init_zcull_0 },
 82	{ gf119_gr_init_gpm_0 },
 83	{ gf119_gr_init_gpc_unk_1 },
 84	{ gf100_gr_init_gcc_0 },
 85	{ gf100_gr_init_tpccs_0 },
 86	{ gf119_gr_init_tex_0 },
 87	{ gf117_gr_init_pe_0 },
 88	{ gf100_gr_init_l1c_0 },
 89	{ gf100_gr_init_mpc_0 },
 90	{ gf119_gr_init_sm_0 },
 91	{ gf117_gr_init_pes_0 },
 92	{ gf117_gr_init_wwdx_0 },
 93	{ gf117_gr_init_cbm_0 },
 94	{ gf100_gr_init_be_0 },
 95	{ gf119_gr_init_fe_1 },
 96	{}
 97};
 98
 99/*******************************************************************************
100 * PGRAPH engine/subdev functions
101 ******************************************************************************/
102
103#include "fuc/hubgf117.fuc3.h"
104
105static struct gf100_gr_ucode
106gf117_gr_fecs_ucode = {
107	.code.data = gf117_grhub_code,
108	.code.size = sizeof(gf117_grhub_code),
109	.data.data = gf117_grhub_data,
110	.data.size = sizeof(gf117_grhub_data),
111};
112
113#include "fuc/gpcgf117.fuc3.h"
114
115static struct gf100_gr_ucode
116gf117_gr_gpccs_ucode = {
117	.code.data = gf117_grgpc_code,
118	.code.size = sizeof(gf117_grgpc_code),
119	.data.data = gf117_grgpc_data,
120	.data.size = sizeof(gf117_grgpc_data),
121};
122
123void
124gf117_gr_init_zcull(struct gf100_gr *gr)
125{
126	struct nvkm_device *device = gr->base.engine.subdev.device;
127	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
128	/*TODO: fill in litter vals for gf117-gm2xx */
129	const u8 tile_nr = !gr->func->gpc_nr ? ALIGN(gr->tpc_total, 32) :
130			   (gr->func->gpc_nr * gr->func->tpc_nr);
131	u8 bank[GPC_MAX] = {}, gpc, i, j;
132	u32 data;
133
134	for (i = 0; i < tile_nr; i += 8) {
135		for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
136			data |= bank[gr->tile[i + j]] << (j * 4);
137			bank[gr->tile[i + j]]++;
138		}
139		nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
140	}
141
142	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
143		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
144			  gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
145		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
146							 gr->tpc_total);
147		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
148	}
149
150	nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
151}
152
153static const struct gf100_gr_func
154gf117_gr = {
155	.oneinit_tiles = gf100_gr_oneinit_tiles,
156	.oneinit_sm_id = gf100_gr_oneinit_sm_id,
157	.init = gf100_gr_init,
158	.init_gpc_mmu = gf100_gr_init_gpc_mmu,
159	.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
160	.init_zcull = gf117_gr_init_zcull,
161	.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
162	.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
163	.init_40601c = gf100_gr_init_40601c,
164	.init_419cc0 = gf100_gr_init_419cc0,
165	.init_419eb4 = gf100_gr_init_419eb4,
166	.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
167	.init_shader_exceptions = gf100_gr_init_shader_exceptions,
168	.init_rop_exceptions = gf100_gr_init_rop_exceptions,
169	.init_exception2 = gf100_gr_init_exception2,
170	.init_400054 = gf100_gr_init_400054,
171	.trap_mp = gf100_gr_trap_mp,
172	.mmio = gf117_gr_pack_mmio,
173	.fecs.ucode = &gf117_gr_fecs_ucode,
174	.fecs.reset = gf100_gr_fecs_reset,
175	.gpccs.ucode = &gf117_gr_gpccs_ucode,
176	.rops = gf100_gr_rops,
177	.ppc_nr = 1,
178	.grctx = &gf117_grctx,
179	.zbc = &gf100_gr_zbc,
180	.sclass = {
181		{ -1, -1, FERMI_TWOD_A },
182		{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
183		{ -1, -1, FERMI_A, &gf100_fermi },
184		{ -1, -1, FERMI_B, &gf100_fermi },
185		{ -1, -1, FERMI_C, &gf100_fermi },
186		{ -1, -1, FERMI_COMPUTE_A },
187		{ -1, -1, FERMI_COMPUTE_B },
188		{}
189	}
190};
191
192static const struct gf100_gr_fwif
193gf117_gr_fwif[] = {
194	{ -1, gf100_gr_load, &gf117_gr },
195	{ -1, gf100_gr_nofw, &gf117_gr },
196	{}
197};
198
199int
200gf117_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
201{
202	return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr);
203}