gv100.c

  1/*
  2 * Copyright 2018 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22#include "priv.h"
 23#include "chan.h"
 24#include "chid.h"
 25#include "cgrp.h"
 26#include "runl.h"
 27#include "runq.h"
 28
 29#include <core/gpuobj.h>
 30#include <subdev/mmu.h>
 31
 32#include <nvif/class.h>
 33
 34static u32
 35gv100_chan_doorbell_handle(struct nvkm_chan *chan)
 36{
 37	return chan->id;
 38}
 39
 40static int
 41gv100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
 42{
 43	const u64 userd = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
 44	const u32 limit2 = ilog2(length / 8);
 45
 46	nvkm_kmap(chan->inst);
 47	nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd));
 48	nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd));
 49	nvkm_wo32(chan->inst, 0x010, 0x0000face);
 50	nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
 51	nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
 52	nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
 53	nvkm_wo32(chan->inst, 0x084, 0x20400000);
 54	nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
 55	nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
 56	nvkm_wo32(chan->inst, 0x0e8, chan->id);
 57	nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));
 58	nvkm_wo32(chan->inst, 0x0f8, 0x10003080);
 59	nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
 60	nvkm_done(chan->inst);
 61	return 0;
 62}
 63
 64const struct nvkm_chan_func_ramfc
 65gv100_chan_ramfc = {
 66	.write = gv100_chan_ramfc_write,
 67	.devm = 0xfff,
 68	.priv = true,
 69};
 70
 71const struct nvkm_chan_func_userd
 72gv100_chan_userd = {
 73	.size = 0x200,
 74	.clear = gf100_chan_userd_clear,
 75};
 76
 77static const struct nvkm_chan_func
 78gv100_chan = {
 79	.inst = &gf100_chan_inst,
 80	.userd = &gv100_chan_userd,
 81	.ramfc = &gv100_chan_ramfc,
 82	.bind = gk104_chan_bind_inst,
 83	.unbind = gk104_chan_unbind,
 84	.start = gk104_chan_start,
 85	.stop = gk104_chan_stop,
 86	.preempt = gk110_chan_preempt,
 87	.doorbell_handle = gv100_chan_doorbell_handle,
 88};
 89
 90void
 91gv100_ectx_bind(struct nvkm_engn *engn, struct nvkm_cctx *cctx, struct nvkm_chan *chan)
 92{
 93	u64 addr = 0ULL;
 94
 95	if (cctx) {
 96		addr  = cctx->vctx->vma->addr;
 97		addr |= 4ULL;
 98	}
 99
100	nvkm_kmap(chan->inst);
101	nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr));
102	nvkm_wo32(chan->inst, 0x214, upper_32_bits(addr));
103	nvkm_mo32(chan->inst, 0x0ac, 0x00010000, cctx ? 0x00010000 : 0x00000000);
104	nvkm_done(chan->inst);
105}
106
107const struct nvkm_engn_func
108gv100_engn = {
109	.chsw = gk104_engn_chsw,
110	.cxid = gk104_engn_cxid,
111	.ctor = gk104_ectx_ctor,
112	.bind = gv100_ectx_bind,
113};
114
115void
116gv100_ectx_ce_bind(struct nvkm_engn *engn, struct nvkm_cctx *cctx, struct nvkm_chan *chan)
117{
118	const u64 bar2 = cctx ? nvkm_memory_bar2(cctx->vctx->inst->memory) : 0ULL;
119
120	nvkm_kmap(chan->inst);
121	nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2));
122	nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2));
123	nvkm_mo32(chan->inst, 0x0ac, 0x00020000, cctx ? 0x00020000 : 0x00000000);
124	nvkm_done(chan->inst);
125}
126
127int
128gv100_ectx_ce_ctor(struct nvkm_engn *engn, struct nvkm_vctx *vctx)
129{
130	if (nvkm_memory_bar2(vctx->inst->memory) == ~0ULL)
131		return -EFAULT;
132
133	return 0;
134}
135
136const struct nvkm_engn_func
137gv100_engn_ce = {
138	.chsw = gk104_engn_chsw,
139	.cxid = gk104_engn_cxid,
140	.ctor = gv100_ectx_ce_ctor,
141	.bind = gv100_ectx_ce_bind,
142};
143
144static bool
145gv100_runq_intr_1_ctxnotvalid(struct nvkm_runq *runq, int chid)
146{
147	struct nvkm_fifo *fifo = runq->fifo;
148	struct nvkm_device *device = fifo->engine.subdev.device;
149	struct nvkm_chan *chan;
150	unsigned long flags;
151
152	RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid);
153
154	chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
155	if (WARN_ON_ONCE(!chan))
156		return false;
157
158	nvkm_chan_error(chan, true);
159	nvkm_chan_put(&chan, flags);
160
161	nvkm_mask(device, 0x0400ac + (runq->id * 0x2000), 0x00030000, 0x00030000);
162	nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), 0x80000000);
163	return true;
164}
165
166const struct nvkm_runq_func
167gv100_runq = {
168	.init = gk208_runq_init,
169	.intr = gk104_runq_intr,
170	.intr_0_names = gk104_runq_intr_0_names,
171	.intr_1_ctxnotvalid = gv100_runq_intr_1_ctxnotvalid,
172	.idle = gk104_runq_idle,
173};
174
175void
176gv100_runl_preempt(struct nvkm_runl *runl)
177{
178	nvkm_wr32(runl->fifo->engine.subdev.device, 0x002638, BIT(runl->id));
179}
180
181void
182gv100_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset)
183{
184	const u64 user = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
185	const u64 inst = chan->inst->addr;
186
187	nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1);
188	nvkm_wo32(memory, offset + 0x4, upper_32_bits(user));
189	nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id);
190	nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst));
191}
192
193void
194gv100_runl_insert_cgrp(struct nvkm_cgrp *cgrp, struct nvkm_memory *memory, u64 offset)
195{
196	nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001);
197	nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr);
198	nvkm_wo32(memory, offset + 0x8, cgrp->id);
199	nvkm_wo32(memory, offset + 0xc, 0x00000000);
200}
201
202static const struct nvkm_runl_func
203gv100_runl = {
204	.runqs = 2,
205	.size = 16,
206	.update = nv50_runl_update,
207	.insert_cgrp = gv100_runl_insert_cgrp,
208	.insert_chan = gv100_runl_insert_chan,
209	.commit = gk104_runl_commit,
210	.wait = nv50_runl_wait,
211	.pending = gk104_runl_pending,
212	.block = gk104_runl_block,
213	.allow = gk104_runl_allow,
214	.preempt = gv100_runl_preempt,
215	.preempt_pending = gf100_runl_preempt_pending,
216};
217
218const struct nvkm_enum
219gv100_fifo_mmu_fault_gpcclient[] = {
220	{ 0x00, "T1_0" },
221	{ 0x01, "T1_1" },
222	{ 0x02, "T1_2" },
223	{ 0x03, "T1_3" },
224	{ 0x04, "T1_4" },
225	{ 0x05, "T1_5" },
226	{ 0x06, "T1_6" },
227	{ 0x07, "T1_7" },
228	{ 0x08, "PE_0" },
229	{ 0x09, "PE_1" },
230	{ 0x0a, "PE_2" },
231	{ 0x0b, "PE_3" },
232	{ 0x0c, "PE_4" },
233	{ 0x0d, "PE_5" },
234	{ 0x0e, "PE_6" },
235	{ 0x0f, "PE_7" },
236	{ 0x10, "RAST" },
237	{ 0x11, "GCC" },
238	{ 0x12, "GPCCS" },
239	{ 0x13, "PROP_0" },
240	{ 0x14, "PROP_1" },
241	{ 0x15, "PROP_2" },
242	{ 0x16, "PROP_3" },
243	{ 0x17, "GPM" },
244	{ 0x18, "LTP_UTLB_0" },
245	{ 0x19, "LTP_UTLB_1" },
246	{ 0x1a, "LTP_UTLB_2" },
247	{ 0x1b, "LTP_UTLB_3" },
248	{ 0x1c, "LTP_UTLB_4" },
249	{ 0x1d, "LTP_UTLB_5" },
250	{ 0x1e, "LTP_UTLB_6" },
251	{ 0x1f, "LTP_UTLB_7" },
252	{ 0x20, "RGG_UTLB" },
253	{ 0x21, "T1_8" },
254	{ 0x22, "T1_9" },
255	{ 0x23, "T1_10" },
256	{ 0x24, "T1_11" },
257	{ 0x25, "T1_12" },
258	{ 0x26, "T1_13" },
259	{ 0x27, "T1_14" },
260	{ 0x28, "T1_15" },
261	{ 0x29, "TPCCS_0" },
262	{ 0x2a, "TPCCS_1" },
263	{ 0x2b, "TPCCS_2" },
264	{ 0x2c, "TPCCS_3" },
265	{ 0x2d, "TPCCS_4" },
266	{ 0x2e, "TPCCS_5" },
267	{ 0x2f, "TPCCS_6" },
268	{ 0x30, "TPCCS_7" },
269	{ 0x31, "PE_8" },
270	{ 0x32, "PE_9" },
271	{ 0x33, "TPCCS_8" },
272	{ 0x34, "TPCCS_9" },
273	{ 0x35, "T1_16" },
274	{ 0x36, "T1_17" },
275	{ 0x37, "T1_18" },
276	{ 0x38, "T1_19" },
277	{ 0x39, "PE_10" },
278	{ 0x3a, "PE_11" },
279	{ 0x3b, "TPCCS_10" },
280	{ 0x3c, "TPCCS_11" },
281	{ 0x3d, "T1_20" },
282	{ 0x3e, "T1_21" },
283	{ 0x3f, "T1_22" },
284	{ 0x40, "T1_23" },
285	{ 0x41, "PE_12" },
286	{ 0x42, "PE_13" },
287	{ 0x43, "TPCCS_12" },
288	{ 0x44, "TPCCS_13" },
289	{ 0x45, "T1_24" },
290	{ 0x46, "T1_25" },
291	{ 0x47, "T1_26" },
292	{ 0x48, "T1_27" },
293	{ 0x49, "PE_14" },
294	{ 0x4a, "PE_15" },
295	{ 0x4b, "TPCCS_14" },
296	{ 0x4c, "TPCCS_15" },
297	{ 0x4d, "T1_28" },
298	{ 0x4e, "T1_29" },
299	{ 0x4f, "T1_30" },
300	{ 0x50, "T1_31" },
301	{ 0x51, "PE_16" },
302	{ 0x52, "PE_17" },
303	{ 0x53, "TPCCS_16" },
304	{ 0x54, "TPCCS_17" },
305	{ 0x55, "T1_32" },
306	{ 0x56, "T1_33" },
307	{ 0x57, "T1_34" },
308	{ 0x58, "T1_35" },
309	{ 0x59, "PE_18" },
310	{ 0x5a, "PE_19" },
311	{ 0x5b, "TPCCS_18" },
312	{ 0x5c, "TPCCS_19" },
313	{ 0x5d, "T1_36" },
314	{ 0x5e, "T1_37" },
315	{ 0x5f, "T1_38" },
316	{ 0x60, "T1_39" },
317	{}
318};
319
320const struct nvkm_enum
321gv100_fifo_mmu_fault_hubclient[] = {
322	{ 0x00, "VIP" },
323	{ 0x01, "CE0" },
324	{ 0x02, "CE1" },
325	{ 0x03, "DNISO" },
326	{ 0x04, "FE" },
327	{ 0x05, "FECS" },
328	{ 0x06, "HOST" },
329	{ 0x07, "HOST_CPU" },
330	{ 0x08, "HOST_CPU_NB" },
331	{ 0x09, "ISO" },
332	{ 0x0a, "MMU" },
333	{ 0x0b, "NVDEC" },
334	{ 0x0d, "NVENC1" },
335	{ 0x0e, "NISO" },
336	{ 0x0f, "P2P" },
337	{ 0x10, "PD" },
338	{ 0x11, "PERF" },
339	{ 0x12, "PMU" },
340	{ 0x13, "RASTERTWOD" },
341	{ 0x14, "SCC" },
342	{ 0x15, "SCC_NB" },
343	{ 0x16, "SEC" },
344	{ 0x17, "SSYNC" },
345	{ 0x18, "CE2" },
346	{ 0x19, "XV" },
347	{ 0x1a, "MMU_NB" },
348	{ 0x1b, "NVENC0" },
349	{ 0x1c, "DFALCON" },
350	{ 0x1d, "SKED" },
351	{ 0x1e, "AFALCON" },
352	{ 0x1f, "DONT_CARE" },
353	{ 0x20, "HSCE0" },
354	{ 0x21, "HSCE1" },
355	{ 0x22, "HSCE2" },
356	{ 0x23, "HSCE3" },
357	{ 0x24, "HSCE4" },
358	{ 0x25, "HSCE5" },
359	{ 0x26, "HSCE6" },
360	{ 0x27, "HSCE7" },
361	{ 0x28, "HSCE8" },
362	{ 0x29, "HSCE9" },
363	{ 0x2a, "HSHUB" },
364	{ 0x2b, "PTP_X0" },
365	{ 0x2c, "PTP_X1" },
366	{ 0x2d, "PTP_X2" },
367	{ 0x2e, "PTP_X3" },
368	{ 0x2f, "PTP_X4" },
369	{ 0x30, "PTP_X5" },
370	{ 0x31, "PTP_X6" },
371	{ 0x32, "PTP_X7" },
372	{ 0x33, "NVENC2" },
373	{ 0x34, "VPR_SCRUBBER0" },
374	{ 0x35, "VPR_SCRUBBER1" },
375	{ 0x36, "DWBIF" },
376	{ 0x37, "FBFALCON" },
377	{ 0x38, "CE_SHIM" },
378	{ 0x39, "GSP" },
379	{}
380};
381
382const struct nvkm_enum
383gv100_fifo_mmu_fault_reason[] = {
384	{ 0x00, "PDE" },
385	{ 0x01, "PDE_SIZE" },
386	{ 0x02, "PTE" },
387	{ 0x03, "VA_LIMIT_VIOLATION" },
388	{ 0x04, "UNBOUND_INST_BLOCK" },
389	{ 0x05, "PRIV_VIOLATION" },
390	{ 0x06, "RO_VIOLATION" },
391	{ 0x07, "WO_VIOLATION" },
392	{ 0x08, "PITCH_MASK_VIOLATION" },
393	{ 0x09, "WORK_CREATION" },
394	{ 0x0a, "UNSUPPORTED_APERTURE" },
395	{ 0x0b, "COMPRESSION_FAILURE" },
396	{ 0x0c, "UNSUPPORTED_KIND" },
397	{ 0x0d, "REGION_VIOLATION" },
398	{ 0x0e, "POISONED" },
399	{ 0x0f, "ATOMIC_VIOLATION" },
400	{}
401};
402
403static const struct nvkm_enum
404gv100_fifo_mmu_fault_engine[] = {
405	{ 0x01, "DISPLAY" },
406	{ 0x03, "PTP" },
407	{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
408	{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
409	{ 0x06, "PWR_PMU" },
410	{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
411	{ 0x09, "PERF" },
412	{ 0x1f, "PHYSICAL" },
413	{ 0x20, "HOST0" },
414	{ 0x21, "HOST1" },
415	{ 0x22, "HOST2" },
416	{ 0x23, "HOST3" },
417	{ 0x24, "HOST4" },
418	{ 0x25, "HOST5" },
419	{ 0x26, "HOST6" },
420	{ 0x27, "HOST7" },
421	{ 0x28, "HOST8" },
422	{ 0x29, "HOST9" },
423	{ 0x2a, "HOST10" },
424	{ 0x2b, "HOST11" },
425	{ 0x2c, "HOST12" },
426	{ 0x2d, "HOST13" },
427	{}
428};
429
430const struct nvkm_enum
431gv100_fifo_mmu_fault_access[] = {
432	{ 0x0, "VIRT_READ" },
433	{ 0x1, "VIRT_WRITE" },
434	{ 0x2, "VIRT_ATOMIC" },
435	{ 0x3, "VIRT_PREFETCH" },
436	{ 0x4, "VIRT_ATOMIC_WEAK" },
437	{ 0x8, "PHYS_READ" },
438	{ 0x9, "PHYS_WRITE" },
439	{ 0xa, "PHYS_ATOMIC" },
440	{ 0xb, "PHYS_PREFETCH" },
441	{}
442};
443
444static const struct nvkm_fifo_func_mmu_fault
445gv100_fifo_mmu_fault = {
446	.recover = gf100_fifo_mmu_fault_recover,
447	.access = gv100_fifo_mmu_fault_access,
448	.engine = gv100_fifo_mmu_fault_engine,
449	.reason = gv100_fifo_mmu_fault_reason,
450	.hubclient = gv100_fifo_mmu_fault_hubclient,
451	.gpcclient = gv100_fifo_mmu_fault_gpcclient,
452};
453
454static void
455gv100_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo, u32 engm)
456{
457	struct nvkm_runl *runl;
458	struct nvkm_engn *engn;
459
460	nvkm_runl_foreach(runl, fifo) {
461		nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id))
462			nvkm_runl_rc_engn(runl, engn);
463	}
464}
465
466static const struct nvkm_fifo_func
467gv100_fifo = {
468	.chid_nr = gm200_fifo_chid_nr,
469	.chid_ctor = gk110_fifo_chid_ctor,
470	.runq_nr = gm200_fifo_runq_nr,
471	.runl_ctor = gk104_fifo_runl_ctor,
472	.init = gk104_fifo_init,
473	.init_pbdmas = gk104_fifo_init_pbdmas,
474	.intr = gk104_fifo_intr,
475	.intr_ctxsw_timeout = gv100_fifo_intr_ctxsw_timeout,
476	.mmu_fault = &gv100_fifo_mmu_fault,
477	.nonstall = &gf100_fifo_nonstall,
478	.runl = &gv100_runl,
479	.runq = &gv100_runq,
480	.engn = &gv100_engn,
481	.engn_ce = &gv100_engn_ce,
482	.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp, .force = true },
483	.chan = {{ 0, 0,  VOLTA_CHANNEL_GPFIFO_A }, &gv100_chan },
484};
485
486int
487gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
488	       struct nvkm_fifo **pfifo)
489{
490	return nvkm_fifo_new_(&gv100_fifo, device, type, inst, pfifo);
491}