base.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "priv.h"
  25#include "acpi.h"
  26
  27#include <core/option.h>
  28
  29#include <subdev/bios.h>
  30#include <subdev/therm.h>
  31
  32static DEFINE_MUTEX(nv_devices_mutex);
  33static LIST_HEAD(nv_devices);
  34
  35static struct nvkm_device *
  36nvkm_device_find_locked(u64 handle)
  37{
  38	struct nvkm_device *device;
  39	list_for_each_entry(device, &nv_devices, head) {
  40		if (device->handle == handle)
  41			return device;
  42	}
  43	return NULL;
  44}
  45
  46struct nvkm_device *
  47nvkm_device_find(u64 handle)
  48{
  49	struct nvkm_device *device;
  50	mutex_lock(&nv_devices_mutex);
  51	device = nvkm_device_find_locked(handle);
  52	mutex_unlock(&nv_devices_mutex);
  53	return device;
  54}
  55
  56static const struct nvkm_device_chip
  57nv4_chipset = {
  58	.name = "NV04",
  59	.bios     = { 0x00000001, nvkm_bios_new },
  60	.bus      = { 0x00000001, nv04_bus_new },
  61	.clk      = { 0x00000001, nv04_clk_new },
  62	.devinit  = { 0x00000001, nv04_devinit_new },
  63	.fb       = { 0x00000001, nv04_fb_new },
  64	.i2c      = { 0x00000001, nv04_i2c_new },
  65	.imem     = { 0x00000001, nv04_instmem_new },
  66	.mc       = { 0x00000001, nv04_mc_new },
  67	.mmu      = { 0x00000001, nv04_mmu_new },
  68	.pci      = { 0x00000001, nv04_pci_new },
  69	.timer    = { 0x00000001, nv04_timer_new },
  70	.disp     = { 0x00000001, nv04_disp_new },
  71	.dma      = { 0x00000001, nv04_dma_new },
  72	.fifo     = { 0x00000001, nv04_fifo_new },
  73	.gr       = { 0x00000001, nv04_gr_new },
  74	.sw       = { 0x00000001, nv04_sw_new },
  75};
  76
  77static const struct nvkm_device_chip
  78nv5_chipset = {
  79	.name = "NV05",
  80	.bios     = { 0x00000001, nvkm_bios_new },
  81	.bus      = { 0x00000001, nv04_bus_new },
  82	.clk      = { 0x00000001, nv04_clk_new },
  83	.devinit  = { 0x00000001, nv05_devinit_new },
  84	.fb       = { 0x00000001, nv04_fb_new },
  85	.i2c      = { 0x00000001, nv04_i2c_new },
  86	.imem     = { 0x00000001, nv04_instmem_new },
  87	.mc       = { 0x00000001, nv04_mc_new },
  88	.mmu      = { 0x00000001, nv04_mmu_new },
  89	.pci      = { 0x00000001, nv04_pci_new },
  90	.timer    = { 0x00000001, nv04_timer_new },
  91	.disp     = { 0x00000001, nv04_disp_new },
  92	.dma      = { 0x00000001, nv04_dma_new },
  93	.fifo     = { 0x00000001, nv04_fifo_new },
  94	.gr       = { 0x00000001, nv04_gr_new },
  95	.sw       = { 0x00000001, nv04_sw_new },
  96};
  97
  98static const struct nvkm_device_chip
  99nv10_chipset = {
 100	.name = "NV10",
 101	.bios     = { 0x00000001, nvkm_bios_new },
 102	.bus      = { 0x00000001, nv04_bus_new },
 103	.clk      = { 0x00000001, nv04_clk_new },
 104	.devinit  = { 0x00000001, nv10_devinit_new },
 105	.fb       = { 0x00000001, nv10_fb_new },
 106	.gpio     = { 0x00000001, nv10_gpio_new },
 107	.i2c      = { 0x00000001, nv04_i2c_new },
 108	.imem     = { 0x00000001, nv04_instmem_new },
 109	.mc       = { 0x00000001, nv04_mc_new },
 110	.mmu      = { 0x00000001, nv04_mmu_new },
 111	.pci      = { 0x00000001, nv04_pci_new },
 112	.timer    = { 0x00000001, nv04_timer_new },
 113	.disp     = { 0x00000001, nv04_disp_new },
 114	.dma      = { 0x00000001, nv04_dma_new },
 115	.gr       = { 0x00000001, nv10_gr_new },
 116};
 117
 118static const struct nvkm_device_chip
 119nv11_chipset = {
 120	.name = "NV11",
 121	.bios     = { 0x00000001, nvkm_bios_new },
 122	.bus      = { 0x00000001, nv04_bus_new },
 123	.clk      = { 0x00000001, nv04_clk_new },
 124	.devinit  = { 0x00000001, nv10_devinit_new },
 125	.fb       = { 0x00000001, nv10_fb_new },
 126	.gpio     = { 0x00000001, nv10_gpio_new },
 127	.i2c      = { 0x00000001, nv04_i2c_new },
 128	.imem     = { 0x00000001, nv04_instmem_new },
 129	.mc       = { 0x00000001, nv11_mc_new },
 130	.mmu      = { 0x00000001, nv04_mmu_new },
 131	.pci      = { 0x00000001, nv04_pci_new },
 132	.timer    = { 0x00000001, nv04_timer_new },
 133	.disp     = { 0x00000001, nv04_disp_new },
 134	.dma      = { 0x00000001, nv04_dma_new },
 135	.fifo     = { 0x00000001, nv10_fifo_new },
 136	.gr       = { 0x00000001, nv15_gr_new },
 137	.sw       = { 0x00000001, nv10_sw_new },
 138};
 139
 140static const struct nvkm_device_chip
 141nv15_chipset = {
 142	.name = "NV15",
 143	.bios     = { 0x00000001, nvkm_bios_new },
 144	.bus      = { 0x00000001, nv04_bus_new },
 145	.clk      = { 0x00000001, nv04_clk_new },
 146	.devinit  = { 0x00000001, nv10_devinit_new },
 147	.fb       = { 0x00000001, nv10_fb_new },
 148	.gpio     = { 0x00000001, nv10_gpio_new },
 149	.i2c      = { 0x00000001, nv04_i2c_new },
 150	.imem     = { 0x00000001, nv04_instmem_new },
 151	.mc       = { 0x00000001, nv04_mc_new },
 152	.mmu      = { 0x00000001, nv04_mmu_new },
 153	.pci      = { 0x00000001, nv04_pci_new },
 154	.timer    = { 0x00000001, nv04_timer_new },
 155	.disp     = { 0x00000001, nv04_disp_new },
 156	.dma      = { 0x00000001, nv04_dma_new },
 157	.fifo     = { 0x00000001, nv10_fifo_new },
 158	.gr       = { 0x00000001, nv15_gr_new },
 159	.sw       = { 0x00000001, nv10_sw_new },
 160};
 161
 162static const struct nvkm_device_chip
 163nv17_chipset = {
 164	.name = "NV17",
 165	.bios     = { 0x00000001, nvkm_bios_new },
 166	.bus      = { 0x00000001, nv04_bus_new },
 167	.clk      = { 0x00000001, nv04_clk_new },
 168	.devinit  = { 0x00000001, nv10_devinit_new },
 169	.fb       = { 0x00000001, nv10_fb_new },
 170	.gpio     = { 0x00000001, nv10_gpio_new },
 171	.i2c      = { 0x00000001, nv04_i2c_new },
 172	.imem     = { 0x00000001, nv04_instmem_new },
 173	.mc       = { 0x00000001, nv17_mc_new },
 174	.mmu      = { 0x00000001, nv04_mmu_new },
 175	.pci      = { 0x00000001, nv04_pci_new },
 176	.timer    = { 0x00000001, nv04_timer_new },
 177	.disp     = { 0x00000001, nv04_disp_new },
 178	.dma      = { 0x00000001, nv04_dma_new },
 179	.fifo     = { 0x00000001, nv17_fifo_new },
 180	.gr       = { 0x00000001, nv17_gr_new },
 181	.sw       = { 0x00000001, nv10_sw_new },
 182};
 183
 184static const struct nvkm_device_chip
 185nv18_chipset = {
 186	.name = "NV18",
 187	.bios     = { 0x00000001, nvkm_bios_new },
 188	.bus      = { 0x00000001, nv04_bus_new },
 189	.clk      = { 0x00000001, nv04_clk_new },
 190	.devinit  = { 0x00000001, nv10_devinit_new },
 191	.fb       = { 0x00000001, nv10_fb_new },
 192	.gpio     = { 0x00000001, nv10_gpio_new },
 193	.i2c      = { 0x00000001, nv04_i2c_new },
 194	.imem     = { 0x00000001, nv04_instmem_new },
 195	.mc       = { 0x00000001, nv17_mc_new },
 196	.mmu      = { 0x00000001, nv04_mmu_new },
 197	.pci      = { 0x00000001, nv04_pci_new },
 198	.timer    = { 0x00000001, nv04_timer_new },
 199	.disp     = { 0x00000001, nv04_disp_new },
 200	.dma      = { 0x00000001, nv04_dma_new },
 201	.fifo     = { 0x00000001, nv17_fifo_new },
 202	.gr       = { 0x00000001, nv17_gr_new },
 203	.sw       = { 0x00000001, nv10_sw_new },
 204};
 205
 206static const struct nvkm_device_chip
 207nv1a_chipset = {
 208	.name = "nForce",
 209	.bios     = { 0x00000001, nvkm_bios_new },
 210	.bus      = { 0x00000001, nv04_bus_new },
 211	.clk      = { 0x00000001, nv04_clk_new },
 212	.devinit  = { 0x00000001, nv1a_devinit_new },
 213	.fb       = { 0x00000001, nv1a_fb_new },
 214	.gpio     = { 0x00000001, nv10_gpio_new },
 215	.i2c      = { 0x00000001, nv04_i2c_new },
 216	.imem     = { 0x00000001, nv04_instmem_new },
 217	.mc       = { 0x00000001, nv04_mc_new },
 218	.mmu      = { 0x00000001, nv04_mmu_new },
 219	.pci      = { 0x00000001, nv04_pci_new },
 220	.timer    = { 0x00000001, nv04_timer_new },
 221	.disp     = { 0x00000001, nv04_disp_new },
 222	.dma      = { 0x00000001, nv04_dma_new },
 223	.fifo     = { 0x00000001, nv10_fifo_new },
 224	.gr       = { 0x00000001, nv15_gr_new },
 225	.sw       = { 0x00000001, nv10_sw_new },
 226};
 227
 228static const struct nvkm_device_chip
 229nv1f_chipset = {
 230	.name = "nForce2",
 231	.bios     = { 0x00000001, nvkm_bios_new },
 232	.bus      = { 0x00000001, nv04_bus_new },
 233	.clk      = { 0x00000001, nv04_clk_new },
 234	.devinit  = { 0x00000001, nv1a_devinit_new },
 235	.fb       = { 0x00000001, nv1a_fb_new },
 236	.gpio     = { 0x00000001, nv10_gpio_new },
 237	.i2c      = { 0x00000001, nv04_i2c_new },
 238	.imem     = { 0x00000001, nv04_instmem_new },
 239	.mc       = { 0x00000001, nv17_mc_new },
 240	.mmu      = { 0x00000001, nv04_mmu_new },
 241	.pci      = { 0x00000001, nv04_pci_new },
 242	.timer    = { 0x00000001, nv04_timer_new },
 243	.disp     = { 0x00000001, nv04_disp_new },
 244	.dma      = { 0x00000001, nv04_dma_new },
 245	.fifo     = { 0x00000001, nv17_fifo_new },
 246	.gr       = { 0x00000001, nv17_gr_new },
 247	.sw       = { 0x00000001, nv10_sw_new },
 248};
 249
 250static const struct nvkm_device_chip
 251nv20_chipset = {
 252	.name = "NV20",
 253	.bios     = { 0x00000001, nvkm_bios_new },
 254	.bus      = { 0x00000001, nv04_bus_new },
 255	.clk      = { 0x00000001, nv04_clk_new },
 256	.devinit  = { 0x00000001, nv20_devinit_new },
 257	.fb       = { 0x00000001, nv20_fb_new },
 258	.gpio     = { 0x00000001, nv10_gpio_new },
 259	.i2c      = { 0x00000001, nv04_i2c_new },
 260	.imem     = { 0x00000001, nv04_instmem_new },
 261	.mc       = { 0x00000001, nv17_mc_new },
 262	.mmu      = { 0x00000001, nv04_mmu_new },
 263	.pci      = { 0x00000001, nv04_pci_new },
 264	.timer    = { 0x00000001, nv04_timer_new },
 265	.disp     = { 0x00000001, nv04_disp_new },
 266	.dma      = { 0x00000001, nv04_dma_new },
 267	.fifo     = { 0x00000001, nv17_fifo_new },
 268	.gr       = { 0x00000001, nv20_gr_new },
 269	.sw       = { 0x00000001, nv10_sw_new },
 270};
 271
 272static const struct nvkm_device_chip
 273nv25_chipset = {
 274	.name = "NV25",
 275	.bios     = { 0x00000001, nvkm_bios_new },
 276	.bus      = { 0x00000001, nv04_bus_new },
 277	.clk      = { 0x00000001, nv04_clk_new },
 278	.devinit  = { 0x00000001, nv20_devinit_new },
 279	.fb       = { 0x00000001, nv25_fb_new },
 280	.gpio     = { 0x00000001, nv10_gpio_new },
 281	.i2c      = { 0x00000001, nv04_i2c_new },
 282	.imem     = { 0x00000001, nv04_instmem_new },
 283	.mc       = { 0x00000001, nv17_mc_new },
 284	.mmu      = { 0x00000001, nv04_mmu_new },
 285	.pci      = { 0x00000001, nv04_pci_new },
 286	.timer    = { 0x00000001, nv04_timer_new },
 287	.disp     = { 0x00000001, nv04_disp_new },
 288	.dma      = { 0x00000001, nv04_dma_new },
 289	.fifo     = { 0x00000001, nv17_fifo_new },
 290	.gr       = { 0x00000001, nv25_gr_new },
 291	.sw       = { 0x00000001, nv10_sw_new },
 292};
 293
 294static const struct nvkm_device_chip
 295nv28_chipset = {
 296	.name = "NV28",
 297	.bios     = { 0x00000001, nvkm_bios_new },
 298	.bus      = { 0x00000001, nv04_bus_new },
 299	.clk      = { 0x00000001, nv04_clk_new },
 300	.devinit  = { 0x00000001, nv20_devinit_new },
 301	.fb       = { 0x00000001, nv25_fb_new },
 302	.gpio     = { 0x00000001, nv10_gpio_new },
 303	.i2c      = { 0x00000001, nv04_i2c_new },
 304	.imem     = { 0x00000001, nv04_instmem_new },
 305	.mc       = { 0x00000001, nv17_mc_new },
 306	.mmu      = { 0x00000001, nv04_mmu_new },
 307	.pci      = { 0x00000001, nv04_pci_new },
 308	.timer    = { 0x00000001, nv04_timer_new },
 309	.disp     = { 0x00000001, nv04_disp_new },
 310	.dma      = { 0x00000001, nv04_dma_new },
 311	.fifo     = { 0x00000001, nv17_fifo_new },
 312	.gr       = { 0x00000001, nv25_gr_new },
 313	.sw       = { 0x00000001, nv10_sw_new },
 314};
 315
 316static const struct nvkm_device_chip
 317nv2a_chipset = {
 318	.name = "NV2A",
 319	.bios     = { 0x00000001, nvkm_bios_new },
 320	.bus      = { 0x00000001, nv04_bus_new },
 321	.clk      = { 0x00000001, nv04_clk_new },
 322	.devinit  = { 0x00000001, nv20_devinit_new },
 323	.fb       = { 0x00000001, nv25_fb_new },
 324	.gpio     = { 0x00000001, nv10_gpio_new },
 325	.i2c      = { 0x00000001, nv04_i2c_new },
 326	.imem     = { 0x00000001, nv04_instmem_new },
 327	.mc       = { 0x00000001, nv17_mc_new },
 328	.mmu      = { 0x00000001, nv04_mmu_new },
 329	.pci      = { 0x00000001, nv04_pci_new },
 330	.timer    = { 0x00000001, nv04_timer_new },
 331	.disp     = { 0x00000001, nv04_disp_new },
 332	.dma      = { 0x00000001, nv04_dma_new },
 333	.fifo     = { 0x00000001, nv17_fifo_new },
 334	.gr       = { 0x00000001, nv2a_gr_new },
 335	.sw       = { 0x00000001, nv10_sw_new },
 336};
 337
 338static const struct nvkm_device_chip
 339nv30_chipset = {
 340	.name = "NV30",
 341	.bios     = { 0x00000001, nvkm_bios_new },
 342	.bus      = { 0x00000001, nv04_bus_new },
 343	.clk      = { 0x00000001, nv04_clk_new },
 344	.devinit  = { 0x00000001, nv20_devinit_new },
 345	.fb       = { 0x00000001, nv30_fb_new },
 346	.gpio     = { 0x00000001, nv10_gpio_new },
 347	.i2c      = { 0x00000001, nv04_i2c_new },
 348	.imem     = { 0x00000001, nv04_instmem_new },
 349	.mc       = { 0x00000001, nv17_mc_new },
 350	.mmu      = { 0x00000001, nv04_mmu_new },
 351	.pci      = { 0x00000001, nv04_pci_new },
 352	.timer    = { 0x00000001, nv04_timer_new },
 353	.disp     = { 0x00000001, nv04_disp_new },
 354	.dma      = { 0x00000001, nv04_dma_new },
 355	.fifo     = { 0x00000001, nv17_fifo_new },
 356	.gr       = { 0x00000001, nv30_gr_new },
 357	.sw       = { 0x00000001, nv10_sw_new },
 358};
 359
 360static const struct nvkm_device_chip
 361nv31_chipset = {
 362	.name = "NV31",
 363	.bios     = { 0x00000001, nvkm_bios_new },
 364	.bus      = { 0x00000001, nv31_bus_new },
 365	.clk      = { 0x00000001, nv04_clk_new },
 366	.devinit  = { 0x00000001, nv20_devinit_new },
 367	.fb       = { 0x00000001, nv30_fb_new },
 368	.gpio     = { 0x00000001, nv10_gpio_new },
 369	.i2c      = { 0x00000001, nv04_i2c_new },
 370	.imem     = { 0x00000001, nv04_instmem_new },
 371	.mc       = { 0x00000001, nv17_mc_new },
 372	.mmu      = { 0x00000001, nv04_mmu_new },
 373	.pci      = { 0x00000001, nv04_pci_new },
 374	.timer    = { 0x00000001, nv04_timer_new },
 375	.disp     = { 0x00000001, nv04_disp_new },
 376	.dma      = { 0x00000001, nv04_dma_new },
 377	.fifo     = { 0x00000001, nv17_fifo_new },
 378	.gr       = { 0x00000001, nv30_gr_new },
 379	.mpeg     = { 0x00000001, nv31_mpeg_new },
 380	.sw       = { 0x00000001, nv10_sw_new },
 381};
 382
 383static const struct nvkm_device_chip
 384nv34_chipset = {
 385	.name = "NV34",
 386	.bios     = { 0x00000001, nvkm_bios_new },
 387	.bus      = { 0x00000001, nv31_bus_new },
 388	.clk      = { 0x00000001, nv04_clk_new },
 389	.devinit  = { 0x00000001, nv10_devinit_new },
 390	.fb       = { 0x00000001, nv10_fb_new },
 391	.gpio     = { 0x00000001, nv10_gpio_new },
 392	.i2c      = { 0x00000001, nv04_i2c_new },
 393	.imem     = { 0x00000001, nv04_instmem_new },
 394	.mc       = { 0x00000001, nv17_mc_new },
 395	.mmu      = { 0x00000001, nv04_mmu_new },
 396	.pci      = { 0x00000001, nv04_pci_new },
 397	.timer    = { 0x00000001, nv04_timer_new },
 398	.disp     = { 0x00000001, nv04_disp_new },
 399	.dma      = { 0x00000001, nv04_dma_new },
 400	.fifo     = { 0x00000001, nv17_fifo_new },
 401	.gr       = { 0x00000001, nv34_gr_new },
 402	.mpeg     = { 0x00000001, nv31_mpeg_new },
 403	.sw       = { 0x00000001, nv10_sw_new },
 404};
 405
 406static const struct nvkm_device_chip
 407nv35_chipset = {
 408	.name = "NV35",
 409	.bios     = { 0x00000001, nvkm_bios_new },
 410	.bus      = { 0x00000001, nv04_bus_new },
 411	.clk      = { 0x00000001, nv04_clk_new },
 412	.devinit  = { 0x00000001, nv20_devinit_new },
 413	.fb       = { 0x00000001, nv35_fb_new },
 414	.gpio     = { 0x00000001, nv10_gpio_new },
 415	.i2c      = { 0x00000001, nv04_i2c_new },
 416	.imem     = { 0x00000001, nv04_instmem_new },
 417	.mc       = { 0x00000001, nv17_mc_new },
 418	.mmu      = { 0x00000001, nv04_mmu_new },
 419	.pci      = { 0x00000001, nv04_pci_new },
 420	.timer    = { 0x00000001, nv04_timer_new },
 421	.disp     = { 0x00000001, nv04_disp_new },
 422	.dma      = { 0x00000001, nv04_dma_new },
 423	.fifo     = { 0x00000001, nv17_fifo_new },
 424	.gr       = { 0x00000001, nv35_gr_new },
 425	.sw       = { 0x00000001, nv10_sw_new },
 426};
 427
 428static const struct nvkm_device_chip
 429nv36_chipset = {
 430	.name = "NV36",
 431	.bios     = { 0x00000001, nvkm_bios_new },
 432	.bus      = { 0x00000001, nv31_bus_new },
 433	.clk      = { 0x00000001, nv04_clk_new },
 434	.devinit  = { 0x00000001, nv20_devinit_new },
 435	.fb       = { 0x00000001, nv36_fb_new },
 436	.gpio     = { 0x00000001, nv10_gpio_new },
 437	.i2c      = { 0x00000001, nv04_i2c_new },
 438	.imem     = { 0x00000001, nv04_instmem_new },
 439	.mc       = { 0x00000001, nv17_mc_new },
 440	.mmu      = { 0x00000001, nv04_mmu_new },
 441	.pci      = { 0x00000001, nv04_pci_new },
 442	.timer    = { 0x00000001, nv04_timer_new },
 443	.disp     = { 0x00000001, nv04_disp_new },
 444	.dma      = { 0x00000001, nv04_dma_new },
 445	.fifo     = { 0x00000001, nv17_fifo_new },
 446	.gr       = { 0x00000001, nv35_gr_new },
 447	.mpeg     = { 0x00000001, nv31_mpeg_new },
 448	.sw       = { 0x00000001, nv10_sw_new },
 449};
 450
 451static const struct nvkm_device_chip
 452nv40_chipset = {
 453	.name = "NV40",
 454	.bios     = { 0x00000001, nvkm_bios_new },
 455	.bus      = { 0x00000001, nv31_bus_new },
 456	.clk      = { 0x00000001, nv40_clk_new },
 457	.devinit  = { 0x00000001, nv1a_devinit_new },
 458	.fb       = { 0x00000001, nv40_fb_new },
 459	.gpio     = { 0x00000001, nv10_gpio_new },
 460	.i2c      = { 0x00000001, nv04_i2c_new },
 461	.imem     = { 0x00000001, nv40_instmem_new },
 462	.mc       = { 0x00000001, nv17_mc_new },
 463	.mmu      = { 0x00000001, nv04_mmu_new },
 464	.pci      = { 0x00000001, nv40_pci_new },
 465	.therm    = { 0x00000001, nv40_therm_new },
 466	.timer    = { 0x00000001, nv40_timer_new },
 467	.volt     = { 0x00000001, nv40_volt_new },
 468	.disp     = { 0x00000001, nv04_disp_new },
 469	.dma      = { 0x00000001, nv04_dma_new },
 470	.fifo     = { 0x00000001, nv40_fifo_new },
 471	.gr       = { 0x00000001, nv40_gr_new },
 472	.mpeg     = { 0x00000001, nv40_mpeg_new },
 473	.sw       = { 0x00000001, nv10_sw_new },
 474};
 475
 476static const struct nvkm_device_chip
 477nv41_chipset = {
 478	.name = "NV41",
 479	.bios     = { 0x00000001, nvkm_bios_new },
 480	.bus      = { 0x00000001, nv31_bus_new },
 481	.clk      = { 0x00000001, nv40_clk_new },
 482	.devinit  = { 0x00000001, nv1a_devinit_new },
 483	.fb       = { 0x00000001, nv41_fb_new },
 484	.gpio     = { 0x00000001, nv10_gpio_new },
 485	.i2c      = { 0x00000001, nv04_i2c_new },
 486	.imem     = { 0x00000001, nv40_instmem_new },
 487	.mc       = { 0x00000001, nv17_mc_new },
 488	.mmu      = { 0x00000001, nv41_mmu_new },
 489	.pci      = { 0x00000001, nv40_pci_new },
 490	.therm    = { 0x00000001, nv40_therm_new },
 491	.timer    = { 0x00000001, nv41_timer_new },
 492	.volt     = { 0x00000001, nv40_volt_new },
 493	.disp     = { 0x00000001, nv04_disp_new },
 494	.dma      = { 0x00000001, nv04_dma_new },
 495	.fifo     = { 0x00000001, nv40_fifo_new },
 496	.gr       = { 0x00000001, nv40_gr_new },
 497	.mpeg     = { 0x00000001, nv40_mpeg_new },
 498	.sw       = { 0x00000001, nv10_sw_new },
 499};
 500
 501static const struct nvkm_device_chip
 502nv42_chipset = {
 503	.name = "NV42",
 504	.bios     = { 0x00000001, nvkm_bios_new },
 505	.bus      = { 0x00000001, nv31_bus_new },
 506	.clk      = { 0x00000001, nv40_clk_new },
 507	.devinit  = { 0x00000001, nv1a_devinit_new },
 508	.fb       = { 0x00000001, nv41_fb_new },
 509	.gpio     = { 0x00000001, nv10_gpio_new },
 510	.i2c      = { 0x00000001, nv04_i2c_new },
 511	.imem     = { 0x00000001, nv40_instmem_new },
 512	.mc       = { 0x00000001, nv17_mc_new },
 513	.mmu      = { 0x00000001, nv41_mmu_new },
 514	.pci      = { 0x00000001, nv40_pci_new },
 515	.therm    = { 0x00000001, nv40_therm_new },
 516	.timer    = { 0x00000001, nv41_timer_new },
 517	.volt     = { 0x00000001, nv40_volt_new },
 518	.disp     = { 0x00000001, nv04_disp_new },
 519	.dma      = { 0x00000001, nv04_dma_new },
 520	.fifo     = { 0x00000001, nv40_fifo_new },
 521	.gr       = { 0x00000001, nv40_gr_new },
 522	.mpeg     = { 0x00000001, nv40_mpeg_new },
 523	.sw       = { 0x00000001, nv10_sw_new },
 524};
 525
 526static const struct nvkm_device_chip
 527nv43_chipset = {
 528	.name = "NV43",
 529	.bios     = { 0x00000001, nvkm_bios_new },
 530	.bus      = { 0x00000001, nv31_bus_new },
 531	.clk      = { 0x00000001, nv40_clk_new },
 532	.devinit  = { 0x00000001, nv1a_devinit_new },
 533	.fb       = { 0x00000001, nv41_fb_new },
 534	.gpio     = { 0x00000001, nv10_gpio_new },
 535	.i2c      = { 0x00000001, nv04_i2c_new },
 536	.imem     = { 0x00000001, nv40_instmem_new },
 537	.mc       = { 0x00000001, nv17_mc_new },
 538	.mmu      = { 0x00000001, nv41_mmu_new },
 539	.pci      = { 0x00000001, nv40_pci_new },
 540	.therm    = { 0x00000001, nv40_therm_new },
 541	.timer    = { 0x00000001, nv41_timer_new },
 542	.volt     = { 0x00000001, nv40_volt_new },
 543	.disp     = { 0x00000001, nv04_disp_new },
 544	.dma      = { 0x00000001, nv04_dma_new },
 545	.fifo     = { 0x00000001, nv40_fifo_new },
 546	.gr       = { 0x00000001, nv40_gr_new },
 547	.mpeg     = { 0x00000001, nv40_mpeg_new },
 548	.sw       = { 0x00000001, nv10_sw_new },
 549};
 550
 551static const struct nvkm_device_chip
 552nv44_chipset = {
 553	.name = "NV44",
 554	.bios     = { 0x00000001, nvkm_bios_new },
 555	.bus      = { 0x00000001, nv31_bus_new },
 556	.clk      = { 0x00000001, nv40_clk_new },
 557	.devinit  = { 0x00000001, nv1a_devinit_new },
 558	.fb       = { 0x00000001, nv44_fb_new },
 559	.gpio     = { 0x00000001, nv10_gpio_new },
 560	.i2c      = { 0x00000001, nv04_i2c_new },
 561	.imem     = { 0x00000001, nv40_instmem_new },
 562	.mc       = { 0x00000001, nv44_mc_new },
 563	.mmu      = { 0x00000001, nv44_mmu_new },
 564	.pci      = { 0x00000001, nv40_pci_new },
 565	.therm    = { 0x00000001, nv40_therm_new },
 566	.timer    = { 0x00000001, nv41_timer_new },
 567	.volt     = { 0x00000001, nv40_volt_new },
 568	.disp     = { 0x00000001, nv04_disp_new },
 569	.dma      = { 0x00000001, nv04_dma_new },
 570	.fifo     = { 0x00000001, nv40_fifo_new },
 571	.gr       = { 0x00000001, nv44_gr_new },
 572	.mpeg     = { 0x00000001, nv44_mpeg_new },
 573	.sw       = { 0x00000001, nv10_sw_new },
 574};
 575
 576static const struct nvkm_device_chip
 577nv45_chipset = {
 578	.name = "NV45",
 579	.bios     = { 0x00000001, nvkm_bios_new },
 580	.bus      = { 0x00000001, nv31_bus_new },
 581	.clk      = { 0x00000001, nv40_clk_new },
 582	.devinit  = { 0x00000001, nv1a_devinit_new },
 583	.fb       = { 0x00000001, nv40_fb_new },
 584	.gpio     = { 0x00000001, nv10_gpio_new },
 585	.i2c      = { 0x00000001, nv04_i2c_new },
 586	.imem     = { 0x00000001, nv40_instmem_new },
 587	.mc       = { 0x00000001, nv17_mc_new },
 588	.mmu      = { 0x00000001, nv04_mmu_new },
 589	.pci      = { 0x00000001, nv40_pci_new },
 590	.therm    = { 0x00000001, nv40_therm_new },
 591	.timer    = { 0x00000001, nv41_timer_new },
 592	.volt     = { 0x00000001, nv40_volt_new },
 593	.disp     = { 0x00000001, nv04_disp_new },
 594	.dma      = { 0x00000001, nv04_dma_new },
 595	.fifo     = { 0x00000001, nv40_fifo_new },
 596	.gr       = { 0x00000001, nv40_gr_new },
 597	.mpeg     = { 0x00000001, nv44_mpeg_new },
 598	.sw       = { 0x00000001, nv10_sw_new },
 599};
 600
 601static const struct nvkm_device_chip
 602nv46_chipset = {
 603	.name = "G72",
 604	.bios     = { 0x00000001, nvkm_bios_new },
 605	.bus      = { 0x00000001, nv31_bus_new },
 606	.clk      = { 0x00000001, nv40_clk_new },
 607	.devinit  = { 0x00000001, nv1a_devinit_new },
 608	.fb       = { 0x00000001, nv46_fb_new },
 609	.gpio     = { 0x00000001, nv10_gpio_new },
 610	.i2c      = { 0x00000001, nv04_i2c_new },
 611	.imem     = { 0x00000001, nv40_instmem_new },
 612	.mc       = { 0x00000001, nv44_mc_new },
 613	.mmu      = { 0x00000001, nv44_mmu_new },
 614	.pci      = { 0x00000001, nv46_pci_new },
 615	.therm    = { 0x00000001, nv40_therm_new },
 616	.timer    = { 0x00000001, nv41_timer_new },
 617	.volt     = { 0x00000001, nv40_volt_new },
 618	.disp     = { 0x00000001, nv04_disp_new },
 619	.dma      = { 0x00000001, nv04_dma_new },
 620	.fifo     = { 0x00000001, nv40_fifo_new },
 621	.gr       = { 0x00000001, nv44_gr_new },
 622	.mpeg     = { 0x00000001, nv44_mpeg_new },
 623	.sw       = { 0x00000001, nv10_sw_new },
 624};
 625
 626static const struct nvkm_device_chip
 627nv47_chipset = {
 628	.name = "G70",
 629	.bios     = { 0x00000001, nvkm_bios_new },
 630	.bus      = { 0x00000001, nv31_bus_new },
 631	.clk      = { 0x00000001, nv40_clk_new },
 632	.devinit  = { 0x00000001, nv1a_devinit_new },
 633	.fb       = { 0x00000001, nv47_fb_new },
 634	.gpio     = { 0x00000001, nv10_gpio_new },
 635	.i2c      = { 0x00000001, nv04_i2c_new },
 636	.imem     = { 0x00000001, nv40_instmem_new },
 637	.mc       = { 0x00000001, nv17_mc_new },
 638	.mmu      = { 0x00000001, nv41_mmu_new },
 639	.pci      = { 0x00000001, nv40_pci_new },
 640	.therm    = { 0x00000001, nv40_therm_new },
 641	.timer    = { 0x00000001, nv41_timer_new },
 642	.volt     = { 0x00000001, nv40_volt_new },
 643	.disp     = { 0x00000001, nv04_disp_new },
 644	.dma      = { 0x00000001, nv04_dma_new },
 645	.fifo     = { 0x00000001, nv40_fifo_new },
 646	.gr       = { 0x00000001, nv40_gr_new },
 647	.mpeg     = { 0x00000001, nv44_mpeg_new },
 648	.sw       = { 0x00000001, nv10_sw_new },
 649};
 650
 651static const struct nvkm_device_chip
 652nv49_chipset = {
 653	.name = "G71",
 654	.bios     = { 0x00000001, nvkm_bios_new },
 655	.bus      = { 0x00000001, nv31_bus_new },
 656	.clk      = { 0x00000001, nv40_clk_new },
 657	.devinit  = { 0x00000001, nv1a_devinit_new },
 658	.fb       = { 0x00000001, nv49_fb_new },
 659	.gpio     = { 0x00000001, nv10_gpio_new },
 660	.i2c      = { 0x00000001, nv04_i2c_new },
 661	.imem     = { 0x00000001, nv40_instmem_new },
 662	.mc       = { 0x00000001, nv17_mc_new },
 663	.mmu      = { 0x00000001, nv41_mmu_new },
 664	.pci      = { 0x00000001, nv40_pci_new },
 665	.therm    = { 0x00000001, nv40_therm_new },
 666	.timer    = { 0x00000001, nv41_timer_new },
 667	.volt     = { 0x00000001, nv40_volt_new },
 668	.disp     = { 0x00000001, nv04_disp_new },
 669	.dma      = { 0x00000001, nv04_dma_new },
 670	.fifo     = { 0x00000001, nv40_fifo_new },
 671	.gr       = { 0x00000001, nv40_gr_new },
 672	.mpeg     = { 0x00000001, nv44_mpeg_new },
 673	.sw       = { 0x00000001, nv10_sw_new },
 674};
 675
 676static const struct nvkm_device_chip
 677nv4a_chipset = {
 678	.name = "NV44A",
 679	.bios     = { 0x00000001, nvkm_bios_new },
 680	.bus      = { 0x00000001, nv31_bus_new },
 681	.clk      = { 0x00000001, nv40_clk_new },
 682	.devinit  = { 0x00000001, nv1a_devinit_new },
 683	.fb       = { 0x00000001, nv44_fb_new },
 684	.gpio     = { 0x00000001, nv10_gpio_new },
 685	.i2c      = { 0x00000001, nv04_i2c_new },
 686	.imem     = { 0x00000001, nv40_instmem_new },
 687	.mc       = { 0x00000001, nv44_mc_new },
 688	.mmu      = { 0x00000001, nv04_mmu_new },
 689	.pci      = { 0x00000001, nv40_pci_new },
 690	.therm    = { 0x00000001, nv40_therm_new },
 691	.timer    = { 0x00000001, nv41_timer_new },
 692	.volt     = { 0x00000001, nv40_volt_new },
 693	.disp     = { 0x00000001, nv04_disp_new },
 694	.dma      = { 0x00000001, nv04_dma_new },
 695	.fifo     = { 0x00000001, nv40_fifo_new },
 696	.gr       = { 0x00000001, nv44_gr_new },
 697	.mpeg     = { 0x00000001, nv44_mpeg_new },
 698	.sw       = { 0x00000001, nv10_sw_new },
 699};
 700
 701static const struct nvkm_device_chip
 702nv4b_chipset = {
 703	.name = "G73",
 704	.bios     = { 0x00000001, nvkm_bios_new },
 705	.bus      = { 0x00000001, nv31_bus_new },
 706	.clk      = { 0x00000001, nv40_clk_new },
 707	.devinit  = { 0x00000001, nv1a_devinit_new },
 708	.fb       = { 0x00000001, nv49_fb_new },
 709	.gpio     = { 0x00000001, nv10_gpio_new },
 710	.i2c      = { 0x00000001, nv04_i2c_new },
 711	.imem     = { 0x00000001, nv40_instmem_new },
 712	.mc       = { 0x00000001, nv17_mc_new },
 713	.mmu      = { 0x00000001, nv41_mmu_new },
 714	.pci      = { 0x00000001, nv40_pci_new },
 715	.therm    = { 0x00000001, nv40_therm_new },
 716	.timer    = { 0x00000001, nv41_timer_new },
 717	.volt     = { 0x00000001, nv40_volt_new },
 718	.disp     = { 0x00000001, nv04_disp_new },
 719	.dma      = { 0x00000001, nv04_dma_new },
 720	.fifo     = { 0x00000001, nv40_fifo_new },
 721	.gr       = { 0x00000001, nv40_gr_new },
 722	.mpeg     = { 0x00000001, nv44_mpeg_new },
 723	.sw       = { 0x00000001, nv10_sw_new },
 724};
 725
 726static const struct nvkm_device_chip
 727nv4c_chipset = {
 728	.name = "C61",
 729	.bios     = { 0x00000001, nvkm_bios_new },
 730	.bus      = { 0x00000001, nv31_bus_new },
 731	.clk      = { 0x00000001, nv40_clk_new },
 732	.devinit  = { 0x00000001, nv1a_devinit_new },
 733	.fb       = { 0x00000001, nv46_fb_new },
 734	.gpio     = { 0x00000001, nv10_gpio_new },
 735	.i2c      = { 0x00000001, nv04_i2c_new },
 736	.imem     = { 0x00000001, nv40_instmem_new },
 737	.mc       = { 0x00000001, nv44_mc_new },
 738	.mmu      = { 0x00000001, nv44_mmu_new },
 739	.pci      = { 0x00000001, nv4c_pci_new },
 740	.therm    = { 0x00000001, nv40_therm_new },
 741	.timer    = { 0x00000001, nv41_timer_new },
 742	.volt     = { 0x00000001, nv40_volt_new },
 743	.disp     = { 0x00000001, nv04_disp_new },
 744	.dma      = { 0x00000001, nv04_dma_new },
 745	.fifo     = { 0x00000001, nv40_fifo_new },
 746	.gr       = { 0x00000001, nv44_gr_new },
 747	.mpeg     = { 0x00000001, nv44_mpeg_new },
 748	.sw       = { 0x00000001, nv10_sw_new },
 749};
 750
 751static const struct nvkm_device_chip
 752nv4e_chipset = {
 753	.name = "C51",
 754	.bios     = { 0x00000001, nvkm_bios_new },
 755	.bus      = { 0x00000001, nv31_bus_new },
 756	.clk      = { 0x00000001, nv40_clk_new },
 757	.devinit  = { 0x00000001, nv1a_devinit_new },
 758	.fb       = { 0x00000001, nv4e_fb_new },
 759	.gpio     = { 0x00000001, nv10_gpio_new },
 760	.i2c      = { 0x00000001, nv4e_i2c_new },
 761	.imem     = { 0x00000001, nv40_instmem_new },
 762	.mc       = { 0x00000001, nv44_mc_new },
 763	.mmu      = { 0x00000001, nv44_mmu_new },
 764	.pci      = { 0x00000001, nv4c_pci_new },
 765	.therm    = { 0x00000001, nv40_therm_new },
 766	.timer    = { 0x00000001, nv41_timer_new },
 767	.volt     = { 0x00000001, nv40_volt_new },
 768	.disp     = { 0x00000001, nv04_disp_new },
 769	.dma      = { 0x00000001, nv04_dma_new },
 770	.fifo     = { 0x00000001, nv40_fifo_new },
 771	.gr       = { 0x00000001, nv44_gr_new },
 772	.mpeg     = { 0x00000001, nv44_mpeg_new },
 773	.sw       = { 0x00000001, nv10_sw_new },
 774};
 775
 776static const struct nvkm_device_chip
 777nv50_chipset = {
 778	.name = "G80",
 779	.bar      = { 0x00000001, nv50_bar_new },
 780	.bios     = { 0x00000001, nvkm_bios_new },
 781	.bus      = { 0x00000001, nv50_bus_new },
 782	.clk      = { 0x00000001, nv50_clk_new },
 783	.devinit  = { 0x00000001, nv50_devinit_new },
 784	.fb       = { 0x00000001, nv50_fb_new },
 785	.fuse     = { 0x00000001, nv50_fuse_new },
 786	.gpio     = { 0x00000001, nv50_gpio_new },
 787	.i2c      = { 0x00000001, nv50_i2c_new },
 788	.imem     = { 0x00000001, nv50_instmem_new },
 789	.mc       = { 0x00000001, nv50_mc_new },
 790	.mmu      = { 0x00000001, nv50_mmu_new },
 791	.mxm      = { 0x00000001, nv50_mxm_new },
 792	.pci      = { 0x00000001, nv46_pci_new },
 793	.therm    = { 0x00000001, nv50_therm_new },
 794	.timer    = { 0x00000001, nv41_timer_new },
 795	.volt     = { 0x00000001, nv40_volt_new },
 796	.disp     = { 0x00000001, nv50_disp_new },
 797	.dma      = { 0x00000001, nv50_dma_new },
 798	.fifo     = { 0x00000001, nv50_fifo_new },
 799	.gr       = { 0x00000001, nv50_gr_new },
 800	.mpeg     = { 0x00000001, nv50_mpeg_new },
 801	.sw       = { 0x00000001, nv50_sw_new },
 802};
 803
 804static const struct nvkm_device_chip
 805nv63_chipset = {
 806	.name = "C73",
 807	.bios     = { 0x00000001, nvkm_bios_new },
 808	.bus      = { 0x00000001, nv31_bus_new },
 809	.clk      = { 0x00000001, nv40_clk_new },
 810	.devinit  = { 0x00000001, nv1a_devinit_new },
 811	.fb       = { 0x00000001, nv46_fb_new },
 812	.gpio     = { 0x00000001, nv10_gpio_new },
 813	.i2c      = { 0x00000001, nv04_i2c_new },
 814	.imem     = { 0x00000001, nv40_instmem_new },
 815	.mc       = { 0x00000001, nv44_mc_new },
 816	.mmu      = { 0x00000001, nv44_mmu_new },
 817	.pci      = { 0x00000001, nv4c_pci_new },
 818	.therm    = { 0x00000001, nv40_therm_new },
 819	.timer    = { 0x00000001, nv41_timer_new },
 820	.volt     = { 0x00000001, nv40_volt_new },
 821	.disp     = { 0x00000001, nv04_disp_new },
 822	.dma      = { 0x00000001, nv04_dma_new },
 823	.fifo     = { 0x00000001, nv40_fifo_new },
 824	.gr       = { 0x00000001, nv44_gr_new },
 825	.mpeg     = { 0x00000001, nv44_mpeg_new },
 826	.sw       = { 0x00000001, nv10_sw_new },
 827};
 828
 829static const struct nvkm_device_chip
 830nv67_chipset = {
 831	.name = "C67",
 832	.bios     = { 0x00000001, nvkm_bios_new },
 833	.bus      = { 0x00000001, nv31_bus_new },
 834	.clk      = { 0x00000001, nv40_clk_new },
 835	.devinit  = { 0x00000001, nv1a_devinit_new },
 836	.fb       = { 0x00000001, nv46_fb_new },
 837	.gpio     = { 0x00000001, nv10_gpio_new },
 838	.i2c      = { 0x00000001, nv04_i2c_new },
 839	.imem     = { 0x00000001, nv40_instmem_new },
 840	.mc       = { 0x00000001, nv44_mc_new },
 841	.mmu      = { 0x00000001, nv44_mmu_new },
 842	.pci      = { 0x00000001, nv4c_pci_new },
 843	.therm    = { 0x00000001, nv40_therm_new },
 844	.timer    = { 0x00000001, nv41_timer_new },
 845	.volt     = { 0x00000001, nv40_volt_new },
 846	.disp     = { 0x00000001, nv04_disp_new },
 847	.dma      = { 0x00000001, nv04_dma_new },
 848	.fifo     = { 0x00000001, nv40_fifo_new },
 849	.gr       = { 0x00000001, nv44_gr_new },
 850	.mpeg     = { 0x00000001, nv44_mpeg_new },
 851	.sw       = { 0x00000001, nv10_sw_new },
 852};
 853
 854static const struct nvkm_device_chip
 855nv68_chipset = {
 856	.name = "C68",
 857	.bios     = { 0x00000001, nvkm_bios_new },
 858	.bus      = { 0x00000001, nv31_bus_new },
 859	.clk      = { 0x00000001, nv40_clk_new },
 860	.devinit  = { 0x00000001, nv1a_devinit_new },
 861	.fb       = { 0x00000001, nv46_fb_new },
 862	.gpio     = { 0x00000001, nv10_gpio_new },
 863	.i2c      = { 0x00000001, nv04_i2c_new },
 864	.imem     = { 0x00000001, nv40_instmem_new },
 865	.mc       = { 0x00000001, nv44_mc_new },
 866	.mmu      = { 0x00000001, nv44_mmu_new },
 867	.pci      = { 0x00000001, nv4c_pci_new },
 868	.therm    = { 0x00000001, nv40_therm_new },
 869	.timer    = { 0x00000001, nv41_timer_new },
 870	.volt     = { 0x00000001, nv40_volt_new },
 871	.disp     = { 0x00000001, nv04_disp_new },
 872	.dma      = { 0x00000001, nv04_dma_new },
 873	.fifo     = { 0x00000001, nv40_fifo_new },
 874	.gr       = { 0x00000001, nv44_gr_new },
 875	.mpeg     = { 0x00000001, nv44_mpeg_new },
 876	.sw       = { 0x00000001, nv10_sw_new },
 877};
 878
 879static const struct nvkm_device_chip
 880nv84_chipset = {
 881	.name = "G84",
 882	.bar      = { 0x00000001, g84_bar_new },
 883	.bios     = { 0x00000001, nvkm_bios_new },
 884	.bus      = { 0x00000001, nv50_bus_new },
 885	.clk      = { 0x00000001, g84_clk_new },
 886	.devinit  = { 0x00000001, g84_devinit_new },
 887	.fb       = { 0x00000001, g84_fb_new },
 888	.fuse     = { 0x00000001, nv50_fuse_new },
 889	.gpio     = { 0x00000001, nv50_gpio_new },
 890	.i2c      = { 0x00000001, nv50_i2c_new },
 891	.imem     = { 0x00000001, nv50_instmem_new },
 892	.mc       = { 0x00000001, g84_mc_new },
 893	.mmu      = { 0x00000001, g84_mmu_new },
 894	.mxm      = { 0x00000001, nv50_mxm_new },
 895	.pci      = { 0x00000001, g84_pci_new },
 896	.therm    = { 0x00000001, g84_therm_new },
 897	.timer    = { 0x00000001, nv41_timer_new },
 898	.volt     = { 0x00000001, nv40_volt_new },
 899	.bsp      = { 0x00000001, g84_bsp_new },
 900	.cipher   = { 0x00000001, g84_cipher_new },
 901	.disp     = { 0x00000001, g84_disp_new },
 902	.dma      = { 0x00000001, nv50_dma_new },
 903	.fifo     = { 0x00000001, g84_fifo_new },
 904	.gr       = { 0x00000001, g84_gr_new },
 905	.mpeg     = { 0x00000001, g84_mpeg_new },
 906	.sw       = { 0x00000001, nv50_sw_new },
 907	.vp       = { 0x00000001, g84_vp_new },
 908};
 909
 910static const struct nvkm_device_chip
 911nv86_chipset = {
 912	.name = "G86",
 913	.bar      = { 0x00000001, g84_bar_new },
 914	.bios     = { 0x00000001, nvkm_bios_new },
 915	.bus      = { 0x00000001, nv50_bus_new },
 916	.clk      = { 0x00000001, g84_clk_new },
 917	.devinit  = { 0x00000001, g84_devinit_new },
 918	.fb       = { 0x00000001, g84_fb_new },
 919	.fuse     = { 0x00000001, nv50_fuse_new },
 920	.gpio     = { 0x00000001, nv50_gpio_new },
 921	.i2c      = { 0x00000001, nv50_i2c_new },
 922	.imem     = { 0x00000001, nv50_instmem_new },
 923	.mc       = { 0x00000001, g84_mc_new },
 924	.mmu      = { 0x00000001, g84_mmu_new },
 925	.mxm      = { 0x00000001, nv50_mxm_new },
 926	.pci      = { 0x00000001, g84_pci_new },
 927	.therm    = { 0x00000001, g84_therm_new },
 928	.timer    = { 0x00000001, nv41_timer_new },
 929	.volt     = { 0x00000001, nv40_volt_new },
 930	.bsp      = { 0x00000001, g84_bsp_new },
 931	.cipher   = { 0x00000001, g84_cipher_new },
 932	.disp     = { 0x00000001, g84_disp_new },
 933	.dma      = { 0x00000001, nv50_dma_new },
 934	.fifo     = { 0x00000001, g84_fifo_new },
 935	.gr       = { 0x00000001, g84_gr_new },
 936	.mpeg     = { 0x00000001, g84_mpeg_new },
 937	.sw       = { 0x00000001, nv50_sw_new },
 938	.vp       = { 0x00000001, g84_vp_new },
 939};
 940
 941static const struct nvkm_device_chip
 942nv92_chipset = {
 943	.name = "G92",
 944	.bar      = { 0x00000001, g84_bar_new },
 945	.bios     = { 0x00000001, nvkm_bios_new },
 946	.bus      = { 0x00000001, nv50_bus_new },
 947	.clk      = { 0x00000001, g84_clk_new },
 948	.devinit  = { 0x00000001, g84_devinit_new },
 949	.fb       = { 0x00000001, g84_fb_new },
 950	.fuse     = { 0x00000001, nv50_fuse_new },
 951	.gpio     = { 0x00000001, nv50_gpio_new },
 952	.i2c      = { 0x00000001, nv50_i2c_new },
 953	.imem     = { 0x00000001, nv50_instmem_new },
 954	.mc       = { 0x00000001, g84_mc_new },
 955	.mmu      = { 0x00000001, g84_mmu_new },
 956	.mxm      = { 0x00000001, nv50_mxm_new },
 957	.pci      = { 0x00000001, g92_pci_new },
 958	.therm    = { 0x00000001, g84_therm_new },
 959	.timer    = { 0x00000001, nv41_timer_new },
 960	.volt     = { 0x00000001, nv40_volt_new },
 961	.bsp      = { 0x00000001, g84_bsp_new },
 962	.cipher   = { 0x00000001, g84_cipher_new },
 963	.disp     = { 0x00000001, g84_disp_new },
 964	.dma      = { 0x00000001, nv50_dma_new },
 965	.fifo     = { 0x00000001, g84_fifo_new },
 966	.gr       = { 0x00000001, g84_gr_new },
 967	.mpeg     = { 0x00000001, g84_mpeg_new },
 968	.sw       = { 0x00000001, nv50_sw_new },
 969	.vp       = { 0x00000001, g84_vp_new },
 970};
 971
 972static const struct nvkm_device_chip
 973nv94_chipset = {
 974	.name = "G94",
 975	.bar      = { 0x00000001, g84_bar_new },
 976	.bios     = { 0x00000001, nvkm_bios_new },
 977	.bus      = { 0x00000001, g94_bus_new },
 978	.clk      = { 0x00000001, g84_clk_new },
 979	.devinit  = { 0x00000001, g84_devinit_new },
 980	.fb       = { 0x00000001, g84_fb_new },
 981	.fuse     = { 0x00000001, nv50_fuse_new },
 982	.gpio     = { 0x00000001, g94_gpio_new },
 983	.i2c      = { 0x00000001, g94_i2c_new },
 984	.imem     = { 0x00000001, nv50_instmem_new },
 985	.mc       = { 0x00000001, g84_mc_new },
 986	.mmu      = { 0x00000001, g84_mmu_new },
 987	.mxm      = { 0x00000001, nv50_mxm_new },
 988	.pci      = { 0x00000001, g94_pci_new },
 989	.therm    = { 0x00000001, g84_therm_new },
 990	.timer    = { 0x00000001, nv41_timer_new },
 991	.volt     = { 0x00000001, nv40_volt_new },
 992	.bsp      = { 0x00000001, g84_bsp_new },
 993	.cipher   = { 0x00000001, g84_cipher_new },
 994	.disp     = { 0x00000001, g94_disp_new },
 995	.dma      = { 0x00000001, nv50_dma_new },
 996	.fifo     = { 0x00000001, g84_fifo_new },
 997	.gr       = { 0x00000001, g84_gr_new },
 998	.mpeg     = { 0x00000001, g84_mpeg_new },
 999	.sw       = { 0x00000001, nv50_sw_new },
1000	.vp       = { 0x00000001, g84_vp_new },
1001};
1002
1003static const struct nvkm_device_chip
1004nv96_chipset = {
1005	.name = "G96",
1006	.bar      = { 0x00000001, g84_bar_new },
1007	.bios     = { 0x00000001, nvkm_bios_new },
1008	.bus      = { 0x00000001, g94_bus_new },
1009	.clk      = { 0x00000001, g84_clk_new },
1010	.devinit  = { 0x00000001, g84_devinit_new },
1011	.fb       = { 0x00000001, g84_fb_new },
1012	.fuse     = { 0x00000001, nv50_fuse_new },
1013	.gpio     = { 0x00000001, g94_gpio_new },
1014	.i2c      = { 0x00000001, g94_i2c_new },
1015	.imem     = { 0x00000001, nv50_instmem_new },
1016	.mc       = { 0x00000001, g84_mc_new },
1017	.mmu      = { 0x00000001, g84_mmu_new },
1018	.mxm      = { 0x00000001, nv50_mxm_new },
1019	.pci      = { 0x00000001, g94_pci_new },
1020	.therm    = { 0x00000001, g84_therm_new },
1021	.timer    = { 0x00000001, nv41_timer_new },
1022	.volt     = { 0x00000001, nv40_volt_new },
1023	.bsp      = { 0x00000001, g84_bsp_new },
1024	.cipher   = { 0x00000001, g84_cipher_new },
1025	.disp     = { 0x00000001, g94_disp_new },
1026	.dma      = { 0x00000001, nv50_dma_new },
1027	.fifo     = { 0x00000001, g84_fifo_new },
1028	.gr       = { 0x00000001, g84_gr_new },
1029	.mpeg     = { 0x00000001, g84_mpeg_new },
1030	.sw       = { 0x00000001, nv50_sw_new },
1031	.vp       = { 0x00000001, g84_vp_new },
1032};
1033
1034static const struct nvkm_device_chip
1035nv98_chipset = {
1036	.name = "G98",
1037	.bar      = { 0x00000001, g84_bar_new },
1038	.bios     = { 0x00000001, nvkm_bios_new },
1039	.bus      = { 0x00000001, g94_bus_new },
1040	.clk      = { 0x00000001, g84_clk_new },
1041	.devinit  = { 0x00000001, g98_devinit_new },
1042	.fb       = { 0x00000001, g84_fb_new },
1043	.fuse     = { 0x00000001, nv50_fuse_new },
1044	.gpio     = { 0x00000001, g94_gpio_new },
1045	.i2c      = { 0x00000001, g94_i2c_new },
1046	.imem     = { 0x00000001, nv50_instmem_new },
1047	.mc       = { 0x00000001, g98_mc_new },
1048	.mmu      = { 0x00000001, g84_mmu_new },
1049	.mxm      = { 0x00000001, nv50_mxm_new },
1050	.pci      = { 0x00000001, g94_pci_new },
1051	.therm    = { 0x00000001, g84_therm_new },
1052	.timer    = { 0x00000001, nv41_timer_new },
1053	.volt     = { 0x00000001, nv40_volt_new },
1054	.disp     = { 0x00000001, g94_disp_new },
1055	.dma      = { 0x00000001, nv50_dma_new },
1056	.fifo     = { 0x00000001, g98_fifo_new },
1057	.gr       = { 0x00000001, g84_gr_new },
1058	.mspdec   = { 0x00000001, g98_mspdec_new },
1059	.msppp    = { 0x00000001, g98_msppp_new },
1060	.msvld    = { 0x00000001, g98_msvld_new },
1061	.sec      = { 0x00000001, g98_sec_new },
1062	.sw       = { 0x00000001, nv50_sw_new },
1063};
1064
1065static const struct nvkm_device_chip
1066nva0_chipset = {
1067	.name = "GT200",
1068	.bar      = { 0x00000001, g84_bar_new },
1069	.bios     = { 0x00000001, nvkm_bios_new },
1070	.bus      = { 0x00000001, g94_bus_new },
1071	.clk      = { 0x00000001, g84_clk_new },
1072	.devinit  = { 0x00000001, g84_devinit_new },
1073	.fb       = { 0x00000001, g84_fb_new },
1074	.fuse     = { 0x00000001, nv50_fuse_new },
1075	.gpio     = { 0x00000001, g94_gpio_new },
1076	.i2c      = { 0x00000001, nv50_i2c_new },
1077	.imem     = { 0x00000001, nv50_instmem_new },
1078	.mc       = { 0x00000001, g84_mc_new },
1079	.mmu      = { 0x00000001, g84_mmu_new },
1080	.mxm      = { 0x00000001, nv50_mxm_new },
1081	.pci      = { 0x00000001, g94_pci_new },
1082	.therm    = { 0x00000001, g84_therm_new },
1083	.timer    = { 0x00000001, nv41_timer_new },
1084	.volt     = { 0x00000001, nv40_volt_new },
1085	.bsp      = { 0x00000001, g84_bsp_new },
1086	.cipher   = { 0x00000001, g84_cipher_new },
1087	.disp     = { 0x00000001, gt200_disp_new },
1088	.dma      = { 0x00000001, nv50_dma_new },
1089	.fifo     = { 0x00000001, g84_fifo_new },
1090	.gr       = { 0x00000001, gt200_gr_new },
1091	.mpeg     = { 0x00000001, g84_mpeg_new },
1092	.sw       = { 0x00000001, nv50_sw_new },
1093	.vp       = { 0x00000001, g84_vp_new },
1094};
1095
1096static const struct nvkm_device_chip
1097nva3_chipset = {
1098	.name = "GT215",
1099	.bar      = { 0x00000001, g84_bar_new },
1100	.bios     = { 0x00000001, nvkm_bios_new },
1101	.bus      = { 0x00000001, g94_bus_new },
1102	.clk      = { 0x00000001, gt215_clk_new },
1103	.devinit  = { 0x00000001, gt215_devinit_new },
1104	.fb       = { 0x00000001, gt215_fb_new },
1105	.fuse     = { 0x00000001, nv50_fuse_new },
1106	.gpio     = { 0x00000001, g94_gpio_new },
1107	.i2c      = { 0x00000001, g94_i2c_new },
1108	.imem     = { 0x00000001, nv50_instmem_new },
1109	.mc       = { 0x00000001, gt215_mc_new },
1110	.mmu      = { 0x00000001, g84_mmu_new },
1111	.mxm      = { 0x00000001, nv50_mxm_new },
1112	.pci      = { 0x00000001, g94_pci_new },
1113	.pmu      = { 0x00000001, gt215_pmu_new },
1114	.therm    = { 0x00000001, gt215_therm_new },
1115	.timer    = { 0x00000001, nv41_timer_new },
1116	.volt     = { 0x00000001, nv40_volt_new },
1117	.ce       = { 0x00000001, gt215_ce_new },
1118	.disp     = { 0x00000001, gt215_disp_new },
1119	.dma      = { 0x00000001, nv50_dma_new },
1120	.fifo     = { 0x00000001, g98_fifo_new },
1121	.gr       = { 0x00000001, gt215_gr_new },
1122	.mpeg     = { 0x00000001, g84_mpeg_new },
1123	.mspdec   = { 0x00000001, gt215_mspdec_new },
1124	.msppp    = { 0x00000001, gt215_msppp_new },
1125	.msvld    = { 0x00000001, gt215_msvld_new },
1126	.sw       = { 0x00000001, nv50_sw_new },
1127};
1128
1129static const struct nvkm_device_chip
1130nva5_chipset = {
1131	.name = "GT216",
1132	.bar      = { 0x00000001, g84_bar_new },
1133	.bios     = { 0x00000001, nvkm_bios_new },
1134	.bus      = { 0x00000001, g94_bus_new },
1135	.clk      = { 0x00000001, gt215_clk_new },
1136	.devinit  = { 0x00000001, gt215_devinit_new },
1137	.fb       = { 0x00000001, gt215_fb_new },
1138	.fuse     = { 0x00000001, nv50_fuse_new },
1139	.gpio     = { 0x00000001, g94_gpio_new },
1140	.i2c      = { 0x00000001, g94_i2c_new },
1141	.imem     = { 0x00000001, nv50_instmem_new },
1142	.mc       = { 0x00000001, gt215_mc_new },
1143	.mmu      = { 0x00000001, g84_mmu_new },
1144	.mxm      = { 0x00000001, nv50_mxm_new },
1145	.pci      = { 0x00000001, g94_pci_new },
1146	.pmu      = { 0x00000001, gt215_pmu_new },
1147	.therm    = { 0x00000001, gt215_therm_new },
1148	.timer    = { 0x00000001, nv41_timer_new },
1149	.volt     = { 0x00000001, nv40_volt_new },
1150	.ce       = { 0x00000001, gt215_ce_new },
1151	.disp     = { 0x00000001, gt215_disp_new },
1152	.dma      = { 0x00000001, nv50_dma_new },
1153	.fifo     = { 0x00000001, g98_fifo_new },
1154	.gr       = { 0x00000001, gt215_gr_new },
1155	.mspdec   = { 0x00000001, gt215_mspdec_new },
1156	.msppp    = { 0x00000001, gt215_msppp_new },
1157	.msvld    = { 0x00000001, gt215_msvld_new },
1158	.sw       = { 0x00000001, nv50_sw_new },
1159};
1160
1161static const struct nvkm_device_chip
1162nva8_chipset = {
1163	.name = "GT218",
1164	.bar      = { 0x00000001, g84_bar_new },
1165	.bios     = { 0x00000001, nvkm_bios_new },
1166	.bus      = { 0x00000001, g94_bus_new },
1167	.clk      = { 0x00000001, gt215_clk_new },
1168	.devinit  = { 0x00000001, gt215_devinit_new },
1169	.fb       = { 0x00000001, gt215_fb_new },
1170	.fuse     = { 0x00000001, nv50_fuse_new },
1171	.gpio     = { 0x00000001, g94_gpio_new },
1172	.i2c      = { 0x00000001, g94_i2c_new },
1173	.imem     = { 0x00000001, nv50_instmem_new },
1174	.mc       = { 0x00000001, gt215_mc_new },
1175	.mmu      = { 0x00000001, g84_mmu_new },
1176	.mxm      = { 0x00000001, nv50_mxm_new },
1177	.pci      = { 0x00000001, g94_pci_new },
1178	.pmu      = { 0x00000001, gt215_pmu_new },
1179	.therm    = { 0x00000001, gt215_therm_new },
1180	.timer    = { 0x00000001, nv41_timer_new },
1181	.volt     = { 0x00000001, nv40_volt_new },
1182	.ce       = { 0x00000001, gt215_ce_new },
1183	.disp     = { 0x00000001, gt215_disp_new },
1184	.dma      = { 0x00000001, nv50_dma_new },
1185	.fifo     = { 0x00000001, g98_fifo_new },
1186	.gr       = { 0x00000001, gt215_gr_new },
1187	.mspdec   = { 0x00000001, gt215_mspdec_new },
1188	.msppp    = { 0x00000001, gt215_msppp_new },
1189	.msvld    = { 0x00000001, gt215_msvld_new },
1190	.sw       = { 0x00000001, nv50_sw_new },
1191};
1192
1193static const struct nvkm_device_chip
1194nvaa_chipset = {
1195	.name = "MCP77/MCP78",
1196	.bar      = { 0x00000001, g84_bar_new },
1197	.bios     = { 0x00000001, nvkm_bios_new },
1198	.bus      = { 0x00000001, g94_bus_new },
1199	.clk      = { 0x00000001, mcp77_clk_new },
1200	.devinit  = { 0x00000001, g98_devinit_new },
1201	.fb       = { 0x00000001, mcp77_fb_new },
1202	.fuse     = { 0x00000001, nv50_fuse_new },
1203	.gpio     = { 0x00000001, g94_gpio_new },
1204	.i2c      = { 0x00000001, g94_i2c_new },
1205	.imem     = { 0x00000001, nv50_instmem_new },
1206	.mc       = { 0x00000001, g98_mc_new },
1207	.mmu      = { 0x00000001, mcp77_mmu_new },
1208	.mxm      = { 0x00000001, nv50_mxm_new },
1209	.pci      = { 0x00000001, g94_pci_new },
1210	.therm    = { 0x00000001, g84_therm_new },
1211	.timer    = { 0x00000001, nv41_timer_new },
1212	.volt     = { 0x00000001, nv40_volt_new },
1213	.disp     = { 0x00000001, mcp77_disp_new },
1214	.dma      = { 0x00000001, nv50_dma_new },
1215	.fifo     = { 0x00000001, g98_fifo_new },
1216	.gr       = { 0x00000001, gt200_gr_new },
1217	.mspdec   = { 0x00000001, g98_mspdec_new },
1218	.msppp    = { 0x00000001, g98_msppp_new },
1219	.msvld    = { 0x00000001, g98_msvld_new },
1220	.sec      = { 0x00000001, g98_sec_new },
1221	.sw       = { 0x00000001, nv50_sw_new },
1222};
1223
1224static const struct nvkm_device_chip
1225nvac_chipset = {
1226	.name = "MCP79/MCP7A",
1227	.bar      = { 0x00000001, g84_bar_new },
1228	.bios     = { 0x00000001, nvkm_bios_new },
1229	.bus      = { 0x00000001, g94_bus_new },
1230	.clk      = { 0x00000001, mcp77_clk_new },
1231	.devinit  = { 0x00000001, g98_devinit_new },
1232	.fb       = { 0x00000001, mcp77_fb_new },
1233	.fuse     = { 0x00000001, nv50_fuse_new },
1234	.gpio     = { 0x00000001, g94_gpio_new },
1235	.i2c      = { 0x00000001, g94_i2c_new },
1236	.imem     = { 0x00000001, nv50_instmem_new },
1237	.mc       = { 0x00000001, g98_mc_new },
1238	.mmu      = { 0x00000001, mcp77_mmu_new },
1239	.mxm      = { 0x00000001, nv50_mxm_new },
1240	.pci      = { 0x00000001, g94_pci_new },
1241	.therm    = { 0x00000001, g84_therm_new },
1242	.timer    = { 0x00000001, nv41_timer_new },
1243	.volt     = { 0x00000001, nv40_volt_new },
1244	.disp     = { 0x00000001, mcp77_disp_new },
1245	.dma      = { 0x00000001, nv50_dma_new },
1246	.fifo     = { 0x00000001, g98_fifo_new },
1247	.gr       = { 0x00000001, mcp79_gr_new },
1248	.mspdec   = { 0x00000001, g98_mspdec_new },
1249	.msppp    = { 0x00000001, g98_msppp_new },
1250	.msvld    = { 0x00000001, g98_msvld_new },
1251	.sec      = { 0x00000001, g98_sec_new },
1252	.sw       = { 0x00000001, nv50_sw_new },
1253};
1254
1255static const struct nvkm_device_chip
1256nvaf_chipset = {
1257	.name = "MCP89",
1258	.bar      = { 0x00000001, g84_bar_new },
1259	.bios     = { 0x00000001, nvkm_bios_new },
1260	.bus      = { 0x00000001, g94_bus_new },
1261	.clk      = { 0x00000001, gt215_clk_new },
1262	.devinit  = { 0x00000001, mcp89_devinit_new },
1263	.fb       = { 0x00000001, mcp89_fb_new },
1264	.fuse     = { 0x00000001, nv50_fuse_new },
1265	.gpio     = { 0x00000001, g94_gpio_new },
1266	.i2c      = { 0x00000001, g94_i2c_new },
1267	.imem     = { 0x00000001, nv50_instmem_new },
1268	.mc       = { 0x00000001, gt215_mc_new },
1269	.mmu      = { 0x00000001, mcp77_mmu_new },
1270	.mxm      = { 0x00000001, nv50_mxm_new },
1271	.pci      = { 0x00000001, g94_pci_new },
1272	.pmu      = { 0x00000001, gt215_pmu_new },
1273	.therm    = { 0x00000001, gt215_therm_new },
1274	.timer    = { 0x00000001, nv41_timer_new },
1275	.volt     = { 0x00000001, nv40_volt_new },
1276	.ce       = { 0x00000001, gt215_ce_new },
1277	.disp     = { 0x00000001, mcp89_disp_new },
1278	.dma      = { 0x00000001, nv50_dma_new },
1279	.fifo     = { 0x00000001, g98_fifo_new },
1280	.gr       = { 0x00000001, mcp89_gr_new },
1281	.mspdec   = { 0x00000001, gt215_mspdec_new },
1282	.msppp    = { 0x00000001, gt215_msppp_new },
1283	.msvld    = { 0x00000001, mcp89_msvld_new },
1284	.sw       = { 0x00000001, nv50_sw_new },
1285};
1286
1287static const struct nvkm_device_chip
1288nvc0_chipset = {
1289	.name = "GF100",
1290	.bar      = { 0x00000001, gf100_bar_new },
1291	.bios     = { 0x00000001, nvkm_bios_new },
1292	.bus      = { 0x00000001, gf100_bus_new },
1293	.clk      = { 0x00000001, gf100_clk_new },
1294	.devinit  = { 0x00000001, gf100_devinit_new },
1295	.fb       = { 0x00000001, gf100_fb_new },
1296	.fuse     = { 0x00000001, gf100_fuse_new },
1297	.gpio     = { 0x00000001, g94_gpio_new },
1298	.i2c      = { 0x00000001, g94_i2c_new },
1299	.iccsense = { 0x00000001, gf100_iccsense_new },
1300	.imem     = { 0x00000001, nv50_instmem_new },
1301	.ltc      = { 0x00000001, gf100_ltc_new },
1302	.mc       = { 0x00000001, gf100_mc_new },
1303	.mmu      = { 0x00000001, gf100_mmu_new },
1304	.mxm      = { 0x00000001, nv50_mxm_new },
1305	.pci      = { 0x00000001, gf100_pci_new },
1306	.pmu      = { 0x00000001, gf100_pmu_new },
1307	.privring = { 0x00000001, gf100_privring_new },
1308	.therm    = { 0x00000001, gt215_therm_new },
1309	.timer    = { 0x00000001, nv41_timer_new },
1310	.volt     = { 0x00000001, gf100_volt_new },
1311	.ce       = { 0x00000003, gf100_ce_new },
1312	.disp     = { 0x00000001, gt215_disp_new },
1313	.dma      = { 0x00000001, gf100_dma_new },
1314	.fifo     = { 0x00000001, gf100_fifo_new },
1315	.gr       = { 0x00000001, gf100_gr_new },
1316	.mspdec   = { 0x00000001, gf100_mspdec_new },
1317	.msppp    = { 0x00000001, gf100_msppp_new },
1318	.msvld    = { 0x00000001, gf100_msvld_new },
1319	.sw       = { 0x00000001, gf100_sw_new },
1320};
1321
1322static const struct nvkm_device_chip
1323nvc1_chipset = {
1324	.name = "GF108",
1325	.bar      = { 0x00000001, gf100_bar_new },
1326	.bios     = { 0x00000001, nvkm_bios_new },
1327	.bus      = { 0x00000001, gf100_bus_new },
1328	.clk      = { 0x00000001, gf100_clk_new },
1329	.devinit  = { 0x00000001, gf100_devinit_new },
1330	.fb       = { 0x00000001, gf108_fb_new },
1331	.fuse     = { 0x00000001, gf100_fuse_new },
1332	.gpio     = { 0x00000001, g94_gpio_new },
1333	.i2c      = { 0x00000001, g94_i2c_new },
1334	.iccsense = { 0x00000001, gf100_iccsense_new },
1335	.imem     = { 0x00000001, nv50_instmem_new },
1336	.ltc      = { 0x00000001, gf100_ltc_new },
1337	.mc       = { 0x00000001, gf100_mc_new },
1338	.mmu      = { 0x00000001, gf100_mmu_new },
1339	.mxm      = { 0x00000001, nv50_mxm_new },
1340	.pci      = { 0x00000001, gf106_pci_new },
1341	.pmu      = { 0x00000001, gf100_pmu_new },
1342	.privring = { 0x00000001, gf100_privring_new },
1343	.therm    = { 0x00000001, gt215_therm_new },
1344	.timer    = { 0x00000001, nv41_timer_new },
1345	.volt     = { 0x00000001, gf100_volt_new },
1346	.ce       = { 0x00000001, gf100_ce_new },
1347	.disp     = { 0x00000001, gt215_disp_new },
1348	.dma      = { 0x00000001, gf100_dma_new },
1349	.fifo     = { 0x00000001, gf100_fifo_new },
1350	.gr       = { 0x00000001, gf108_gr_new },
1351	.mspdec   = { 0x00000001, gf100_mspdec_new },
1352	.msppp    = { 0x00000001, gf100_msppp_new },
1353	.msvld    = { 0x00000001, gf100_msvld_new },
1354	.sw       = { 0x00000001, gf100_sw_new },
1355};
1356
1357static const struct nvkm_device_chip
1358nvc3_chipset = {
1359	.name = "GF106",
1360	.bar      = { 0x00000001, gf100_bar_new },
1361	.bios     = { 0x00000001, nvkm_bios_new },
1362	.bus      = { 0x00000001, gf100_bus_new },
1363	.clk      = { 0x00000001, gf100_clk_new },
1364	.devinit  = { 0x00000001, gf100_devinit_new },
1365	.fb       = { 0x00000001, gf100_fb_new },
1366	.fuse     = { 0x00000001, gf100_fuse_new },
1367	.gpio     = { 0x00000001, g94_gpio_new },
1368	.i2c      = { 0x00000001, g94_i2c_new },
1369	.iccsense = { 0x00000001, gf100_iccsense_new },
1370	.imem     = { 0x00000001, nv50_instmem_new },
1371	.ltc      = { 0x00000001, gf100_ltc_new },
1372	.mc       = { 0x00000001, gf100_mc_new },
1373	.mmu      = { 0x00000001, gf100_mmu_new },
1374	.mxm      = { 0x00000001, nv50_mxm_new },
1375	.pci      = { 0x00000001, gf106_pci_new },
1376	.pmu      = { 0x00000001, gf100_pmu_new },
1377	.privring = { 0x00000001, gf100_privring_new },
1378	.therm    = { 0x00000001, gt215_therm_new },
1379	.timer    = { 0x00000001, nv41_timer_new },
1380	.volt     = { 0x00000001, gf100_volt_new },
1381	.ce       = { 0x00000001, gf100_ce_new },
1382	.disp     = { 0x00000001, gt215_disp_new },
1383	.dma      = { 0x00000001, gf100_dma_new },
1384	.fifo     = { 0x00000001, gf100_fifo_new },
1385	.gr       = { 0x00000001, gf104_gr_new },
1386	.mspdec   = { 0x00000001, gf100_mspdec_new },
1387	.msppp    = { 0x00000001, gf100_msppp_new },
1388	.msvld    = { 0x00000001, gf100_msvld_new },
1389	.sw       = { 0x00000001, gf100_sw_new },
1390};
1391
1392static const struct nvkm_device_chip
1393nvc4_chipset = {
1394	.name = "GF104",
1395	.bar      = { 0x00000001, gf100_bar_new },
1396	.bios     = { 0x00000001, nvkm_bios_new },
1397	.bus      = { 0x00000001, gf100_bus_new },
1398	.clk      = { 0x00000001, gf100_clk_new },
1399	.devinit  = { 0x00000001, gf100_devinit_new },
1400	.fb       = { 0x00000001, gf100_fb_new },
1401	.fuse     = { 0x00000001, gf100_fuse_new },
1402	.gpio     = { 0x00000001, g94_gpio_new },
1403	.i2c      = { 0x00000001, g94_i2c_new },
1404	.iccsense = { 0x00000001, gf100_iccsense_new },
1405	.imem     = { 0x00000001, nv50_instmem_new },
1406	.ltc      = { 0x00000001, gf100_ltc_new },
1407	.mc       = { 0x00000001, gf100_mc_new },
1408	.mmu      = { 0x00000001, gf100_mmu_new },
1409	.mxm      = { 0x00000001, nv50_mxm_new },
1410	.pci      = { 0x00000001, gf100_pci_new },
1411	.pmu      = { 0x00000001, gf100_pmu_new },
1412	.privring = { 0x00000001, gf100_privring_new },
1413	.therm    = { 0x00000001, gt215_therm_new },
1414	.timer    = { 0x00000001, nv41_timer_new },
1415	.volt     = { 0x00000001, gf100_volt_new },
1416	.ce       = { 0x00000003, gf100_ce_new },
1417	.disp     = { 0x00000001, gt215_disp_new },
1418	.dma      = { 0x00000001, gf100_dma_new },
1419	.fifo     = { 0x00000001, gf100_fifo_new },
1420	.gr       = { 0x00000001, gf104_gr_new },
1421	.mspdec   = { 0x00000001, gf100_mspdec_new },
1422	.msppp    = { 0x00000001, gf100_msppp_new },
1423	.msvld    = { 0x00000001, gf100_msvld_new },
1424	.sw       = { 0x00000001, gf100_sw_new },
1425};
1426
1427static const struct nvkm_device_chip
1428nvc8_chipset = {
1429	.name = "GF110",
1430	.bar      = { 0x00000001, gf100_bar_new },
1431	.bios     = { 0x00000001, nvkm_bios_new },
1432	.bus      = { 0x00000001, gf100_bus_new },
1433	.clk      = { 0x00000001, gf100_clk_new },
1434	.devinit  = { 0x00000001, gf100_devinit_new },
1435	.fb       = { 0x00000001, gf100_fb_new },
1436	.fuse     = { 0x00000001, gf100_fuse_new },
1437	.gpio     = { 0x00000001, g94_gpio_new },
1438	.i2c      = { 0x00000001, g94_i2c_new },
1439	.iccsense = { 0x00000001, gf100_iccsense_new },
1440	.imem     = { 0x00000001, nv50_instmem_new },
1441	.ltc      = { 0x00000001, gf100_ltc_new },
1442	.mc       = { 0x00000001, gf100_mc_new },
1443	.mmu      = { 0x00000001, gf100_mmu_new },
1444	.mxm      = { 0x00000001, nv50_mxm_new },
1445	.pci      = { 0x00000001, gf100_pci_new },
1446	.pmu      = { 0x00000001, gf100_pmu_new },
1447	.privring = { 0x00000001, gf100_privring_new },
1448	.therm    = { 0x00000001, gt215_therm_new },
1449	.timer    = { 0x00000001, nv41_timer_new },
1450	.volt     = { 0x00000001, gf100_volt_new },
1451	.ce       = { 0x00000003, gf100_ce_new },
1452	.disp     = { 0x00000001, gt215_disp_new },
1453	.dma      = { 0x00000001, gf100_dma_new },
1454	.fifo     = { 0x00000001, gf100_fifo_new },
1455	.gr       = { 0x00000001, gf110_gr_new },
1456	.mspdec   = { 0x00000001, gf100_mspdec_new },
1457	.msppp    = { 0x00000001, gf100_msppp_new },
1458	.msvld    = { 0x00000001, gf100_msvld_new },
1459	.sw       = { 0x00000001, gf100_sw_new },
1460};
1461
1462static const struct nvkm_device_chip
1463nvce_chipset = {
1464	.name = "GF114",
1465	.bar      = { 0x00000001, gf100_bar_new },
1466	.bios     = { 0x00000001, nvkm_bios_new },
1467	.bus      = { 0x00000001, gf100_bus_new },
1468	.clk      = { 0x00000001, gf100_clk_new },
1469	.devinit  = { 0x00000001, gf100_devinit_new },
1470	.fb       = { 0x00000001, gf100_fb_new },
1471	.fuse     = { 0x00000001, gf100_fuse_new },
1472	.gpio     = { 0x00000001, g94_gpio_new },
1473	.i2c      = { 0x00000001, g94_i2c_new },
1474	.iccsense = { 0x00000001, gf100_iccsense_new },
1475	.imem     = { 0x00000001, nv50_instmem_new },
1476	.ltc      = { 0x00000001, gf100_ltc_new },
1477	.mc       = { 0x00000001, gf100_mc_new },
1478	.mmu      = { 0x00000001, gf100_mmu_new },
1479	.mxm      = { 0x00000001, nv50_mxm_new },
1480	.pci      = { 0x00000001, gf100_pci_new },
1481	.pmu      = { 0x00000001, gf100_pmu_new },
1482	.privring = { 0x00000001, gf100_privring_new },
1483	.therm    = { 0x00000001, gt215_therm_new },
1484	.timer    = { 0x00000001, nv41_timer_new },
1485	.volt     = { 0x00000001, gf100_volt_new },
1486	.ce       = { 0x00000003, gf100_ce_new },
1487	.disp     = { 0x00000001, gt215_disp_new },
1488	.dma      = { 0x00000001, gf100_dma_new },
1489	.fifo     = { 0x00000001, gf100_fifo_new },
1490	.gr       = { 0x00000001, gf104_gr_new },
1491	.mspdec   = { 0x00000001, gf100_mspdec_new },
1492	.msppp    = { 0x00000001, gf100_msppp_new },
1493	.msvld    = { 0x00000001, gf100_msvld_new },
1494	.sw       = { 0x00000001, gf100_sw_new },
1495};
1496
1497static const struct nvkm_device_chip
1498nvcf_chipset = {
1499	.name = "GF116",
1500	.bar      = { 0x00000001, gf100_bar_new },
1501	.bios     = { 0x00000001, nvkm_bios_new },
1502	.bus      = { 0x00000001, gf100_bus_new },
1503	.clk      = { 0x00000001, gf100_clk_new },
1504	.devinit  = { 0x00000001, gf100_devinit_new },
1505	.fb       = { 0x00000001, gf100_fb_new },
1506	.fuse     = { 0x00000001, gf100_fuse_new },
1507	.gpio     = { 0x00000001, g94_gpio_new },
1508	.i2c      = { 0x00000001, g94_i2c_new },
1509	.iccsense = { 0x00000001, gf100_iccsense_new },
1510	.imem     = { 0x00000001, nv50_instmem_new },
1511	.ltc      = { 0x00000001, gf100_ltc_new },
1512	.mc       = { 0x00000001, gf100_mc_new },
1513	.mmu      = { 0x00000001, gf100_mmu_new },
1514	.mxm      = { 0x00000001, nv50_mxm_new },
1515	.pci      = { 0x00000001, gf106_pci_new },
1516	.pmu      = { 0x00000001, gf100_pmu_new },
1517	.privring = { 0x00000001, gf100_privring_new },
1518	.therm    = { 0x00000001, gt215_therm_new },
1519	.timer    = { 0x00000001, nv41_timer_new },
1520	.volt     = { 0x00000001, gf100_volt_new },
1521	.ce       = { 0x00000001, gf100_ce_new },
1522	.disp     = { 0x00000001, gt215_disp_new },
1523	.dma      = { 0x00000001, gf100_dma_new },
1524	.fifo     = { 0x00000001, gf100_fifo_new },
1525	.gr       = { 0x00000001, gf104_gr_new },
1526	.mspdec   = { 0x00000001, gf100_mspdec_new },
1527	.msppp    = { 0x00000001, gf100_msppp_new },
1528	.msvld    = { 0x00000001, gf100_msvld_new },
1529	.sw       = { 0x00000001, gf100_sw_new },
1530};
1531
1532static const struct nvkm_device_chip
1533nvd7_chipset = {
1534	.name = "GF117",
1535	.bar      = { 0x00000001, gf100_bar_new },
1536	.bios     = { 0x00000001, nvkm_bios_new },
1537	.bus      = { 0x00000001, gf100_bus_new },
1538	.clk      = { 0x00000001, gf100_clk_new },
1539	.devinit  = { 0x00000001, gf100_devinit_new },
1540	.fb       = { 0x00000001, gf100_fb_new },
1541	.fuse     = { 0x00000001, gf100_fuse_new },
1542	.gpio     = { 0x00000001, gf119_gpio_new },
1543	.i2c      = { 0x00000001, gf117_i2c_new },
1544	.iccsense = { 0x00000001, gf100_iccsense_new },
1545	.imem     = { 0x00000001, nv50_instmem_new },
1546	.ltc      = { 0x00000001, gf100_ltc_new },
1547	.mc       = { 0x00000001, gf100_mc_new },
1548	.mmu      = { 0x00000001, gf100_mmu_new },
1549	.mxm      = { 0x00000001, nv50_mxm_new },
1550	.pci      = { 0x00000001, gf106_pci_new },
1551	.privring = { 0x00000001, gf117_privring_new },
1552	.therm    = { 0x00000001, gf119_therm_new },
1553	.timer    = { 0x00000001, nv41_timer_new },
1554	.volt     = { 0x00000001, gf117_volt_new },
1555	.ce       = { 0x00000001, gf100_ce_new },
1556	.disp     = { 0x00000001, gf119_disp_new },
1557	.dma      = { 0x00000001, gf119_dma_new },
1558	.fifo     = { 0x00000001, gf100_fifo_new },
1559	.gr       = { 0x00000001, gf117_gr_new },
1560	.mspdec   = { 0x00000001, gf100_mspdec_new },
1561	.msppp    = { 0x00000001, gf100_msppp_new },
1562	.msvld    = { 0x00000001, gf100_msvld_new },
1563	.sw       = { 0x00000001, gf100_sw_new },
1564};
1565
1566static const struct nvkm_device_chip
1567nvd9_chipset = {
1568	.name = "GF119",
1569	.bar      = { 0x00000001, gf100_bar_new },
1570	.bios     = { 0x00000001, nvkm_bios_new },
1571	.bus      = { 0x00000001, gf100_bus_new },
1572	.clk      = { 0x00000001, gf100_clk_new },
1573	.devinit  = { 0x00000001, gf100_devinit_new },
1574	.fb       = { 0x00000001, gf100_fb_new },
1575	.fuse     = { 0x00000001, gf100_fuse_new },
1576	.gpio     = { 0x00000001, gf119_gpio_new },
1577	.i2c      = { 0x00000001, gf119_i2c_new },
1578	.iccsense = { 0x00000001, gf100_iccsense_new },
1579	.imem     = { 0x00000001, nv50_instmem_new },
1580	.ltc      = { 0x00000001, gf100_ltc_new },
1581	.mc       = { 0x00000001, gf100_mc_new },
1582	.mmu      = { 0x00000001, gf100_mmu_new },
1583	.mxm      = { 0x00000001, nv50_mxm_new },
1584	.pci      = { 0x00000001, gf106_pci_new },
1585	.pmu      = { 0x00000001, gf119_pmu_new },
1586	.privring = { 0x00000001, gf117_privring_new },
1587	.therm    = { 0x00000001, gf119_therm_new },
1588	.timer    = { 0x00000001, nv41_timer_new },
1589	.volt     = { 0x00000001, gf100_volt_new },
1590	.ce       = { 0x00000001, gf100_ce_new },
1591	.disp     = { 0x00000001, gf119_disp_new },
1592	.dma      = { 0x00000001, gf119_dma_new },
1593	.fifo     = { 0x00000001, gf100_fifo_new },
1594	.gr       = { 0x00000001, gf119_gr_new },
1595	.mspdec   = { 0x00000001, gf100_mspdec_new },
1596	.msppp    = { 0x00000001, gf100_msppp_new },
1597	.msvld    = { 0x00000001, gf100_msvld_new },
1598	.sw       = { 0x00000001, gf100_sw_new },
1599};
1600
1601static const struct nvkm_device_chip
1602nve4_chipset = {
1603	.name = "GK104",
1604	.bar      = { 0x00000001, gf100_bar_new },
1605	.bios     = { 0x00000001, nvkm_bios_new },
1606	.bus      = { 0x00000001, gf100_bus_new },
1607	.clk      = { 0x00000001, gk104_clk_new },
1608	.devinit  = { 0x00000001, gf100_devinit_new },
1609	.fb       = { 0x00000001, gk104_fb_new },
1610	.fuse     = { 0x00000001, gf100_fuse_new },
1611	.gpio     = { 0x00000001, gk104_gpio_new },
1612	.i2c      = { 0x00000001, gk104_i2c_new },
1613	.iccsense = { 0x00000001, gf100_iccsense_new },
1614	.imem     = { 0x00000001, nv50_instmem_new },
1615	.ltc      = { 0x00000001, gk104_ltc_new },
1616	.mc       = { 0x00000001, gk104_mc_new },
1617	.mmu      = { 0x00000001, gk104_mmu_new },
1618	.mxm      = { 0x00000001, nv50_mxm_new },
1619	.pci      = { 0x00000001, gk104_pci_new },
1620	.pmu      = { 0x00000001, gk104_pmu_new },
1621	.privring = { 0x00000001, gk104_privring_new },
1622	.therm    = { 0x00000001, gk104_therm_new },
1623	.timer    = { 0x00000001, nv41_timer_new },
1624	.top      = { 0x00000001, gk104_top_new },
1625	.volt     = { 0x00000001, gk104_volt_new },
1626	.ce       = { 0x00000007, gk104_ce_new },
1627	.disp     = { 0x00000001, gk104_disp_new },
1628	.dma      = { 0x00000001, gf119_dma_new },
1629	.fifo     = { 0x00000001, gk104_fifo_new },
1630	.gr       = { 0x00000001, gk104_gr_new },
1631	.mspdec   = { 0x00000001, gk104_mspdec_new },
1632	.msppp    = { 0x00000001, gf100_msppp_new },
1633	.msvld    = { 0x00000001, gk104_msvld_new },
1634	.sw       = { 0x00000001, gf100_sw_new },
1635};
1636
1637static const struct nvkm_device_chip
1638nve6_chipset = {
1639	.name = "GK106",
1640	.bar      = { 0x00000001, gf100_bar_new },
1641	.bios     = { 0x00000001, nvkm_bios_new },
1642	.bus      = { 0x00000001, gf100_bus_new },
1643	.clk      = { 0x00000001, gk104_clk_new },
1644	.devinit  = { 0x00000001, gf100_devinit_new },
1645	.fb       = { 0x00000001, gk104_fb_new },
1646	.fuse     = { 0x00000001, gf100_fuse_new },
1647	.gpio     = { 0x00000001, gk104_gpio_new },
1648	.i2c      = { 0x00000001, gk104_i2c_new },
1649	.iccsense = { 0x00000001, gf100_iccsense_new },
1650	.imem     = { 0x00000001, nv50_instmem_new },
1651	.ltc      = { 0x00000001, gk104_ltc_new },
1652	.mc       = { 0x00000001, gk104_mc_new },
1653	.mmu      = { 0x00000001, gk104_mmu_new },
1654	.mxm      = { 0x00000001, nv50_mxm_new },
1655	.pci      = { 0x00000001, gk104_pci_new },
1656	.pmu      = { 0x00000001, gk104_pmu_new },
1657	.privring = { 0x00000001, gk104_privring_new },
1658	.therm    = { 0x00000001, gk104_therm_new },
1659	.timer    = { 0x00000001, nv41_timer_new },
1660	.top      = { 0x00000001, gk104_top_new },
1661	.volt     = { 0x00000001, gk104_volt_new },
1662	.ce       = { 0x00000007, gk104_ce_new },
1663	.disp     = { 0x00000001, gk104_disp_new },
1664	.dma      = { 0x00000001, gf119_dma_new },
1665	.fifo     = { 0x00000001, gk104_fifo_new },
1666	.gr       = { 0x00000001, gk104_gr_new },
1667	.mspdec   = { 0x00000001, gk104_mspdec_new },
1668	.msppp    = { 0x00000001, gf100_msppp_new },
1669	.msvld    = { 0x00000001, gk104_msvld_new },
1670	.sw       = { 0x00000001, gf100_sw_new },
1671};
1672
1673static const struct nvkm_device_chip
1674nve7_chipset = {
1675	.name = "GK107",
1676	.bar      = { 0x00000001, gf100_bar_new },
1677	.bios     = { 0x00000001, nvkm_bios_new },
1678	.bus      = { 0x00000001, gf100_bus_new },
1679	.clk      = { 0x00000001, gk104_clk_new },
1680	.devinit  = { 0x00000001, gf100_devinit_new },
1681	.fb       = { 0x00000001, gk104_fb_new },
1682	.fuse     = { 0x00000001, gf100_fuse_new },
1683	.gpio     = { 0x00000001, gk104_gpio_new },
1684	.i2c      = { 0x00000001, gk104_i2c_new },
1685	.iccsense = { 0x00000001, gf100_iccsense_new },
1686	.imem     = { 0x00000001, nv50_instmem_new },
1687	.ltc      = { 0x00000001, gk104_ltc_new },
1688	.mc       = { 0x00000001, gk104_mc_new },
1689	.mmu      = { 0x00000001, gk104_mmu_new },
1690	.mxm      = { 0x00000001, nv50_mxm_new },
1691	.pci      = { 0x00000001, gk104_pci_new },
1692	.pmu      = { 0x00000001, gk104_pmu_new },
1693	.privring = { 0x00000001, gk104_privring_new },
1694	.therm    = { 0x00000001, gk104_therm_new },
1695	.timer    = { 0x00000001, nv41_timer_new },
1696	.top      = { 0x00000001, gk104_top_new },
1697	.volt     = { 0x00000001, gk104_volt_new },
1698	.ce       = { 0x00000007, gk104_ce_new },
1699	.disp     = { 0x00000001, gk104_disp_new },
1700	.dma      = { 0x00000001, gf119_dma_new },
1701	.fifo     = { 0x00000001, gk104_fifo_new },
1702	.gr       = { 0x00000001, gk104_gr_new },
1703	.mspdec   = { 0x00000001, gk104_mspdec_new },
1704	.msppp    = { 0x00000001, gf100_msppp_new },
1705	.msvld    = { 0x00000001, gk104_msvld_new },
1706	.sw       = { 0x00000001, gf100_sw_new },
1707};
1708
1709static const struct nvkm_device_chip
1710nvea_chipset = {
1711	.name = "GK20A",
1712	.bar      = { 0x00000001, gk20a_bar_new },
1713	.bus      = { 0x00000001, gf100_bus_new },
1714	.clk      = { 0x00000001, gk20a_clk_new },
1715	.fb       = { 0x00000001, gk20a_fb_new },
1716	.fuse     = { 0x00000001, gf100_fuse_new },
1717	.imem     = { 0x00000001, gk20a_instmem_new },
1718	.ltc      = { 0x00000001, gk104_ltc_new },
1719	.mc       = { 0x00000001, gk20a_mc_new },
1720	.mmu      = { 0x00000001, gk20a_mmu_new },
1721	.pmu      = { 0x00000001, gk20a_pmu_new },
1722	.privring = { 0x00000001, gk20a_privring_new },
1723	.timer    = { 0x00000001, gk20a_timer_new },
1724	.top      = { 0x00000001, gk104_top_new },
1725	.volt     = { 0x00000001, gk20a_volt_new },
1726	.ce       = { 0x00000004, gk104_ce_new },
1727	.dma      = { 0x00000001, gf119_dma_new },
1728	.fifo     = { 0x00000001, gk20a_fifo_new },
1729	.gr       = { 0x00000001, gk20a_gr_new },
1730	.sw       = { 0x00000001, gf100_sw_new },
1731};
1732
1733static const struct nvkm_device_chip
1734nvf0_chipset = {
1735	.name = "GK110",
1736	.bar      = { 0x00000001, gf100_bar_new },
1737	.bios     = { 0x00000001, nvkm_bios_new },
1738	.bus      = { 0x00000001, gf100_bus_new },
1739	.clk      = { 0x00000001, gk104_clk_new },
1740	.devinit  = { 0x00000001, gf100_devinit_new },
1741	.fb       = { 0x00000001, gk110_fb_new },
1742	.fuse     = { 0x00000001, gf100_fuse_new },
1743	.gpio     = { 0x00000001, gk104_gpio_new },
1744	.i2c      = { 0x00000001, gk110_i2c_new },
1745	.iccsense = { 0x00000001, gf100_iccsense_new },
1746	.imem     = { 0x00000001, nv50_instmem_new },
1747	.ltc      = { 0x00000001, gk104_ltc_new },
1748	.mc       = { 0x00000001, gk104_mc_new },
1749	.mmu      = { 0x00000001, gk104_mmu_new },
1750	.mxm      = { 0x00000001, nv50_mxm_new },
1751	.pci      = { 0x00000001, gk104_pci_new },
1752	.pmu      = { 0x00000001, gk110_pmu_new },
1753	.privring = { 0x00000001, gk104_privring_new },
1754	.therm    = { 0x00000001, gk104_therm_new },
1755	.timer    = { 0x00000001, nv41_timer_new },
1756	.top      = { 0x00000001, gk104_top_new },
1757	.volt     = { 0x00000001, gk104_volt_new },
1758	.ce       = { 0x00000007, gk104_ce_new },
1759	.disp     = { 0x00000001, gk110_disp_new },
1760	.dma      = { 0x00000001, gf119_dma_new },
1761	.fifo     = { 0x00000001, gk110_fifo_new },
1762	.gr       = { 0x00000001, gk110_gr_new },
1763	.mspdec   = { 0x00000001, gk104_mspdec_new },
1764	.msppp    = { 0x00000001, gf100_msppp_new },
1765	.msvld    = { 0x00000001, gk104_msvld_new },
1766	.sw       = { 0x00000001, gf100_sw_new },
1767};
1768
1769static const struct nvkm_device_chip
1770nvf1_chipset = {
1771	.name = "GK110B",
1772	.bar      = { 0x00000001, gf100_bar_new },
1773	.bios     = { 0x00000001, nvkm_bios_new },
1774	.bus      = { 0x00000001, gf100_bus_new },
1775	.clk      = { 0x00000001, gk104_clk_new },
1776	.devinit  = { 0x00000001, gf100_devinit_new },
1777	.fb       = { 0x00000001, gk110_fb_new },
1778	.fuse     = { 0x00000001, gf100_fuse_new },
1779	.gpio     = { 0x00000001, gk104_gpio_new },
1780	.i2c      = { 0x00000001, gk110_i2c_new },
1781	.iccsense = { 0x00000001, gf100_iccsense_new },
1782	.imem     = { 0x00000001, nv50_instmem_new },
1783	.ltc      = { 0x00000001, gk104_ltc_new },
1784	.mc       = { 0x00000001, gk104_mc_new },
1785	.mmu      = { 0x00000001, gk104_mmu_new },
1786	.mxm      = { 0x00000001, nv50_mxm_new },
1787	.pci      = { 0x00000001, gk104_pci_new },
1788	.pmu      = { 0x00000001, gk110_pmu_new },
1789	.privring = { 0x00000001, gk104_privring_new },
1790	.therm    = { 0x00000001, gk104_therm_new },
1791	.timer    = { 0x00000001, nv41_timer_new },
1792	.top      = { 0x00000001, gk104_top_new },
1793	.volt     = { 0x00000001, gk104_volt_new },
1794	.ce       = { 0x00000007, gk104_ce_new },
1795	.disp     = { 0x00000001, gk110_disp_new },
1796	.dma      = { 0x00000001, gf119_dma_new },
1797	.fifo     = { 0x00000001, gk110_fifo_new },
1798	.gr       = { 0x00000001, gk110b_gr_new },
1799	.mspdec   = { 0x00000001, gk104_mspdec_new },
1800	.msppp    = { 0x00000001, gf100_msppp_new },
1801	.msvld    = { 0x00000001, gk104_msvld_new },
1802	.sw       = { 0x00000001, gf100_sw_new },
1803};
1804
1805static const struct nvkm_device_chip
1806nv106_chipset = {
1807	.name = "GK208B",
1808	.bar      = { 0x00000001, gf100_bar_new },
1809	.bios     = { 0x00000001, nvkm_bios_new },
1810	.bus      = { 0x00000001, gf100_bus_new },
1811	.clk      = { 0x00000001, gk104_clk_new },
1812	.devinit  = { 0x00000001, gf100_devinit_new },
1813	.fb       = { 0x00000001, gk110_fb_new },
1814	.fuse     = { 0x00000001, gf100_fuse_new },
1815	.gpio     = { 0x00000001, gk104_gpio_new },
1816	.i2c      = { 0x00000001, gk110_i2c_new },
1817	.iccsense = { 0x00000001, gf100_iccsense_new },
1818	.imem     = { 0x00000001, nv50_instmem_new },
1819	.ltc      = { 0x00000001, gk104_ltc_new },
1820	.mc       = { 0x00000001, gk20a_mc_new },
1821	.mmu      = { 0x00000001, gk104_mmu_new },
1822	.mxm      = { 0x00000001, nv50_mxm_new },
1823	.pci      = { 0x00000001, gk104_pci_new },
1824	.pmu      = { 0x00000001, gk208_pmu_new },
1825	.privring = { 0x00000001, gk104_privring_new },
1826	.therm    = { 0x00000001, gk104_therm_new },
1827	.timer    = { 0x00000001, nv41_timer_new },
1828	.top      = { 0x00000001, gk104_top_new },
1829	.volt     = { 0x00000001, gk104_volt_new },
1830	.ce       = { 0x00000007, gk104_ce_new },
1831	.disp     = { 0x00000001, gk110_disp_new },
1832	.dma      = { 0x00000001, gf119_dma_new },
1833	.fifo     = { 0x00000001, gk208_fifo_new },
1834	.gr       = { 0x00000001, gk208_gr_new },
1835	.mspdec   = { 0x00000001, gk104_mspdec_new },
1836	.msppp    = { 0x00000001, gf100_msppp_new },
1837	.msvld    = { 0x00000001, gk104_msvld_new },
1838	.sw       = { 0x00000001, gf100_sw_new },
1839};
1840
1841static const struct nvkm_device_chip
1842nv108_chipset = {
1843	.name = "GK208",
1844	.bar      = { 0x00000001, gf100_bar_new },
1845	.bios     = { 0x00000001, nvkm_bios_new },
1846	.bus      = { 0x00000001, gf100_bus_new },
1847	.clk      = { 0x00000001, gk104_clk_new },
1848	.devinit  = { 0x00000001, gf100_devinit_new },
1849	.fb       = { 0x00000001, gk110_fb_new },
1850	.fuse     = { 0x00000001, gf100_fuse_new },
1851	.gpio     = { 0x00000001, gk104_gpio_new },
1852	.i2c      = { 0x00000001, gk110_i2c_new },
1853	.iccsense = { 0x00000001, gf100_iccsense_new },
1854	.imem     = { 0x00000001, nv50_instmem_new },
1855	.ltc      = { 0x00000001, gk104_ltc_new },
1856	.mc       = { 0x00000001, gk20a_mc_new },
1857	.mmu      = { 0x00000001, gk104_mmu_new },
1858	.mxm      = { 0x00000001, nv50_mxm_new },
1859	.pci      = { 0x00000001, gk104_pci_new },
1860	.pmu      = { 0x00000001, gk208_pmu_new },
1861	.privring = { 0x00000001, gk104_privring_new },
1862	.therm    = { 0x00000001, gk104_therm_new },
1863	.timer    = { 0x00000001, nv41_timer_new },
1864	.top      = { 0x00000001, gk104_top_new },
1865	.volt     = { 0x00000001, gk104_volt_new },
1866	.ce       = { 0x00000007, gk104_ce_new },
1867	.disp     = { 0x00000001, gk110_disp_new },
1868	.dma      = { 0x00000001, gf119_dma_new },
1869	.fifo     = { 0x00000001, gk208_fifo_new },
1870	.gr       = { 0x00000001, gk208_gr_new },
1871	.mspdec   = { 0x00000001, gk104_mspdec_new },
1872	.msppp    = { 0x00000001, gf100_msppp_new },
1873	.msvld    = { 0x00000001, gk104_msvld_new },
1874	.sw       = { 0x00000001, gf100_sw_new },
1875};
1876
1877static const struct nvkm_device_chip
1878nv117_chipset = {
1879	.name = "GM107",
1880	.bar      = { 0x00000001, gm107_bar_new },
1881	.bios     = { 0x00000001, nvkm_bios_new },
1882	.bus      = { 0x00000001, gf100_bus_new },
1883	.clk      = { 0x00000001, gk104_clk_new },
1884	.devinit  = { 0x00000001, gm107_devinit_new },
1885	.fb       = { 0x00000001, gm107_fb_new },
1886	.fuse     = { 0x00000001, gm107_fuse_new },
1887	.gpio     = { 0x00000001, gk104_gpio_new },
1888	.i2c      = { 0x00000001, gk110_i2c_new },
1889	.iccsense = { 0x00000001, gf100_iccsense_new },
1890	.imem     = { 0x00000001, nv50_instmem_new },
1891	.ltc      = { 0x00000001, gm107_ltc_new },
1892	.mc       = { 0x00000001, gk20a_mc_new },
1893	.mmu      = { 0x00000001, gk104_mmu_new },
1894	.mxm      = { 0x00000001, nv50_mxm_new },
1895	.pci      = { 0x00000001, gk104_pci_new },
1896	.pmu      = { 0x00000001, gm107_pmu_new },
1897	.privring = { 0x00000001, gk104_privring_new },
1898	.therm    = { 0x00000001, gm107_therm_new },
1899	.timer    = { 0x00000001, gk20a_timer_new },
1900	.top      = { 0x00000001, gk104_top_new },
1901	.volt     = { 0x00000001, gk104_volt_new },
1902	.ce       = { 0x00000005, gm107_ce_new },
1903	.disp     = { 0x00000001, gm107_disp_new },
1904	.dma      = { 0x00000001, gf119_dma_new },
1905	.fifo     = { 0x00000001, gm107_fifo_new },
1906	.gr       = { 0x00000001, gm107_gr_new },
1907	.nvdec    = { 0x00000001, gm107_nvdec_new },
1908	.nvenc    = { 0x00000001, gm107_nvenc_new },
1909	.sw       = { 0x00000001, gf100_sw_new },
1910};
1911
1912static const struct nvkm_device_chip
1913nv118_chipset = {
1914	.name = "GM108",
1915	.bar      = { 0x00000001, gm107_bar_new },
1916	.bios     = { 0x00000001, nvkm_bios_new },
1917	.bus      = { 0x00000001, gf100_bus_new },
1918	.clk      = { 0x00000001, gk104_clk_new },
1919	.devinit  = { 0x00000001, gm107_devinit_new },
1920	.fb       = { 0x00000001, gm107_fb_new },
1921	.fuse     = { 0x00000001, gm107_fuse_new },
1922	.gpio     = { 0x00000001, gk104_gpio_new },
1923	.i2c      = { 0x00000001, gk110_i2c_new },
1924	.iccsense = { 0x00000001, gf100_iccsense_new },
1925	.imem     = { 0x00000001, nv50_instmem_new },
1926	.ltc      = { 0x00000001, gm107_ltc_new },
1927	.mc       = { 0x00000001, gk20a_mc_new },
1928	.mmu      = { 0x00000001, gk104_mmu_new },
1929	.mxm      = { 0x00000001, nv50_mxm_new },
1930	.pci      = { 0x00000001, gk104_pci_new },
1931	.pmu      = { 0x00000001, gm107_pmu_new },
1932	.privring = { 0x00000001, gk104_privring_new },
1933	.therm    = { 0x00000001, gm107_therm_new },
1934	.timer    = { 0x00000001, gk20a_timer_new },
1935	.top      = { 0x00000001, gk104_top_new },
1936	.volt     = { 0x00000001, gk104_volt_new },
1937	.ce       = { 0x00000005, gm107_ce_new },
1938	.disp     = { 0x00000001, gm107_disp_new },
1939	.dma      = { 0x00000001, gf119_dma_new },
1940	.fifo     = { 0x00000001, gm107_fifo_new },
1941	.gr       = { 0x00000001, gm107_gr_new },
1942	.sw       = { 0x00000001, gf100_sw_new },
1943};
1944
1945static const struct nvkm_device_chip
1946nv120_chipset = {
1947	.name = "GM200",
1948	.acr      = { 0x00000001, gm200_acr_new },
1949	.bar      = { 0x00000001, gm107_bar_new },
1950	.bios     = { 0x00000001, nvkm_bios_new },
1951	.bus      = { 0x00000001, gf100_bus_new },
1952	.devinit  = { 0x00000001, gm200_devinit_new },
1953	.fb       = { 0x00000001, gm200_fb_new },
1954	.fuse     = { 0x00000001, gm107_fuse_new },
1955	.gpio     = { 0x00000001, gk104_gpio_new },
1956	.i2c      = { 0x00000001, gm200_i2c_new },
1957	.iccsense = { 0x00000001, gf100_iccsense_new },
1958	.imem     = { 0x00000001, nv50_instmem_new },
1959	.ltc      = { 0x00000001, gm200_ltc_new },
1960	.mc       = { 0x00000001, gk20a_mc_new },
1961	.mmu      = { 0x00000001, gm200_mmu_new },
1962	.mxm      = { 0x00000001, nv50_mxm_new },
1963	.pci      = { 0x00000001, gk104_pci_new },
1964	.pmu      = { 0x00000001, gm200_pmu_new },
1965	.privring = { 0x00000001, gm200_privring_new },
1966	.therm    = { 0x00000001, gm200_therm_new },
1967	.timer    = { 0x00000001, gk20a_timer_new },
1968	.top      = { 0x00000001, gk104_top_new },
1969	.volt     = { 0x00000001, gk104_volt_new },
1970	.ce       = { 0x00000007, gm200_ce_new },
1971	.disp     = { 0x00000001, gm200_disp_new },
1972	.dma      = { 0x00000001, gf119_dma_new },
1973	.fifo     = { 0x00000001, gm200_fifo_new },
1974	.gr       = { 0x00000001, gm200_gr_new },
1975	.nvdec    = { 0x00000001, gm107_nvdec_new },
1976	.nvenc    = { 0x00000003, gm107_nvenc_new },
1977	.sw       = { 0x00000001, gf100_sw_new },
1978};
1979
1980static const struct nvkm_device_chip
1981nv124_chipset = {
1982	.name = "GM204",
1983	.acr      = { 0x00000001, gm200_acr_new },
1984	.bar      = { 0x00000001, gm107_bar_new },
1985	.bios     = { 0x00000001, nvkm_bios_new },
1986	.bus      = { 0x00000001, gf100_bus_new },
1987	.devinit  = { 0x00000001, gm200_devinit_new },
1988	.fb       = { 0x00000001, gm200_fb_new },
1989	.fuse     = { 0x00000001, gm107_fuse_new },
1990	.gpio     = { 0x00000001, gk104_gpio_new },
1991	.i2c      = { 0x00000001, gm200_i2c_new },
1992	.iccsense = { 0x00000001, gf100_iccsense_new },
1993	.imem     = { 0x00000001, nv50_instmem_new },
1994	.ltc      = { 0x00000001, gm200_ltc_new },
1995	.mc       = { 0x00000001, gk20a_mc_new },
1996	.mmu      = { 0x00000001, gm200_mmu_new },
1997	.mxm      = { 0x00000001, nv50_mxm_new },
1998	.pci      = { 0x00000001, gk104_pci_new },
1999	.pmu      = { 0x00000001, gm200_pmu_new },
2000	.privring = { 0x00000001, gm200_privring_new },
2001	.therm    = { 0x00000001, gm200_therm_new },
2002	.timer    = { 0x00000001, gk20a_timer_new },
2003	.top      = { 0x00000001, gk104_top_new },
2004	.volt     = { 0x00000001, gk104_volt_new },
2005	.ce       = { 0x00000007, gm200_ce_new },
2006	.disp     = { 0x00000001, gm200_disp_new },
2007	.dma      = { 0x00000001, gf119_dma_new },
2008	.fifo     = { 0x00000001, gm200_fifo_new },
2009	.gr       = { 0x00000001, gm200_gr_new },
2010	.nvdec    = { 0x00000001, gm107_nvdec_new },
2011	.nvenc    = { 0x00000003, gm107_nvenc_new },
2012	.sw       = { 0x00000001, gf100_sw_new },
2013};
2014
2015static const struct nvkm_device_chip
2016nv126_chipset = {
2017	.name = "GM206",
2018	.acr      = { 0x00000001, gm200_acr_new },
2019	.bar      = { 0x00000001, gm107_bar_new },
2020	.bios     = { 0x00000001, nvkm_bios_new },
2021	.bus      = { 0x00000001, gf100_bus_new },
2022	.devinit  = { 0x00000001, gm200_devinit_new },
2023	.fb       = { 0x00000001, gm200_fb_new },
2024	.fuse     = { 0x00000001, gm107_fuse_new },
2025	.gpio     = { 0x00000001, gk104_gpio_new },
2026	.i2c      = { 0x00000001, gm200_i2c_new },
2027	.iccsense = { 0x00000001, gf100_iccsense_new },
2028	.imem     = { 0x00000001, nv50_instmem_new },
2029	.ltc      = { 0x00000001, gm200_ltc_new },
2030	.mc       = { 0x00000001, gk20a_mc_new },
2031	.mmu      = { 0x00000001, gm200_mmu_new },
2032	.mxm      = { 0x00000001, nv50_mxm_new },
2033	.pci      = { 0x00000001, gk104_pci_new },
2034	.pmu      = { 0x00000001, gm200_pmu_new },
2035	.privring = { 0x00000001, gm200_privring_new },
2036	.therm    = { 0x00000001, gm200_therm_new },
2037	.timer    = { 0x00000001, gk20a_timer_new },
2038	.top      = { 0x00000001, gk104_top_new },
2039	.volt     = { 0x00000001, gk104_volt_new },
2040	.ce       = { 0x00000007, gm200_ce_new },
2041	.disp     = { 0x00000001, gm200_disp_new },
2042	.dma      = { 0x00000001, gf119_dma_new },
2043	.fifo     = { 0x00000001, gm200_fifo_new },
2044	.gr       = { 0x00000001, gm200_gr_new },
2045	.nvdec    = { 0x00000001, gm107_nvdec_new },
2046	.nvenc    = { 0x00000001, gm107_nvenc_new },
2047	.sw       = { 0x00000001, gf100_sw_new },
2048};
2049
2050static const struct nvkm_device_chip
2051nv12b_chipset = {
2052	.name = "GM20B",
2053	.acr      = { 0x00000001, gm20b_acr_new },
2054	.bar      = { 0x00000001, gm20b_bar_new },
2055	.bus      = { 0x00000001, gf100_bus_new },
2056	.clk      = { 0x00000001, gm20b_clk_new },
2057	.fb       = { 0x00000001, gm20b_fb_new },
2058	.fuse     = { 0x00000001, gm107_fuse_new },
2059	.imem     = { 0x00000001, gk20a_instmem_new },
2060	.ltc      = { 0x00000001, gm200_ltc_new },
2061	.mc       = { 0x00000001, gk20a_mc_new },
2062	.mmu      = { 0x00000001, gm20b_mmu_new },
2063	.pmu      = { 0x00000001, gm20b_pmu_new },
2064	.privring = { 0x00000001, gk20a_privring_new },
2065	.timer    = { 0x00000001, gk20a_timer_new },
2066	.top      = { 0x00000001, gk104_top_new },
2067	.volt     = { 0x00000001, gm20b_volt_new },
2068	.ce       = { 0x00000004, gm200_ce_new },
2069	.dma      = { 0x00000001, gf119_dma_new },
2070	.fifo     = { 0x00000001, gm200_fifo_new },
2071	.gr       = { 0x00000001, gm20b_gr_new },
2072	.sw       = { 0x00000001, gf100_sw_new },
2073};
2074
2075static const struct nvkm_device_chip
2076nv130_chipset = {
2077	.name = "GP100",
2078	.acr      = { 0x00000001, gm200_acr_new },
2079	.bar      = { 0x00000001, gm107_bar_new },
2080	.bios     = { 0x00000001, nvkm_bios_new },
2081	.bus      = { 0x00000001, gf100_bus_new },
2082	.devinit  = { 0x00000001, gm200_devinit_new },
2083	.fault    = { 0x00000001, gp100_fault_new },
2084	.fb       = { 0x00000001, gp100_fb_new },
2085	.fuse     = { 0x00000001, gm107_fuse_new },
2086	.gpio     = { 0x00000001, gk104_gpio_new },
2087	.i2c      = { 0x00000001, gm200_i2c_new },
2088	.imem     = { 0x00000001, nv50_instmem_new },
2089	.ltc      = { 0x00000001, gp100_ltc_new },
2090	.mc       = { 0x00000001, gp100_mc_new },
2091	.mmu      = { 0x00000001, gp100_mmu_new },
2092	.therm    = { 0x00000001, gp100_therm_new },
2093	.pci      = { 0x00000001, gp100_pci_new },
2094	.pmu      = { 0x00000001, gm200_pmu_new },
2095	.privring = { 0x00000001, gm200_privring_new },
2096	.timer    = { 0x00000001, gk20a_timer_new },
2097	.top      = { 0x00000001, gk104_top_new },
2098	.ce       = { 0x0000003f, gp100_ce_new },
2099	.dma      = { 0x00000001, gf119_dma_new },
2100	.disp     = { 0x00000001, gp100_disp_new },
2101	.fifo     = { 0x00000001, gp100_fifo_new },
2102	.gr       = { 0x00000001, gp100_gr_new },
2103	.nvdec    = { 0x00000001, gm107_nvdec_new },
2104	.nvenc    = { 0x00000007, gm107_nvenc_new },
2105	.sw       = { 0x00000001, gf100_sw_new },
2106};
2107
2108static const struct nvkm_device_chip
2109nv132_chipset = {
2110	.name = "GP102",
2111	.acr      = { 0x00000001, gp102_acr_new },
2112	.bar      = { 0x00000001, gm107_bar_new },
2113	.bios     = { 0x00000001, nvkm_bios_new },
2114	.bus      = { 0x00000001, gf100_bus_new },
2115	.devinit  = { 0x00000001, gm200_devinit_new },
2116	.fault    = { 0x00000001, gp100_fault_new },
2117	.fb       = { 0x00000001, gp102_fb_new },
2118	.fuse     = { 0x00000001, gm107_fuse_new },
2119	.gpio     = { 0x00000001, gk104_gpio_new },
2120	.i2c      = { 0x00000001, gm200_i2c_new },
2121	.imem     = { 0x00000001, nv50_instmem_new },
2122	.ltc      = { 0x00000001, gp102_ltc_new },
2123	.mc       = { 0x00000001, gp100_mc_new },
2124	.mmu      = { 0x00000001, gp100_mmu_new },
2125	.therm    = { 0x00000001, gp100_therm_new },
2126	.pci      = { 0x00000001, gp100_pci_new },
2127	.pmu      = { 0x00000001, gp102_pmu_new },
2128	.privring = { 0x00000001, gm200_privring_new },
2129	.timer    = { 0x00000001, gk20a_timer_new },
2130	.top      = { 0x00000001, gk104_top_new },
2131	.ce       = { 0x0000000f, gp102_ce_new },
2132	.disp     = { 0x00000001, gp102_disp_new },
2133	.dma      = { 0x00000001, gf119_dma_new },
2134	.fifo     = { 0x00000001, gp100_fifo_new },
2135	.gr       = { 0x00000001, gp102_gr_new },
2136	.nvdec    = { 0x00000001, gm107_nvdec_new },
2137	.nvenc    = { 0x00000003, gm107_nvenc_new },
2138	.sec2     = { 0x00000001, gp102_sec2_new },
2139	.sw       = { 0x00000001, gf100_sw_new },
2140};
2141
2142static const struct nvkm_device_chip
2143nv134_chipset = {
2144	.name = "GP104",
2145	.acr      = { 0x00000001, gp102_acr_new },
2146	.bar      = { 0x00000001, gm107_bar_new },
2147	.bios     = { 0x00000001, nvkm_bios_new },
2148	.bus      = { 0x00000001, gf100_bus_new },
2149	.devinit  = { 0x00000001, gm200_devinit_new },
2150	.fault    = { 0x00000001, gp100_fault_new },
2151	.fb       = { 0x00000001, gp102_fb_new },
2152	.fuse     = { 0x00000001, gm107_fuse_new },
2153	.gpio     = { 0x00000001, gk104_gpio_new },
2154	.i2c      = { 0x00000001, gm200_i2c_new },
2155	.imem     = { 0x00000001, nv50_instmem_new },
2156	.ltc      = { 0x00000001, gp102_ltc_new },
2157	.mc       = { 0x00000001, gp100_mc_new },
2158	.mmu      = { 0x00000001, gp100_mmu_new },
2159	.therm    = { 0x00000001, gp100_therm_new },
2160	.pci      = { 0x00000001, gp100_pci_new },
2161	.pmu      = { 0x00000001, gp102_pmu_new },
2162	.privring = { 0x00000001, gm200_privring_new },
2163	.timer    = { 0x00000001, gk20a_timer_new },
2164	.top      = { 0x00000001, gk104_top_new },
2165	.ce       = { 0x0000000f, gp102_ce_new },
2166	.disp     = { 0x00000001, gp102_disp_new },
2167	.dma      = { 0x00000001, gf119_dma_new },
2168	.fifo     = { 0x00000001, gp100_fifo_new },
2169	.gr       = { 0x00000001, gp104_gr_new },
2170	.nvdec    = { 0x00000001, gm107_nvdec_new },
2171	.nvenc    = { 0x00000003, gm107_nvenc_new },
2172	.sec2     = { 0x00000001, gp102_sec2_new },
2173	.sw       = { 0x00000001, gf100_sw_new },
2174};
2175
2176static const struct nvkm_device_chip
2177nv136_chipset = {
2178	.name = "GP106",
2179	.acr      = { 0x00000001, gp102_acr_new },
2180	.bar      = { 0x00000001, gm107_bar_new },
2181	.bios     = { 0x00000001, nvkm_bios_new },
2182	.bus      = { 0x00000001, gf100_bus_new },
2183	.devinit  = { 0x00000001, gm200_devinit_new },
2184	.fault    = { 0x00000001, gp100_fault_new },
2185	.fb       = { 0x00000001, gp102_fb_new },
2186	.fuse     = { 0x00000001, gm107_fuse_new },
2187	.gpio     = { 0x00000001, gk104_gpio_new },
2188	.i2c      = { 0x00000001, gm200_i2c_new },
2189	.imem     = { 0x00000001, nv50_instmem_new },
2190	.ltc      = { 0x00000001, gp102_ltc_new },
2191	.mc       = { 0x00000001, gp100_mc_new },
2192	.mmu      = { 0x00000001, gp100_mmu_new },
2193	.therm    = { 0x00000001, gp100_therm_new },
2194	.pci      = { 0x00000001, gp100_pci_new },
2195	.pmu      = { 0x00000001, gp102_pmu_new },
2196	.privring = { 0x00000001, gm200_privring_new },
2197	.timer    = { 0x00000001, gk20a_timer_new },
2198	.top      = { 0x00000001, gk104_top_new },
2199	.ce       = { 0x0000000f, gp102_ce_new },
2200	.disp     = { 0x00000001, gp102_disp_new },
2201	.dma      = { 0x00000001, gf119_dma_new },
2202	.fifo     = { 0x00000001, gp100_fifo_new },
2203	.gr       = { 0x00000001, gp104_gr_new },
2204	.nvdec    = { 0x00000001, gm107_nvdec_new },
2205	.nvenc    = { 0x00000001, gm107_nvenc_new },
2206	.sec2     = { 0x00000001, gp102_sec2_new },
2207	.sw       = { 0x00000001, gf100_sw_new },
2208};
2209
2210static const struct nvkm_device_chip
2211nv137_chipset = {
2212	.name = "GP107",
2213	.acr      = { 0x00000001, gp102_acr_new },
2214	.bar      = { 0x00000001, gm107_bar_new },
2215	.bios     = { 0x00000001, nvkm_bios_new },
2216	.bus      = { 0x00000001, gf100_bus_new },
2217	.devinit  = { 0x00000001, gm200_devinit_new },
2218	.fault    = { 0x00000001, gp100_fault_new },
2219	.fb       = { 0x00000001, gp102_fb_new },
2220	.fuse     = { 0x00000001, gm107_fuse_new },
2221	.gpio     = { 0x00000001, gk104_gpio_new },
2222	.i2c      = { 0x00000001, gm200_i2c_new },
2223	.imem     = { 0x00000001, nv50_instmem_new },
2224	.ltc      = { 0x00000001, gp102_ltc_new },
2225	.mc       = { 0x00000001, gp100_mc_new },
2226	.mmu      = { 0x00000001, gp100_mmu_new },
2227	.therm    = { 0x00000001, gp100_therm_new },
2228	.pci      = { 0x00000001, gp100_pci_new },
2229	.pmu      = { 0x00000001, gp102_pmu_new },
2230	.privring = { 0x00000001, gm200_privring_new },
2231	.timer    = { 0x00000001, gk20a_timer_new },
2232	.top      = { 0x00000001, gk104_top_new },
2233	.ce       = { 0x0000000f, gp102_ce_new },
2234	.disp     = { 0x00000001, gp102_disp_new },
2235	.dma      = { 0x00000001, gf119_dma_new },
2236	.fifo     = { 0x00000001, gp100_fifo_new },
2237	.gr       = { 0x00000001, gp107_gr_new },
2238	.nvdec    = { 0x00000001, gm107_nvdec_new },
2239	.nvenc    = { 0x00000003, gm107_nvenc_new },
2240	.sec2     = { 0x00000001, gp102_sec2_new },
2241	.sw       = { 0x00000001, gf100_sw_new },
2242};
2243
2244static const struct nvkm_device_chip
2245nv138_chipset = {
2246	.name = "GP108",
2247	.acr      = { 0x00000001, gp108_acr_new },
2248	.bar      = { 0x00000001, gm107_bar_new },
2249	.bios     = { 0x00000001, nvkm_bios_new },
2250	.bus      = { 0x00000001, gf100_bus_new },
2251	.devinit  = { 0x00000001, gm200_devinit_new },
2252	.fault    = { 0x00000001, gp100_fault_new },
2253	.fb       = { 0x00000001, gp102_fb_new },
2254	.fuse     = { 0x00000001, gm107_fuse_new },
2255	.gpio     = { 0x00000001, gk104_gpio_new },
2256	.i2c      = { 0x00000001, gm200_i2c_new },
2257	.imem     = { 0x00000001, nv50_instmem_new },
2258	.ltc      = { 0x00000001, gp102_ltc_new },
2259	.mc       = { 0x00000001, gp100_mc_new },
2260	.mmu      = { 0x00000001, gp100_mmu_new },
2261	.therm    = { 0x00000001, gp100_therm_new },
2262	.pci      = { 0x00000001, gp100_pci_new },
2263	.pmu      = { 0x00000001, gp102_pmu_new },
2264	.privring = { 0x00000001, gm200_privring_new },
2265	.timer    = { 0x00000001, gk20a_timer_new },
2266	.top      = { 0x00000001, gk104_top_new },
2267	.ce       = { 0x0000000f, gp102_ce_new },
2268	.disp     = { 0x00000001, gp102_disp_new },
2269	.dma      = { 0x00000001, gf119_dma_new },
2270	.fifo     = { 0x00000001, gp100_fifo_new },
2271	.gr       = { 0x00000001, gp108_gr_new },
2272	.nvdec    = { 0x00000001, gm107_nvdec_new },
2273	.sec2     = { 0x00000001, gp108_sec2_new },
2274	.sw       = { 0x00000001, gf100_sw_new },
2275};
2276
2277static const struct nvkm_device_chip
2278nv13b_chipset = {
2279	.name = "GP10B",
2280	.acr      = { 0x00000001, gp10b_acr_new },
2281	.bar      = { 0x00000001, gm20b_bar_new },
2282	.bus      = { 0x00000001, gf100_bus_new },
2283	.clk      = { 0x00000001, gp10b_clk_new },
2284	.fault    = { 0x00000001, gp10b_fault_new },
2285	.fb       = { 0x00000001, gp10b_fb_new },
2286	.fuse     = { 0x00000001, gm107_fuse_new },
2287	.imem     = { 0x00000001, gk20a_instmem_new },
2288	.ltc      = { 0x00000001, gp10b_ltc_new },
2289	.mc       = { 0x00000001, gp10b_mc_new },
2290	.mmu      = { 0x00000001, gp10b_mmu_new },
2291	.pmu      = { 0x00000001, gp10b_pmu_new },
2292	.privring = { 0x00000001, gp10b_privring_new },
2293	.timer    = { 0x00000001, gk20a_timer_new },
2294	.top      = { 0x00000001, gk104_top_new },
2295	.ce       = { 0x00000001, gp100_ce_new },
2296	.dma      = { 0x00000001, gf119_dma_new },
2297	.fifo     = { 0x00000001, gp100_fifo_new },
2298	.gr       = { 0x00000001, gp10b_gr_new },
2299	.sw       = { 0x00000001, gf100_sw_new },
2300};
2301
2302static const struct nvkm_device_chip
2303nv140_chipset = {
2304	.name = "GV100",
2305	.acr      = { 0x00000001, gv100_acr_new },
2306	.bar      = { 0x00000001, gm107_bar_new },
2307	.bios     = { 0x00000001, nvkm_bios_new },
2308	.bus      = { 0x00000001, gf100_bus_new },
2309	.devinit  = { 0x00000001, gv100_devinit_new },
2310	.fault    = { 0x00000001, gv100_fault_new },
2311	.fb       = { 0x00000001, gv100_fb_new },
2312	.fuse     = { 0x00000001, gm107_fuse_new },
2313	.gpio     = { 0x00000001, gk104_gpio_new },
2314	.gsp      = { 0x00000001, gv100_gsp_new },
2315	.i2c      = { 0x00000001, gm200_i2c_new },
2316	.imem     = { 0x00000001, nv50_instmem_new },
2317	.ltc      = { 0x00000001, gp102_ltc_new },
2318	.mc       = { 0x00000001, gp100_mc_new },
2319	.mmu      = { 0x00000001, gv100_mmu_new },
2320	.pci      = { 0x00000001, gp100_pci_new },
2321	.pmu      = { 0x00000001, gp102_pmu_new },
2322	.privring = { 0x00000001, gm200_privring_new },
2323	.therm    = { 0x00000001, gp100_therm_new },
2324	.timer    = { 0x00000001, gk20a_timer_new },
2325	.top      = { 0x00000001, gk104_top_new },
2326	.vfn      = { 0x00000001, gv100_vfn_new },
2327	.ce       = { 0x000001ff, gv100_ce_new },
2328	.disp     = { 0x00000001, gv100_disp_new },
2329	.dma      = { 0x00000001, gv100_dma_new },
2330	.fifo     = { 0x00000001, gv100_fifo_new },
2331	.gr       = { 0x00000001, gv100_gr_new },
2332	.nvdec    = { 0x00000001, gm107_nvdec_new },
2333	.nvenc    = { 0x00000007, gm107_nvenc_new },
2334	.sec2     = { 0x00000001, gp108_sec2_new },
2335};
2336
2337static const struct nvkm_device_chip
2338nv162_chipset = {
2339	.name = "TU102",
2340	.acr      = { 0x00000001, tu102_acr_new },
2341	.bar      = { 0x00000001, tu102_bar_new },
2342	.bios     = { 0x00000001, nvkm_bios_new },
2343	.bus      = { 0x00000001, gf100_bus_new },
2344	.devinit  = { 0x00000001, tu102_devinit_new },
2345	.fault    = { 0x00000001, tu102_fault_new },
2346	.fb       = { 0x00000001, tu102_fb_new },
2347	.fuse     = { 0x00000001, gm107_fuse_new },
2348	.gpio     = { 0x00000001, gk104_gpio_new },
2349	.gsp      = { 0x00000001, tu102_gsp_new },
2350	.i2c      = { 0x00000001, gm200_i2c_new },
2351	.imem     = { 0x00000001, nv50_instmem_new },
2352	.ltc      = { 0x00000001, gp102_ltc_new },
2353	.mc       = { 0x00000001, gp100_mc_new },
2354	.mmu      = { 0x00000001, tu102_mmu_new },
2355	.pci      = { 0x00000001, gp100_pci_new },
2356	.pmu      = { 0x00000001, gp102_pmu_new },
2357	.privring = { 0x00000001, gm200_privring_new },
2358	.therm    = { 0x00000001, gp100_therm_new },
2359	.timer    = { 0x00000001, gk20a_timer_new },
2360	.top      = { 0x00000001, gk104_top_new },
2361	.vfn      = { 0x00000001, tu102_vfn_new },
2362	.ce       = { 0x0000001f, tu102_ce_new },
2363	.disp     = { 0x00000001, tu102_disp_new },
2364	.dma      = { 0x00000001, gv100_dma_new },
2365	.fifo     = { 0x00000001, tu102_fifo_new },
2366	.gr       = { 0x00000001, tu102_gr_new },
2367	.nvdec    = { 0x00000001, tu102_nvdec_new },
2368	.nvenc    = { 0x00000001, tu102_nvenc_new },
2369	.sec2     = { 0x00000001, tu102_sec2_new },
2370};
2371
2372static const struct nvkm_device_chip
2373nv164_chipset = {
2374	.name = "TU104",
2375	.acr      = { 0x00000001, tu102_acr_new },
2376	.bar      = { 0x00000001, tu102_bar_new },
2377	.bios     = { 0x00000001, nvkm_bios_new },
2378	.bus      = { 0x00000001, gf100_bus_new },
2379	.devinit  = { 0x00000001, tu102_devinit_new },
2380	.fault    = { 0x00000001, tu102_fault_new },
2381	.fb       = { 0x00000001, tu102_fb_new },
2382	.fuse     = { 0x00000001, gm107_fuse_new },
2383	.gpio     = { 0x00000001, gk104_gpio_new },
2384	.gsp      = { 0x00000001, tu102_gsp_new },
2385	.i2c      = { 0x00000001, gm200_i2c_new },
2386	.imem     = { 0x00000001, nv50_instmem_new },
2387	.ltc      = { 0x00000001, gp102_ltc_new },
2388	.mc       = { 0x00000001, gp100_mc_new },
2389	.mmu      = { 0x00000001, tu102_mmu_new },
2390	.pci      = { 0x00000001, gp100_pci_new },
2391	.pmu      = { 0x00000001, gp102_pmu_new },
2392	.privring = { 0x00000001, gm200_privring_new },
2393	.therm    = { 0x00000001, gp100_therm_new },
2394	.timer    = { 0x00000001, gk20a_timer_new },
2395	.top      = { 0x00000001, gk104_top_new },
2396	.vfn      = { 0x00000001, tu102_vfn_new },
2397	.ce       = { 0x0000001f, tu102_ce_new },
2398	.disp     = { 0x00000001, tu102_disp_new },
2399	.dma      = { 0x00000001, gv100_dma_new },
2400	.fifo     = { 0x00000001, tu102_fifo_new },
2401	.gr       = { 0x00000001, tu102_gr_new },
2402	.nvdec    = { 0x00000003, tu102_nvdec_new },
2403	.nvenc    = { 0x00000001, tu102_nvenc_new },
2404	.sec2     = { 0x00000001, tu102_sec2_new },
2405};
2406
2407static const struct nvkm_device_chip
2408nv166_chipset = {
2409	.name = "TU106",
2410	.acr      = { 0x00000001, tu102_acr_new },
2411	.bar      = { 0x00000001, tu102_bar_new },
2412	.bios     = { 0x00000001, nvkm_bios_new },
2413	.bus      = { 0x00000001, gf100_bus_new },
2414	.devinit  = { 0x00000001, tu102_devinit_new },
2415	.fault    = { 0x00000001, tu102_fault_new },
2416	.fb       = { 0x00000001, tu102_fb_new },
2417	.fuse     = { 0x00000001, gm107_fuse_new },
2418	.gpio     = { 0x00000001, gk104_gpio_new },
2419	.gsp      = { 0x00000001, tu102_gsp_new },
2420	.i2c      = { 0x00000001, gm200_i2c_new },
2421	.imem     = { 0x00000001, nv50_instmem_new },
2422	.ltc      = { 0x00000001, gp102_ltc_new },
2423	.mc       = { 0x00000001, gp100_mc_new },
2424	.mmu      = { 0x00000001, tu102_mmu_new },
2425	.pci      = { 0x00000001, gp100_pci_new },
2426	.pmu      = { 0x00000001, gp102_pmu_new },
2427	.privring = { 0x00000001, gm200_privring_new },
2428	.therm    = { 0x00000001, gp100_therm_new },
2429	.timer    = { 0x00000001, gk20a_timer_new },
2430	.top      = { 0x00000001, gk104_top_new },
2431	.vfn      = { 0x00000001, tu102_vfn_new },
2432	.ce       = { 0x0000001f, tu102_ce_new },
2433	.disp     = { 0x00000001, tu102_disp_new },
2434	.dma      = { 0x00000001, gv100_dma_new },
2435	.fifo     = { 0x00000001, tu102_fifo_new },
2436	.gr       = { 0x00000001, tu102_gr_new },
2437	.nvdec    = { 0x00000007, tu102_nvdec_new },
2438	.nvenc    = { 0x00000001, tu102_nvenc_new },
2439	.sec2     = { 0x00000001, tu102_sec2_new },
2440};
2441
2442static const struct nvkm_device_chip
2443nv167_chipset = {
2444	.name = "TU117",
2445	.acr      = { 0x00000001, tu102_acr_new },
2446	.bar      = { 0x00000001, tu102_bar_new },
2447	.bios     = { 0x00000001, nvkm_bios_new },
2448	.bus      = { 0x00000001, gf100_bus_new },
2449	.devinit  = { 0x00000001, tu102_devinit_new },
2450	.fault    = { 0x00000001, tu102_fault_new },
2451	.fb       = { 0x00000001, tu102_fb_new },
2452	.fuse     = { 0x00000001, gm107_fuse_new },
2453	.gpio     = { 0x00000001, gk104_gpio_new },
2454	.gsp      = { 0x00000001, tu116_gsp_new },
2455	.i2c      = { 0x00000001, gm200_i2c_new },
2456	.imem     = { 0x00000001, nv50_instmem_new },
2457	.ltc      = { 0x00000001, gp102_ltc_new },
2458	.mc       = { 0x00000001, gp100_mc_new },
2459	.mmu      = { 0x00000001, tu102_mmu_new },
2460	.pci      = { 0x00000001, gp100_pci_new },
2461	.pmu      = { 0x00000001, gp102_pmu_new },
2462	.privring = { 0x00000001, gm200_privring_new },
2463	.therm    = { 0x00000001, gp100_therm_new },
2464	.timer    = { 0x00000001, gk20a_timer_new },
2465	.top      = { 0x00000001, gk104_top_new },
2466	.vfn      = { 0x00000001, tu102_vfn_new },
2467	.ce       = { 0x0000001f, tu102_ce_new },
2468	.disp     = { 0x00000001, tu102_disp_new },
2469	.dma      = { 0x00000001, gv100_dma_new },
2470	.fifo     = { 0x00000001, tu102_fifo_new },
2471	.gr       = { 0x00000001, tu102_gr_new },
2472	.nvdec    = { 0x00000001, tu102_nvdec_new },
2473	.nvenc    = { 0x00000001, tu102_nvenc_new },
2474	.sec2     = { 0x00000001, tu102_sec2_new },
2475};
2476
2477static const struct nvkm_device_chip
2478nv168_chipset = {
2479	.name = "TU116",
2480	.acr      = { 0x00000001, tu102_acr_new },
2481	.bar      = { 0x00000001, tu102_bar_new },
2482	.bios     = { 0x00000001, nvkm_bios_new },
2483	.bus      = { 0x00000001, gf100_bus_new },
2484	.devinit  = { 0x00000001, tu102_devinit_new },
2485	.fault    = { 0x00000001, tu102_fault_new },
2486	.fb       = { 0x00000001, tu102_fb_new },
2487	.fuse     = { 0x00000001, gm107_fuse_new },
2488	.gpio     = { 0x00000001, gk104_gpio_new },
2489	.gsp      = { 0x00000001, tu116_gsp_new },
2490	.i2c      = { 0x00000001, gm200_i2c_new },
2491	.imem     = { 0x00000001, nv50_instmem_new },
2492	.ltc      = { 0x00000001, gp102_ltc_new },
2493	.mc       = { 0x00000001, gp100_mc_new },
2494	.mmu      = { 0x00000001, tu102_mmu_new },
2495	.pci      = { 0x00000001, gp100_pci_new },
2496	.pmu      = { 0x00000001, gp102_pmu_new },
2497	.privring = { 0x00000001, gm200_privring_new },
2498	.therm    = { 0x00000001, gp100_therm_new },
2499	.timer    = { 0x00000001, gk20a_timer_new },
2500	.top      = { 0x00000001, gk104_top_new },
2501	.vfn      = { 0x00000001, tu102_vfn_new },
2502	.ce       = { 0x0000001f, tu102_ce_new },
2503	.disp     = { 0x00000001, tu102_disp_new },
2504	.dma      = { 0x00000001, gv100_dma_new },
2505	.fifo     = { 0x00000001, tu102_fifo_new },
2506	.gr       = { 0x00000001, tu102_gr_new },
2507	.nvdec    = { 0x00000001, tu102_nvdec_new },
2508	.nvenc    = { 0x00000001, tu102_nvenc_new },
2509	.sec2     = { 0x00000001, tu102_sec2_new },
2510};
2511
2512static const struct nvkm_device_chip
2513nv170_chipset = {
2514	.name = "GA100",
2515	.bar      = { 0x00000001, tu102_bar_new },
2516	.bios     = { 0x00000001, nvkm_bios_new },
2517	.devinit  = { 0x00000001, ga100_devinit_new },
2518	.fault    = { 0x00000001, tu102_fault_new },
2519	.fb       = { 0x00000001, ga100_fb_new },
2520	.gpio     = { 0x00000001, gk104_gpio_new },
2521	.gsp      = { 0x00000001, ga100_gsp_new },
2522	.i2c      = { 0x00000001, gm200_i2c_new },
2523	.imem     = { 0x00000001, nv50_instmem_new },
2524	.mc       = { 0x00000001, ga100_mc_new },
2525	.mmu      = { 0x00000001, tu102_mmu_new },
2526	.pci      = { 0x00000001, gp100_pci_new },
2527	.privring = { 0x00000001, gm200_privring_new },
2528	.timer    = { 0x00000001, gk20a_timer_new },
2529	.top      = { 0x00000001, ga100_top_new },
2530	.vfn      = { 0x00000001, ga100_vfn_new },
2531	.ce       = { 0x000003ff, ga100_ce_new },
2532	.fifo     = { 0x00000001, ga100_fifo_new },
2533};
2534
2535static const struct nvkm_device_chip
2536nv172_chipset = {
2537	.name = "GA102",
2538	.acr      = { 0x00000001, ga102_acr_new },
2539	.bar      = { 0x00000001, tu102_bar_new },
2540	.bios     = { 0x00000001, nvkm_bios_new },
2541	.devinit  = { 0x00000001, ga100_devinit_new },
2542	.fault    = { 0x00000001, tu102_fault_new },
2543	.fb       = { 0x00000001, ga102_fb_new },
2544	.gpio     = { 0x00000001, ga102_gpio_new },
2545	.gsp      = { 0x00000001, ga102_gsp_new },
2546	.i2c      = { 0x00000001, gm200_i2c_new },
2547	.imem     = { 0x00000001, nv50_instmem_new },
2548	.ltc      = { 0x00000001, ga102_ltc_new },
2549	.mc       = { 0x00000001, ga100_mc_new },
2550	.mmu      = { 0x00000001, tu102_mmu_new },
2551	.pci      = { 0x00000001, gp100_pci_new },
2552	.privring = { 0x00000001, gm200_privring_new },
2553	.timer    = { 0x00000001, gk20a_timer_new },
2554	.top      = { 0x00000001, ga100_top_new },
2555	.vfn      = { 0x00000001, ga100_vfn_new },
2556	.ce       = { 0x0000001f, ga102_ce_new },
2557	.disp     = { 0x00000001, ga102_disp_new },
2558	.dma      = { 0x00000001, gv100_dma_new },
2559	.fifo     = { 0x00000001, ga102_fifo_new },
2560	.gr       = { 0x00000001, ga102_gr_new },
2561	.nvdec    = { 0x00000003, ga102_nvdec_new },
2562	.sec2     = { 0x00000001, ga102_sec2_new },
2563};
2564
2565static const struct nvkm_device_chip
2566nv173_chipset = {
2567	.name = "GA103",
2568	.acr      = { 0x00000001, ga102_acr_new },
2569	.bar      = { 0x00000001, tu102_bar_new },
2570	.bios     = { 0x00000001, nvkm_bios_new },
2571	.devinit  = { 0x00000001, ga100_devinit_new },
2572	.fault    = { 0x00000001, tu102_fault_new },
2573	.fb       = { 0x00000001, ga102_fb_new },
2574	.gpio     = { 0x00000001, ga102_gpio_new },
2575	.gsp      = { 0x00000001, ga102_gsp_new },
2576	.i2c      = { 0x00000001, gm200_i2c_new },
2577	.imem     = { 0x00000001, nv50_instmem_new },
2578	.ltc      = { 0x00000001, ga102_ltc_new },
2579	.mc       = { 0x00000001, ga100_mc_new },
2580	.mmu      = { 0x00000001, tu102_mmu_new },
2581	.pci      = { 0x00000001, gp100_pci_new },
2582	.privring = { 0x00000001, gm200_privring_new },
2583	.timer    = { 0x00000001, gk20a_timer_new },
2584	.top      = { 0x00000001, ga100_top_new },
2585	.vfn      = { 0x00000001, ga100_vfn_new },
2586	.ce       = { 0x0000001f, ga102_ce_new },
2587	.disp     = { 0x00000001, ga102_disp_new },
2588	.dma      = { 0x00000001, gv100_dma_new },
2589	.fifo     = { 0x00000001, ga102_fifo_new },
2590	.gr       = { 0x00000001, ga102_gr_new },
2591	.nvdec    = { 0x00000003, ga102_nvdec_new },
2592	.sec2     = { 0x00000001, ga102_sec2_new },
2593};
2594
2595static const struct nvkm_device_chip
2596nv174_chipset = {
2597	.name = "GA104",
2598	.acr      = { 0x00000001, ga102_acr_new },
2599	.bar      = { 0x00000001, tu102_bar_new },
2600	.bios     = { 0x00000001, nvkm_bios_new },
2601	.devinit  = { 0x00000001, ga100_devinit_new },
2602	.fault    = { 0x00000001, tu102_fault_new },
2603	.fb       = { 0x00000001, ga102_fb_new },
2604	.gpio     = { 0x00000001, ga102_gpio_new },
2605	.gsp      = { 0x00000001, ga102_gsp_new },
2606	.i2c      = { 0x00000001, gm200_i2c_new },
2607	.imem     = { 0x00000001, nv50_instmem_new },
2608	.ltc      = { 0x00000001, ga102_ltc_new },
2609	.mc       = { 0x00000001, ga100_mc_new },
2610	.mmu      = { 0x00000001, tu102_mmu_new },
2611	.pci      = { 0x00000001, gp100_pci_new },
2612	.privring = { 0x00000001, gm200_privring_new },
2613	.timer    = { 0x00000001, gk20a_timer_new },
2614	.top      = { 0x00000001, ga100_top_new },
2615	.vfn      = { 0x00000001, ga100_vfn_new },
2616	.ce       = { 0x0000001f, ga102_ce_new },
2617	.disp     = { 0x00000001, ga102_disp_new },
2618	.dma      = { 0x00000001, gv100_dma_new },
2619	.fifo     = { 0x00000001, ga102_fifo_new },
2620	.gr       = { 0x00000001, ga102_gr_new },
2621	.nvdec    = { 0x00000003, ga102_nvdec_new },
2622	.sec2     = { 0x00000001, ga102_sec2_new },
2623};
2624
2625static const struct nvkm_device_chip
2626nv176_chipset = {
2627	.name = "GA106",
2628	.acr      = { 0x00000001, ga102_acr_new },
2629	.bar      = { 0x00000001, tu102_bar_new },
2630	.bios     = { 0x00000001, nvkm_bios_new },
2631	.devinit  = { 0x00000001, ga100_devinit_new },
2632	.fault    = { 0x00000001, tu102_fault_new },
2633	.fb       = { 0x00000001, ga102_fb_new },
2634	.gpio     = { 0x00000001, ga102_gpio_new },
2635	.gsp      = { 0x00000001, ga102_gsp_new },
2636	.i2c      = { 0x00000001, gm200_i2c_new },
2637	.imem     = { 0x00000001, nv50_instmem_new },
2638	.ltc      = { 0x00000001, ga102_ltc_new },
2639	.mc       = { 0x00000001, ga100_mc_new },
2640	.mmu      = { 0x00000001, tu102_mmu_new },
2641	.pci      = { 0x00000001, gp100_pci_new },
2642	.privring = { 0x00000001, gm200_privring_new },
2643	.timer    = { 0x00000001, gk20a_timer_new },
2644	.top      = { 0x00000001, ga100_top_new },
2645	.vfn      = { 0x00000001, ga100_vfn_new },
2646	.ce       = { 0x0000001f, ga102_ce_new },
2647	.disp     = { 0x00000001, ga102_disp_new },
2648	.dma      = { 0x00000001, gv100_dma_new },
2649	.fifo     = { 0x00000001, ga102_fifo_new },
2650	.gr       = { 0x00000001, ga102_gr_new },
2651	.nvdec    = { 0x00000003, ga102_nvdec_new },
2652	.sec2     = { 0x00000001, ga102_sec2_new },
2653};
2654
2655static const struct nvkm_device_chip
2656nv177_chipset = {
2657	.name = "GA107",
2658	.acr      = { 0x00000001, ga102_acr_new },
2659	.bar      = { 0x00000001, tu102_bar_new },
2660	.bios     = { 0x00000001, nvkm_bios_new },
2661	.devinit  = { 0x00000001, ga100_devinit_new },
2662	.fault    = { 0x00000001, tu102_fault_new },
2663	.fb       = { 0x00000001, ga102_fb_new },
2664	.gpio     = { 0x00000001, ga102_gpio_new },
2665	.gsp      = { 0x00000001, ga102_gsp_new },
2666	.i2c      = { 0x00000001, gm200_i2c_new },
2667	.imem     = { 0x00000001, nv50_instmem_new },
2668	.ltc      = { 0x00000001, ga102_ltc_new },
2669	.mc       = { 0x00000001, ga100_mc_new },
2670	.mmu      = { 0x00000001, tu102_mmu_new },
2671	.pci      = { 0x00000001, gp100_pci_new },
2672	.privring = { 0x00000001, gm200_privring_new },
2673	.timer    = { 0x00000001, gk20a_timer_new },
2674	.top      = { 0x00000001, ga100_top_new },
2675	.vfn      = { 0x00000001, ga100_vfn_new },
2676	.ce       = { 0x0000001f, ga102_ce_new },
2677	.disp     = { 0x00000001, ga102_disp_new },
2678	.dma      = { 0x00000001, gv100_dma_new },
2679	.fifo     = { 0x00000001, ga102_fifo_new },
2680	.gr       = { 0x00000001, ga102_gr_new },
2681	.nvdec    = { 0x00000003, ga102_nvdec_new },
2682	.sec2     = { 0x00000001, ga102_sec2_new },
2683};
2684
2685static const struct nvkm_device_chip
2686nv180_chipset = {
2687	.name = "GH100",
2688	.bar      = { 0x00000001, tu102_bar_new },
2689	.fault    = { 0x00000001, tu102_fault_new },
2690	.fb       = { 0x00000001, gh100_fb_new },
2691	.fsp      = { 0x00000001, gh100_fsp_new },
2692	.gsp      = { 0x00000001, gh100_gsp_new },
2693	.imem     = { 0x00000001, gh100_instmem_new },
2694	.mmu      = { 0x00000001, gh100_mmu_new },
2695	.pci      = { 0x00000001, gh100_pci_new },
2696	.timer    = { 0x00000001, gk20a_timer_new },
2697	.vfn      = { 0x00000001, ga100_vfn_new },
2698	.fifo     = { 0x00000001, ga102_fifo_new },
2699};
2700
2701static const struct nvkm_device_chip
2702nv192_chipset = {
2703	.name = "AD102",
2704	.bar      = { 0x00000001, tu102_bar_new },
2705	.bios     = { 0x00000001, nvkm_bios_new },
2706	.devinit  = { 0x00000001, ga100_devinit_new },
2707	.fault    = { 0x00000001, tu102_fault_new },
2708	.fb       = { 0x00000001, ga102_fb_new },
2709	.gsp      = { 0x00000001, ad102_gsp_new },
2710	.imem     = { 0x00000001, nv50_instmem_new },
2711	.mmu      = { 0x00000001, tu102_mmu_new },
2712	.pci      = { 0x00000001, gp100_pci_new },
2713	.timer    = { 0x00000001, gk20a_timer_new },
2714	.vfn      = { 0x00000001, ga100_vfn_new },
2715	.ce       = { 0x0000001f, ga102_ce_new },
2716	.disp     = { 0x00000001, ga102_disp_new },
2717	.dma      = { 0x00000001, gv100_dma_new },
2718	.fifo     = { 0x00000001, ga102_fifo_new },
2719	.sec2     = { 0x00000001, ga102_sec2_new },
2720};
2721
2722static const struct nvkm_device_chip
2723nv193_chipset = {
2724	.name = "AD103",
2725	.bar      = { 0x00000001, tu102_bar_new },
2726	.bios     = { 0x00000001, nvkm_bios_new },
2727	.devinit  = { 0x00000001, ga100_devinit_new },
2728	.fault    = { 0x00000001, tu102_fault_new },
2729	.fb       = { 0x00000001, ga102_fb_new },
2730	.gsp      = { 0x00000001, ad102_gsp_new },
2731	.imem     = { 0x00000001, nv50_instmem_new },
2732	.mmu      = { 0x00000001, tu102_mmu_new },
2733	.pci      = { 0x00000001, gp100_pci_new },
2734	.timer    = { 0x00000001, gk20a_timer_new },
2735	.vfn      = { 0x00000001, ga100_vfn_new },
2736	.ce       = { 0x0000001f, ga102_ce_new },
2737	.disp     = { 0x00000001, ga102_disp_new },
2738	.dma      = { 0x00000001, gv100_dma_new },
2739	.fifo     = { 0x00000001, ga102_fifo_new },
2740	.sec2     = { 0x00000001, ga102_sec2_new },
2741};
2742
2743static const struct nvkm_device_chip
2744nv194_chipset = {
2745	.name = "AD104",
2746	.bar      = { 0x00000001, tu102_bar_new },
2747	.bios     = { 0x00000001, nvkm_bios_new },
2748	.devinit  = { 0x00000001, ga100_devinit_new },
2749	.fault    = { 0x00000001, tu102_fault_new },
2750	.fb       = { 0x00000001, ga102_fb_new },
2751	.gsp      = { 0x00000001, ad102_gsp_new },
2752	.imem     = { 0x00000001, nv50_instmem_new },
2753	.mmu      = { 0x00000001, tu102_mmu_new },
2754	.pci      = { 0x00000001, gp100_pci_new },
2755	.timer    = { 0x00000001, gk20a_timer_new },
2756	.vfn      = { 0x00000001, ga100_vfn_new },
2757	.ce       = { 0x0000001f, ga102_ce_new },
2758	.disp     = { 0x00000001, ga102_disp_new },
2759	.dma      = { 0x00000001, gv100_dma_new },
2760	.fifo     = { 0x00000001, ga102_fifo_new },
2761	.sec2     = { 0x00000001, ga102_sec2_new },
2762};
2763
2764static const struct nvkm_device_chip
2765nv196_chipset = {
2766	.name = "AD106",
2767	.bar      = { 0x00000001, tu102_bar_new },
2768	.bios     = { 0x00000001, nvkm_bios_new },
2769	.devinit  = { 0x00000001, ga100_devinit_new },
2770	.fault    = { 0x00000001, tu102_fault_new },
2771	.fb       = { 0x00000001, ga102_fb_new },
2772	.gsp      = { 0x00000001, ad102_gsp_new },
2773	.imem     = { 0x00000001, nv50_instmem_new },
2774	.mmu      = { 0x00000001, tu102_mmu_new },
2775	.pci      = { 0x00000001, gp100_pci_new },
2776	.timer    = { 0x00000001, gk20a_timer_new },
2777	.vfn      = { 0x00000001, ga100_vfn_new },
2778	.ce       = { 0x0000001f, ga102_ce_new },
2779	.disp     = { 0x00000001, ga102_disp_new },
2780	.dma      = { 0x00000001, gv100_dma_new },
2781	.fifo     = { 0x00000001, ga102_fifo_new },
2782	.sec2     = { 0x00000001, ga102_sec2_new },
2783};
2784
2785static const struct nvkm_device_chip
2786nv197_chipset = {
2787	.name = "AD107",
2788	.bar      = { 0x00000001, tu102_bar_new },
2789	.bios     = { 0x00000001, nvkm_bios_new },
2790	.devinit  = { 0x00000001, ga100_devinit_new },
2791	.fault    = { 0x00000001, tu102_fault_new },
2792	.fb       = { 0x00000001, ga102_fb_new },
2793	.gsp      = { 0x00000001, ad102_gsp_new },
2794	.imem     = { 0x00000001, nv50_instmem_new },
2795	.mmu      = { 0x00000001, tu102_mmu_new },
2796	.pci      = { 0x00000001, gp100_pci_new },
2797	.timer    = { 0x00000001, gk20a_timer_new },
2798	.vfn      = { 0x00000001, ga100_vfn_new },
2799	.ce       = { 0x0000001f, ga102_ce_new },
2800	.disp     = { 0x00000001, ga102_disp_new },
2801	.dma      = { 0x00000001, gv100_dma_new },
2802	.fifo     = { 0x00000001, ga102_fifo_new },
2803	.sec2     = { 0x00000001, ga102_sec2_new },
2804};
2805
2806static const struct nvkm_device_chip
2807nv1a0_chipset = {
2808	.name = "GB100",
2809	.bar      = { 0x00000001, tu102_bar_new },
2810	.fb       = { 0x00000001, gb100_fb_new },
2811	.fsp      = { 0x00000001, gb100_fsp_new },
2812	.gsp      = { 0x00000001, gb100_gsp_new },
2813	.imem     = { 0x00000001, gh100_instmem_new },
2814	.mmu      = { 0x00000001, gh100_mmu_new },
2815	.pci      = { 0x00000001, gh100_pci_new },
2816	.timer    = { 0x00000001, gk20a_timer_new },
2817	.vfn      = { 0x00000001, ga100_vfn_new },
2818	.fifo     = { 0x00000001, ga102_fifo_new },
2819};
2820
2821static const struct nvkm_device_chip
2822nv1a2_chipset = {
2823	.name = "GB102",
2824	.bar      = { 0x00000001, tu102_bar_new },
2825	.fb       = { 0x00000001, gb100_fb_new },
2826	.fsp      = { 0x00000001, gb100_fsp_new },
2827	.gsp      = { 0x00000001, gb100_gsp_new },
2828	.imem     = { 0x00000001, gh100_instmem_new },
2829	.mmu      = { 0x00000001, gh100_mmu_new },
2830	.pci      = { 0x00000001, gh100_pci_new },
2831	.timer    = { 0x00000001, gk20a_timer_new },
2832	.vfn      = { 0x00000001, ga100_vfn_new },
2833	.fifo     = { 0x00000001, ga102_fifo_new },
2834};
2835
2836static const struct nvkm_device_chip
2837nv1b2_chipset = {
2838	.name = "GB202",
2839	.bar      = { 0x00000001, tu102_bar_new },
2840	.fb       = { 0x00000001, gb202_fb_new },
2841	.fsp      = { 0x00000001, gb202_fsp_new },
2842	.gsp      = { 0x00000001, gb202_gsp_new },
2843	.imem     = { 0x00000001, gh100_instmem_new },
2844	.mmu      = { 0x00000001, gh100_mmu_new },
2845	.pci      = { 0x00000001, gh100_pci_new },
2846	.timer    = { 0x00000001, gk20a_timer_new },
2847	.vfn      = { 0x00000001, ga100_vfn_new },
2848	.disp     = { 0x00000001, ga102_disp_new },
2849	.fifo     = { 0x00000001, ga102_fifo_new },
2850};
2851
2852static const struct nvkm_device_chip
2853nv1b3_chipset = {
2854	.name = "GB203",
2855	.bar      = { 0x00000001, tu102_bar_new },
2856	.fb       = { 0x00000001, gb202_fb_new },
2857	.fsp      = { 0x00000001, gb202_fsp_new },
2858	.gsp      = { 0x00000001, gb202_gsp_new },
2859	.imem     = { 0x00000001, gh100_instmem_new },
2860	.mmu      = { 0x00000001, gh100_mmu_new },
2861	.pci      = { 0x00000001, gh100_pci_new },
2862	.timer    = { 0x00000001, gk20a_timer_new },
2863	.vfn      = { 0x00000001, ga100_vfn_new },
2864	.disp     = { 0x00000001, ga102_disp_new },
2865	.fifo     = { 0x00000001, ga102_fifo_new },
2866};
2867
2868static const struct nvkm_device_chip
2869nv1b5_chipset = {
2870	.name = "GB205",
2871	.bar      = { 0x00000001, tu102_bar_new },
2872	.fb       = { 0x00000001, gb202_fb_new },
2873	.fsp      = { 0x00000001, gb202_fsp_new },
2874	.gsp      = { 0x00000001, gb202_gsp_new },
2875	.imem     = { 0x00000001, gh100_instmem_new },
2876	.mmu      = { 0x00000001, gh100_mmu_new },
2877	.pci      = { 0x00000001, gh100_pci_new },
2878	.timer    = { 0x00000001, gk20a_timer_new },
2879	.vfn      = { 0x00000001, ga100_vfn_new },
2880	.disp     = { 0x00000001, ga102_disp_new },
2881	.fifo     = { 0x00000001, ga102_fifo_new },
2882};
2883
2884static const struct nvkm_device_chip
2885nv1b6_chipset = {
2886	.name = "GB206",
2887	.bar      = { 0x00000001, tu102_bar_new },
2888	.fb       = { 0x00000001, gb202_fb_new },
2889	.fsp      = { 0x00000001, gb202_fsp_new },
2890	.gsp      = { 0x00000001, gb202_gsp_new },
2891	.imem     = { 0x00000001, gh100_instmem_new },
2892	.mmu      = { 0x00000001, gh100_mmu_new },
2893	.pci      = { 0x00000001, gh100_pci_new },
2894	.timer    = { 0x00000001, gk20a_timer_new },
2895	.vfn      = { 0x00000001, ga100_vfn_new },
2896	.disp     = { 0x00000001, ga102_disp_new },
2897	.fifo     = { 0x00000001, ga102_fifo_new },
2898};
2899
2900static const struct nvkm_device_chip
2901nv1b7_chipset = {
2902	.name = "GB207",
2903	.bar      = { 0x00000001, tu102_bar_new },
2904	.fb       = { 0x00000001, gb202_fb_new },
2905	.fsp      = { 0x00000001, gb202_fsp_new },
2906	.gsp      = { 0x00000001, gb202_gsp_new },
2907	.imem     = { 0x00000001, gh100_instmem_new },
2908	.mmu      = { 0x00000001, gh100_mmu_new },
2909	.pci      = { 0x00000001, gh100_pci_new },
2910	.timer    = { 0x00000001, gk20a_timer_new },
2911	.vfn      = { 0x00000001, ga100_vfn_new },
2912	.disp     = { 0x00000001, ga102_disp_new },
2913	.fifo     = { 0x00000001, ga102_fifo_new },
2914};
2915
2916struct nvkm_subdev *
2917nvkm_device_subdev(struct nvkm_device *device, int type, int inst)
2918{
2919	struct nvkm_subdev *subdev;
2920
2921	list_for_each_entry(subdev, &device->subdev, head) {
2922		if (subdev->type == type && subdev->inst == inst)
2923			return subdev;
2924	}
2925
2926	return NULL;
2927}
2928
2929struct nvkm_engine *
2930nvkm_device_engine(struct nvkm_device *device, int type, int inst)
2931{
2932	struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst);
2933	if (subdev && subdev->func == &nvkm_engine)
2934		return container_of(subdev, struct nvkm_engine, subdev);
2935	return NULL;
2936}
2937
2938int
2939nvkm_device_fini(struct nvkm_device *device, enum nvkm_suspend_state suspend)
2940{
2941	const char *action;
2942	struct nvkm_subdev *subdev;
2943	int ret;
2944	s64 time;
2945
2946	switch (suspend) {
2947	case NVKM_POWEROFF:
2948	default:
2949		action = "fini";
2950		break;
2951	case NVKM_SUSPEND:
2952		action = "suspend";
2953		break;
2954	case NVKM_RUNTIME_SUSPEND:
2955		action = "runtime";
2956		break;
2957	}
2958	nvdev_trace(device, "%s running...\n", action);
2959	time = ktime_to_us(ktime_get());
2960
2961	nvkm_acpi_fini(device);
2962
2963	list_for_each_entry_reverse(subdev, &device->subdev, head) {
2964		ret = nvkm_subdev_fini(subdev, suspend);
2965		if (ret && suspend)
2966			goto fail;
2967	}
2968
2969	nvkm_therm_clkgate_fini(device->therm, suspend);
2970
2971	if (device->func->fini)
2972		device->func->fini(device, suspend);
2973
2974	nvkm_intr_unarm(device);
2975
2976	time = ktime_to_us(ktime_get()) - time;
2977	nvdev_trace(device, "%s completed in %lldus...\n", action, time);
2978	return 0;
2979
2980fail:
2981	list_for_each_entry_from(subdev, &device->subdev, head) {
2982		int rret = nvkm_subdev_init(subdev);
2983		if (rret)
2984			nvkm_fatal(subdev, "failed restart, %d\n", ret);
2985	}
2986
2987	nvdev_trace(device, "%s failed with %d\n", action, ret);
2988	return ret;
2989}
2990
2991static int
2992nvkm_device_preinit(struct nvkm_device *device)
2993{
2994	struct nvkm_subdev *subdev;
2995	int ret;
2996	s64 time;
2997
2998	nvdev_trace(device, "preinit running...\n");
2999	time = ktime_to_us(ktime_get());
3000
3001	nvkm_intr_unarm(device);
3002
3003	if (device->func->preinit) {
3004		ret = device->func->preinit(device);
3005		if (ret)
3006			goto fail;
3007	}
3008
3009	list_for_each_entry(subdev, &device->subdev, head) {
3010		ret = nvkm_subdev_preinit(subdev);
3011		if (ret)
3012			goto fail;
3013	}
3014
3015	ret = nvkm_devinit_post(device->devinit);
3016	if (ret)
3017		goto fail;
3018
3019	ret = nvkm_top_parse(device);
3020	if (ret)
3021		goto fail;
3022
3023	ret = nvkm_fb_mem_unlock(device->fb);
3024	if (ret)
3025		goto fail;
3026
3027	time = ktime_to_us(ktime_get()) - time;
3028	nvdev_trace(device, "preinit completed in %lldus\n", time);
3029	return 0;
3030
3031fail:
3032	nvdev_error(device, "preinit failed with %d\n", ret);
3033	return ret;
3034}
3035
3036int
3037nvkm_device_init(struct nvkm_device *device)
3038{
3039	struct nvkm_subdev *subdev;
3040	int ret;
3041	s64 time;
3042
3043	ret = nvkm_device_preinit(device);
3044	if (ret)
3045		return ret;
3046
3047	nvkm_device_fini(device, NVKM_POWEROFF);
3048
3049	nvdev_trace(device, "init running...\n");
3050	time = ktime_to_us(ktime_get());
3051
3052	nvkm_intr_rearm(device);
3053
3054	if (device->func->init) {
3055		ret = device->func->init(device);
3056		if (ret)
3057			goto fail;
3058	}
3059
3060	list_for_each_entry(subdev, &device->subdev, head) {
3061		ret = nvkm_subdev_init(subdev);
3062		if (ret)
3063			goto fail_subdev;
3064	}
3065
3066	nvkm_acpi_init(device);
3067	nvkm_therm_clkgate_enable(device->therm);
3068
3069	time = ktime_to_us(ktime_get()) - time;
3070	nvdev_trace(device, "init completed in %lldus\n", time);
3071	return 0;
3072
3073fail_subdev:
3074	list_for_each_entry_from(subdev, &device->subdev, head)
3075		nvkm_subdev_fini(subdev, NVKM_POWEROFF);
3076fail:
3077	nvkm_device_fini(device, NVKM_POWEROFF);
3078
3079	nvdev_error(device, "init failed with %d\n", ret);
3080	return ret;
3081}
3082
3083void
3084nvkm_device_del(struct nvkm_device **pdevice)
3085{
3086	struct nvkm_device *device = *pdevice;
3087	struct nvkm_subdev *subdev, *subtmp;
3088	if (device) {
3089		mutex_lock(&nv_devices_mutex);
3090
3091		nvkm_intr_dtor(device);
3092
3093		list_for_each_entry_safe_reverse(subdev, subtmp, &device->subdev, head)
3094			nvkm_subdev_del(&subdev);
3095
3096		if (device->pri)
3097			iounmap(device->pri);
3098		list_del(&device->head);
3099
3100		if (device->func->dtor)
3101			*pdevice = device->func->dtor(device);
3102		mutex_unlock(&nv_devices_mutex);
3103
3104		kfree(*pdevice);
3105		*pdevice = NULL;
3106	}
3107}
3108
3109/* returns true if the GPU is in the CPU native byte order */
3110static inline bool
3111nvkm_device_endianness(struct nvkm_device *device)
3112{
3113#ifdef __BIG_ENDIAN
3114	const bool big_endian = true;
3115#else
3116	const bool big_endian = false;
3117#endif
3118
3119	/* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it
3120	 * doesn't contain the expected values.
3121	 */
3122	u32 pmc_boot_1 = nvkm_rd32(device, 0x000004);
3123	if (pmc_boot_1 && pmc_boot_1 != 0x01000001)
3124		return !big_endian; /* Assume GPU is LE in this case. */
3125
3126	/* 0 means LE and 0x01000001 means BE GPU. Condition is true when
3127	 * GPU/CPU endianness don't match.
3128	 */
3129	if (big_endian == !pmc_boot_1) {
3130		nvkm_wr32(device, 0x000004, 0x01000001);
3131		nvkm_rd32(device, 0x000000);
3132		if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000))
3133			return !big_endian; /* Assume GPU is LE on any unexpected read-back. */
3134	}
3135
3136	/* CPU/GPU endianness should (hopefully) match. */
3137	return true;
3138}
3139
3140int
3141nvkm_device_ctor(const struct nvkm_device_func *func,
3142		 const struct nvkm_device_quirk *quirk,
3143		 struct device *dev, enum nvkm_device_type type, u64 handle,
3144		 const char *name, const char *cfg, const char *dbg,
3145		 struct nvkm_device *device)
3146{
3147	struct nvkm_subdev *subdev;
3148	u64 mmio_base, mmio_size;
3149	u32 boot0, boot1, strap;
3150	int ret = -EEXIST, j;
3151	unsigned chipset;
3152
3153	mutex_lock(&nv_devices_mutex);
3154	if (nvkm_device_find_locked(handle))
3155		goto done;
3156
3157	device->func = func;
3158	device->quirk = quirk;
3159	device->dev = dev;
3160	device->type = type;
3161	device->handle = handle;
3162	device->cfgopt = cfg;
3163	device->dbgopt = dbg;
3164	device->name = name;
3165	list_add_tail(&device->head, &nv_devices);
3166	device->debug = nvkm_dbgopt(device->dbgopt, "device");
3167	INIT_LIST_HEAD(&device->subdev);
3168
3169	mmio_base = device->func->resource_addr(device, NVKM_BAR0_PRI);
3170	mmio_size = device->func->resource_size(device, NVKM_BAR0_PRI);
3171
3172	device->pri = ioremap(mmio_base, mmio_size);
3173	if (device->pri == NULL) {
3174		nvdev_error(device, "unable to map PRI\n");
3175		ret = -ENOMEM;
3176		goto done;
3177	}
3178
3179	/* identify the chipset, and determine classes of subdev/engines */
3180
3181	/* switch mmio to cpu's native endianness */
3182	if (!nvkm_device_endianness(device)) {
3183		nvdev_error(device,
3184			    "Couldn't switch GPU to CPUs endianness\n");
3185		ret = -ENOSYS;
3186		goto done;
3187	}
3188
3189	boot0 = nvkm_rd32(device, 0x000000);
3190
3191	/* chipset can be overridden for devel/testing purposes */
3192	chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0);
3193	if (chipset) {
3194		u32 override_boot0;
3195
3196		if (chipset >= 0x10) {
3197			override_boot0  = ((chipset & 0x1ff) << 20);
3198			override_boot0 |= 0x000000a1;
3199		} else {
3200			if (chipset != 0x04)
3201				override_boot0 = 0x20104000;
3202			else
3203				override_boot0 = 0x20004000;
3204		}
3205
3206		nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n",
3207			   boot0, override_boot0);
3208		boot0 = override_boot0;
3209	}
3210
3211	/* determine chipset and derive architecture from it */
3212	if ((boot0 & 0x1f000000) > 0) {
3213		device->chipset = (boot0 & 0x1ff00000) >> 20;
3214		device->chiprev = (boot0 & 0x000000ff);
3215		switch (device->chipset & 0x1f0) {
3216		case 0x010: {
3217			if (0x461 & (1 << (device->chipset & 0xf)))
3218				device->card_type = NV_10;
3219			else
3220				device->card_type = NV_11;
3221			device->chiprev = 0x00;
3222			break;
3223		}
3224		case 0x020: device->card_type = NV_20; break;
3225		case 0x030: device->card_type = NV_30; break;
3226		case 0x040:
3227		case 0x060: device->card_type = NV_40; break;
3228		case 0x050:
3229		case 0x080:
3230		case 0x090:
3231		case 0x0a0: device->card_type = NV_50; break;
3232		case 0x0c0:
3233		case 0x0d0: device->card_type = NV_C0; break;
3234		case 0x0e0:
3235		case 0x0f0:
3236		case 0x100: device->card_type = NV_E0; break;
3237		case 0x110:
3238		case 0x120: device->card_type = GM100; break;
3239		case 0x130: device->card_type = GP100; break;
3240		case 0x140: device->card_type = GV100; break;
3241		case 0x160: device->card_type = TU100; break;
3242		case 0x170: device->card_type = GA100; break;
3243		case 0x180: device->card_type = GH100; break;
3244		case 0x190: device->card_type = AD100; break;
3245		case 0x1a0: device->card_type = GB10x; break;
3246		case 0x1b0: device->card_type = GB20x; break;
3247		default:
3248			break;
3249		}
3250	} else
3251	if ((boot0 & 0xff00fff0) == 0x20004000) {
3252		if (boot0 & 0x00f00000)
3253			device->chipset = 0x05;
3254		else
3255			device->chipset = 0x04;
3256		device->card_type = NV_04;
3257	}
3258
3259	switch (device->chipset) {
3260	case 0x004: device->chip = &nv4_chipset; break;
3261	case 0x005: device->chip = &nv5_chipset; break;
3262	case 0x010: device->chip = &nv10_chipset; break;
3263	case 0x011: device->chip = &nv11_chipset; break;
3264	case 0x015: device->chip = &nv15_chipset; break;
3265	case 0x017: device->chip = &nv17_chipset; break;
3266	case 0x018: device->chip = &nv18_chipset; break;
3267	case 0x01a: device->chip = &nv1a_chipset; break;
3268	case 0x01f: device->chip = &nv1f_chipset; break;
3269	case 0x020: device->chip = &nv20_chipset; break;
3270	case 0x025: device->chip = &nv25_chipset; break;
3271	case 0x028: device->chip = &nv28_chipset; break;
3272	case 0x02a: device->chip = &nv2a_chipset; break;
3273	case 0x030: device->chip = &nv30_chipset; break;
3274	case 0x031: device->chip = &nv31_chipset; break;
3275	case 0x034: device->chip = &nv34_chipset; break;
3276	case 0x035: device->chip = &nv35_chipset; break;
3277	case 0x036: device->chip = &nv36_chipset; break;
3278	case 0x040: device->chip = &nv40_chipset; break;
3279	case 0x041: device->chip = &nv41_chipset; break;
3280	case 0x042: device->chip = &nv42_chipset; break;
3281	case 0x043: device->chip = &nv43_chipset; break;
3282	case 0x044: device->chip = &nv44_chipset; break;
3283	case 0x045: device->chip = &nv45_chipset; break;
3284	case 0x046: device->chip = &nv46_chipset; break;
3285	case 0x047: device->chip = &nv47_chipset; break;
3286	case 0x049: device->chip = &nv49_chipset; break;
3287	case 0x04a: device->chip = &nv4a_chipset; break;
3288	case 0x04b: device->chip = &nv4b_chipset; break;
3289	case 0x04c: device->chip = &nv4c_chipset; break;
3290	case 0x04e: device->chip = &nv4e_chipset; break;
3291	case 0x050: device->chip = &nv50_chipset; break;
3292	case 0x063: device->chip = &nv63_chipset; break;
3293	case 0x067: device->chip = &nv67_chipset; break;
3294	case 0x068: device->chip = &nv68_chipset; break;
3295	case 0x084: device->chip = &nv84_chipset; break;
3296	case 0x086: device->chip = &nv86_chipset; break;
3297	case 0x092: device->chip = &nv92_chipset; break;
3298	case 0x094: device->chip = &nv94_chipset; break;
3299	case 0x096: device->chip = &nv96_chipset; break;
3300	case 0x098: device->chip = &nv98_chipset; break;
3301	case 0x0a0: device->chip = &nva0_chipset; break;
3302	case 0x0a3: device->chip = &nva3_chipset; break;
3303	case 0x0a5: device->chip = &nva5_chipset; break;
3304	case 0x0a8: device->chip = &nva8_chipset; break;
3305	case 0x0aa: device->chip = &nvaa_chipset; break;
3306	case 0x0ac: device->chip = &nvac_chipset; break;
3307	case 0x0af: device->chip = &nvaf_chipset; break;
3308	case 0x0c0: device->chip = &nvc0_chipset; break;
3309	case 0x0c1: device->chip = &nvc1_chipset; break;
3310	case 0x0c3: device->chip = &nvc3_chipset; break;
3311	case 0x0c4: device->chip = &nvc4_chipset; break;
3312	case 0x0c8: device->chip = &nvc8_chipset; break;
3313	case 0x0ce: device->chip = &nvce_chipset; break;
3314	case 0x0cf: device->chip = &nvcf_chipset; break;
3315	case 0x0d7: device->chip = &nvd7_chipset; break;
3316	case 0x0d9: device->chip = &nvd9_chipset; break;
3317	case 0x0e4: device->chip = &nve4_chipset; break;
3318	case 0x0e6: device->chip = &nve6_chipset; break;
3319	case 0x0e7: device->chip = &nve7_chipset; break;
3320	case 0x0ea: device->chip = &nvea_chipset; break;
3321	case 0x0f0: device->chip = &nvf0_chipset; break;
3322	case 0x0f1: device->chip = &nvf1_chipset; break;
3323	case 0x106: device->chip = &nv106_chipset; break;
3324	case 0x108: device->chip = &nv108_chipset; break;
3325	case 0x117: device->chip = &nv117_chipset; break;
3326	case 0x118: device->chip = &nv118_chipset; break;
3327	case 0x120: device->chip = &nv120_chipset; break;
3328	case 0x124: device->chip = &nv124_chipset; break;
3329	case 0x126: device->chip = &nv126_chipset; break;
3330	case 0x12b: device->chip = &nv12b_chipset; break;
3331	case 0x130: device->chip = &nv130_chipset; break;
3332	case 0x132: device->chip = &nv132_chipset; break;
3333	case 0x134: device->chip = &nv134_chipset; break;
3334	case 0x136: device->chip = &nv136_chipset; break;
3335	case 0x137: device->chip = &nv137_chipset; break;
3336	case 0x138: device->chip = &nv138_chipset; break;
3337	case 0x13b: device->chip = &nv13b_chipset; break;
3338	case 0x140: device->chip = &nv140_chipset; break;
3339	case 0x162: device->chip = &nv162_chipset; break;
3340	case 0x164: device->chip = &nv164_chipset; break;
3341	case 0x166: device->chip = &nv166_chipset; break;
3342	case 0x167: device->chip = &nv167_chipset; break;
3343	case 0x168: device->chip = &nv168_chipset; break;
3344	case 0x172: device->chip = &nv172_chipset; break;
3345	case 0x173: device->chip = &nv173_chipset; break;
3346	case 0x174: device->chip = &nv174_chipset; break;
3347	case 0x176: device->chip = &nv176_chipset; break;
3348	case 0x177: device->chip = &nv177_chipset; break;
3349	case 0x180: device->chip = &nv180_chipset; break;
3350	case 0x192: device->chip = &nv192_chipset; break;
3351	case 0x193: device->chip = &nv193_chipset; break;
3352	case 0x194: device->chip = &nv194_chipset; break;
3353	case 0x196: device->chip = &nv196_chipset; break;
3354	case 0x197: device->chip = &nv197_chipset; break;
3355	case 0x1a0: device->chip = &nv1a0_chipset; break;
3356	case 0x1a2: device->chip = &nv1a2_chipset; break;
3357	case 0x1b2: device->chip = &nv1b2_chipset; break;
3358	case 0x1b3: device->chip = &nv1b3_chipset; break;
3359	case 0x1b5: device->chip = &nv1b5_chipset; break;
3360	case 0x1b6: device->chip = &nv1b6_chipset; break;
3361	case 0x1b7: device->chip = &nv1b7_chipset; break;
3362	default:
3363		if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
3364			switch (device->chipset) {
3365			case 0x170: device->chip = &nv170_chipset; break;
3366			default:
3367				break;
3368			}
3369		}
3370
3371		if (!device->chip) {
3372			nvdev_error(device, "unknown chipset (%08x)\n", boot0);
3373			ret = -ENODEV;
3374			goto done;
3375		}
3376		break;
3377	}
3378
3379	nvdev_info(device, "NVIDIA %s (%08x)\n",
3380		   device->chip->name, boot0);
3381
3382	/* vGPU detection */
3383	boot1 = nvkm_rd32(device, 0x0000004);
3384	if (device->card_type >= TU100 && (boot1 & 0x00030000)) {
3385		nvdev_info(device, "vGPUs are not supported\n");
3386		ret = -ENODEV;
3387		goto done;
3388	}
3389
3390	/* read strapping information */
3391	strap = nvkm_rd32(device, 0x101000);
3392
3393	/* determine frequency of timing crystal */
3394	if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
3395	    (device->chipset >= 0x20 && device->chipset < 0x25))
3396		strap &= 0x00000040;
3397	else
3398		strap &= 0x00400040;
3399
3400	switch (strap) {
3401	case 0x00000000: device->crystal = 13500; break;
3402	case 0x00000040: device->crystal = 14318; break;
3403	case 0x00400000: device->crystal = 27000; break;
3404	case 0x00400040: device->crystal = 25000; break;
3405	}
3406
3407	if (!device->name)
3408		device->name = device->chip->name;
3409
3410	mutex_init(&device->mutex);
3411	nvkm_intr_ctor(device);
3412
3413#define NVKM_LAYOUT_ONCE(type,data,ptr)                                                      \
3414	if (device->chip->ptr.inst) {                                                        \
3415		WARN_ON(device->chip->ptr.inst != 0x00000001);                               \
3416		ret = device->chip->ptr.ctor(device, (type), -1, &device->ptr);              \
3417		subdev = nvkm_device_subdev(device, (type), 0);                              \
3418		if (ret) {                                                                   \
3419			nvkm_subdev_del(&subdev);                                            \
3420			device->ptr = NULL;                                                  \
3421			if (ret != -ENODEV) {                                                \
3422				nvdev_error(device, "%s ctor failed: %d\n",                  \
3423					    nvkm_subdev_type[(type)], ret);                  \
3424				goto done;                                                   \
3425			}                                                                    \
3426		} else {                                                                     \
3427			subdev->pself = (void **)&device->ptr;                               \
3428		}                                                                            \
3429	}
3430#define NVKM_LAYOUT_INST(type,data,ptr,cnt)                                                  \
3431	WARN_ON(device->chip->ptr.inst & ~((1 << ARRAY_SIZE(device->ptr)) - 1));             \
3432	for (j = 0; device->chip->ptr.inst && j < ARRAY_SIZE(device->ptr); j++) {            \
3433		if (device->chip->ptr.inst & BIT(j)) {                                       \
3434			ret = device->chip->ptr.ctor(device, (type), (j), &device->ptr[j]);  \
3435			subdev = nvkm_device_subdev(device, (type), (j));                    \
3436			if (ret) {                                                           \
3437				nvkm_subdev_del(&subdev);                                    \
3438				device->ptr[j] = NULL;                                       \
3439				if (ret != -ENODEV) {                                        \
3440					nvdev_error(device, "%s%d ctor failed: %d\n",        \
3441						    nvkm_subdev_type[(type)], (j), ret);     \
3442					goto done;                                           \
3443				}                                                            \
3444			} else {                                                             \
3445				subdev->pself = (void **)&device->ptr[j];                    \
3446			}                                                                    \
3447		}                                                                            \
3448	}
3449#include <core/layout.h>
3450#undef NVKM_LAYOUT_INST
3451#undef NVKM_LAYOUT_ONCE
3452
3453	ret = nvkm_intr_install(device);
3454done:
3455	if (ret && device->pri) {
3456		iounmap(device->pri);
3457		device->pri = NULL;
3458	}
3459	mutex_unlock(&nv_devices_mutex);
3460	return ret;
3461}