nouveau_drm.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include <linux/aperture.h>
  26#include <linux/delay.h>
  27#include <linux/module.h>
  28#include <linux/pci.h>
  29#include <linux/pm_runtime.h>
  30#include <linux/vga_switcheroo.h>
  31#include <linux/mmu_notifier.h>
  32#include <linux/dynamic_debug.h>
  33#include <linux/debugfs.h>
  34
  35#include <drm/clients/drm_client_setup.h>
  36#include <drm/drm_drv.h>
  37#include <drm/drm_fbdev_ttm.h>
  38#include <drm/drm_gem_ttm_helper.h>
  39#include <drm/drm_ioctl.h>
  40#include <drm/drm_vblank.h>
  41
  42#include <core/gpuobj.h>
  43#include <core/option.h>
  44#include <core/pci.h>
  45#include <core/tegra.h>
  46
  47#include <nvif/driver.h>
  48#include <nvif/fifo.h>
  49#include <nvif/push006c.h>
  50#include <nvif/user.h>
  51#include <nvif/log.h>
  52
  53#include <nvif/class.h>
  54#include <nvif/cl0002.h>
  55
  56#include "nouveau_drv.h"
  57#include "nouveau_dma.h"
  58#include "nouveau_ttm.h"
  59#include "nouveau_gem.h"
  60#include "nouveau_vga.h"
  61#include "nouveau_led.h"
  62#include "nouveau_hwmon.h"
  63#include "nouveau_acpi.h"
  64#include "nouveau_bios.h"
  65#include "nouveau_ioctl.h"
  66#include "nouveau_abi16.h"
  67#include "nouveau_fence.h"
  68#include "nouveau_debugfs.h"
  69#include "nouveau_connector.h"
  70#include "nouveau_platform.h"
  71#include "nouveau_svm.h"
  72#include "nouveau_dmem.h"
  73#include "nouveau_exec.h"
  74#include "nouveau_uvmm.h"
  75#include "nouveau_sched.h"
  76
  77DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
  78			"DRM_UT_CORE",
  79			"DRM_UT_DRIVER",
  80			"DRM_UT_KMS",
  81			"DRM_UT_PRIME",
  82			"DRM_UT_ATOMIC",
  83			"DRM_UT_VBL",
  84			"DRM_UT_STATE",
  85			"DRM_UT_LEASE",
  86			"DRM_UT_DP",
  87			"DRM_UT_DRMRES");
  88
  89MODULE_PARM_DESC(config, "option string to pass to driver core");
  90static char *nouveau_config;
  91module_param_named(config, nouveau_config, charp, 0400);
  92
  93MODULE_PARM_DESC(debug, "debug string to pass to driver core");
  94static char *nouveau_debug;
  95module_param_named(debug, nouveau_debug, charp, 0400);
  96
  97MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
  98static int nouveau_noaccel = 0;
  99module_param_named(noaccel, nouveau_noaccel, int, 0400);
 100
 101MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
 102		          "0 = disabled, 1 = enabled, 2 = headless)");
 103int nouveau_modeset = -1;
 104module_param_named(modeset, nouveau_modeset, int, 0400);
 105
 106MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
 107static int nouveau_atomic = 0;
 108module_param_named(atomic, nouveau_atomic, int, 0400);
 109
 110MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
 111static int nouveau_runtime_pm = -1;
 112module_param_named(runpm, nouveau_runtime_pm, int, 0400);
 113
 114static struct drm_driver driver_stub;
 115static struct drm_driver driver_pci;
 116static struct drm_driver driver_platform;
 117
 118#ifdef CONFIG_DEBUG_FS
 119struct dentry *nouveau_debugfs_root;
 120
 121/*
 122 * gsp_logs - list of nvif_log GSP-RM logging buffers
 123 *
 124 * Head pointer to a a list of nvif_log buffers that is created for each GPU
 125 * upon GSP shutdown if the "keep_gsp_logging" command-line parameter is
 126 * specified. This is used to track the alternative debugfs entries for the
 127 * GSP-RM logs.
 128 */
 129NVIF_LOGS_DECLARE(gsp_logs);
 130#endif
 131
 132static u64
 133nouveau_pci_name(struct pci_dev *pdev)
 134{
 135	u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
 136	name |= pdev->bus->number << 16;
 137	name |= PCI_SLOT(pdev->devfn) << 8;
 138	return name | PCI_FUNC(pdev->devfn);
 139}
 140
 141static u64
 142nouveau_platform_name(struct platform_device *platformdev)
 143{
 144	return platformdev->id;
 145}
 146
 147static u64
 148nouveau_name(struct drm_device *dev)
 149{
 150	if (dev_is_pci(dev->dev))
 151		return nouveau_pci_name(to_pci_dev(dev->dev));
 152	else
 153		return nouveau_platform_name(to_platform_device(dev->dev));
 154}
 155
 156static inline bool
 157nouveau_cli_work_ready(struct dma_fence *fence)
 158{
 159	bool ret = true;
 160
 161	spin_lock_irq(fence->lock);
 162	if (!dma_fence_is_signaled_locked(fence))
 163		ret = false;
 164	spin_unlock_irq(fence->lock);
 165
 166	if (ret == true)
 167		dma_fence_put(fence);
 168	return ret;
 169}
 170
 171static void
 172nouveau_cli_work(struct work_struct *w)
 173{
 174	struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
 175	struct nouveau_cli_work *work, *wtmp;
 176	mutex_lock(&cli->lock);
 177	list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
 178		if (!work->fence || nouveau_cli_work_ready(work->fence)) {
 179			list_del(&work->head);
 180			work->func(work);
 181		}
 182	}
 183	mutex_unlock(&cli->lock);
 184}
 185
 186static void
 187nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
 188{
 189	struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
 190	schedule_work(&work->cli->work);
 191}
 192
 193void
 194nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
 195		       struct nouveau_cli_work *work)
 196{
 197	work->fence = dma_fence_get(fence);
 198	work->cli = cli;
 199	mutex_lock(&cli->lock);
 200	list_add_tail(&work->head, &cli->worker);
 201	if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
 202		nouveau_cli_work_fence(fence, &work->cb);
 203	mutex_unlock(&cli->lock);
 204}
 205
 206static void
 207nouveau_cli_fini(struct nouveau_cli *cli)
 208{
 209	struct nouveau_uvmm *uvmm = nouveau_cli_uvmm_locked(cli);
 210
 211	/* All our channels are dead now, which means all the fences they
 212	 * own are signalled, and all callback functions have been called.
 213	 *
 214	 * So, after flushing the workqueue, there should be nothing left.
 215	 */
 216	flush_work(&cli->work);
 217	WARN_ON(!list_empty(&cli->worker));
 218
 219	if (cli->sched)
 220		nouveau_sched_destroy(&cli->sched);
 221	if (uvmm)
 222		nouveau_uvmm_fini(uvmm);
 223	nouveau_vmm_fini(&cli->svm);
 224	nouveau_vmm_fini(&cli->vmm);
 225	nvif_mmu_dtor(&cli->mmu);
 226	cli->device.object.map.ptr = NULL;
 227	nvif_device_dtor(&cli->device);
 228	mutex_lock(&cli->drm->client_mutex);
 229	nvif_client_dtor(&cli->base);
 230	mutex_unlock(&cli->drm->client_mutex);
 231}
 232
 233static int
 234nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
 235		 struct nouveau_cli *cli)
 236{
 237	static const struct nvif_mclass
 238	mems[] = {
 239		{ NVIF_CLASS_MEM_GF100, -1 },
 240		{ NVIF_CLASS_MEM_NV50 , -1 },
 241		{ NVIF_CLASS_MEM_NV04 , -1 },
 242		{}
 243	};
 244	static const struct nvif_mclass
 245	vmms[] = {
 246		{ NVIF_CLASS_VMM_GP100, -1 },
 247		{ NVIF_CLASS_VMM_GM200, -1 },
 248		{ NVIF_CLASS_VMM_GF100, -1 },
 249		{ NVIF_CLASS_VMM_NV50 , -1 },
 250		{ NVIF_CLASS_VMM_NV04 , -1 },
 251		{}
 252	};
 253	int ret;
 254
 255	snprintf(cli->name, sizeof(cli->name), "%s", sname);
 256	cli->drm = drm;
 257	mutex_init(&cli->mutex);
 258
 259	INIT_WORK(&cli->work, nouveau_cli_work);
 260	INIT_LIST_HEAD(&cli->worker);
 261	mutex_init(&cli->lock);
 262
 263	mutex_lock(&drm->client_mutex);
 264	ret = nvif_client_ctor(&drm->_client, cli->name, &cli->base);
 265	mutex_unlock(&drm->client_mutex);
 266	if (ret) {
 267		NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
 268		goto done;
 269	}
 270
 271	ret = nvif_device_ctor(&cli->base, "drmDevice", &cli->device);
 272	if (ret) {
 273		NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
 274		goto done;
 275	}
 276
 277	cli->device.object.map.ptr = drm->device.object.map.ptr;
 278
 279	ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", drm->mmu.object.oclass,
 280			    &cli->mmu);
 281	if (ret) {
 282		NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
 283		goto done;
 284	}
 285
 286	ret = nvif_mclass(&cli->mmu.object, vmms);
 287	if (ret < 0) {
 288		NV_PRINTK(err, cli, "No supported VMM class\n");
 289		goto done;
 290	}
 291
 292	ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
 293	if (ret) {
 294		NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
 295		goto done;
 296	}
 297
 298	ret = nvif_mclass(&cli->mmu.object, mems);
 299	if (ret < 0) {
 300		NV_PRINTK(err, cli, "No supported MEM class\n");
 301		goto done;
 302	}
 303
 304	cli->mem = &mems[ret];
 305
 306	/* Don't pass in the (shared) sched_wq in order to let
 307	 * nouveau_sched_create() create a dedicated one for VM_BIND jobs.
 308	 *
 309	 * This is required to ensure that for VM_BIND jobs free_job() work and
 310	 * run_job() work can always run concurrently and hence, free_job() work
 311	 * can never stall run_job() work. For EXEC jobs we don't have this
 312	 * requirement, since EXEC job's free_job() does not require to take any
 313	 * locks which indirectly or directly are held for allocations
 314	 * elsewhere.
 315	 */
 316	ret = nouveau_sched_create(&cli->sched, drm, NULL, 1);
 317	if (ret)
 318		goto done;
 319
 320	return 0;
 321done:
 322	if (ret)
 323		nouveau_cli_fini(cli);
 324	return ret;
 325}
 326
 327static void
 328nouveau_accel_ce_fini(struct nouveau_drm *drm)
 329{
 330	nouveau_channel_idle(drm->cechan);
 331	nvif_object_dtor(&drm->ttm.copy);
 332	nouveau_channel_del(&drm->cechan);
 333}
 334
 335static void
 336nouveau_accel_ce_init(struct nouveau_drm *drm)
 337{
 338	struct nvif_device *device = &drm->client.device;
 339	u64 runm;
 340	int ret = 0;
 341
 342	/* Allocate channel that has access to a (preferably async) copy
 343	 * engine, to use for TTM buffer moves.
 344	 */
 345	runm = nvif_fifo_runlist_ce(device);
 346	if (!runm) {
 347		NV_DEBUG(drm, "no ce runlist\n");
 348		return;
 349	}
 350
 351	ret = nouveau_channel_new(&drm->client, true, runm, NvDmaFB, NvDmaTT, &drm->cechan);
 352	if (ret)
 353		NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
 354}
 355
 356static void
 357nouveau_accel_gr_fini(struct nouveau_drm *drm)
 358{
 359	nouveau_channel_idle(drm->channel);
 360	nvif_object_dtor(&drm->ntfy);
 361	nvkm_gpuobj_del(&drm->notify);
 362	nouveau_channel_del(&drm->channel);
 363}
 364
 365static void
 366nouveau_accel_gr_init(struct nouveau_drm *drm)
 367{
 368	struct nvif_device *device = &drm->client.device;
 369	u64 runm;
 370	int ret;
 371
 372	/* Allocate channel that has access to the graphics engine. */
 373	runm = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
 374	if (!runm) {
 375		NV_DEBUG(drm, "no gr runlist\n");
 376		return;
 377	}
 378
 379	ret = nouveau_channel_new(&drm->client, false, runm, NvDmaFB, NvDmaTT, &drm->channel);
 380	if (ret) {
 381		NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
 382		nouveau_accel_gr_fini(drm);
 383		return;
 384	}
 385
 386	/* A SW class is used on pre-NV50 HW to assist with handling the
 387	 * synchronisation of page flips, as well as to implement fences
 388	 * on TNT/TNT2 HW that lacks any kind of support in host.
 389	 */
 390	if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 391		ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
 392				       NVDRM_NVSW, nouveau_abi16_swclass(drm),
 393				       NULL, 0, &drm->channel->nvsw);
 394
 395		if (ret == 0 && device->info.chipset >= 0x11) {
 396			ret = nvif_object_ctor(&drm->channel->user, "drmBlit",
 397					       0x005f, 0x009f,
 398					       NULL, 0, &drm->channel->blit);
 399		}
 400
 401		if (ret == 0) {
 402			struct nvif_push *push = &drm->channel->chan.push;
 403
 404			ret = PUSH_WAIT(push, 8);
 405			if (ret == 0) {
 406				if (device->info.chipset >= 0x11) {
 407					PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);
 408					PUSH_NVSQ(push, NV09F, 0x0120, 0,
 409							       0x0124, 1,
 410							       0x0128, 2);
 411				}
 412				PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
 413			}
 414		}
 415
 416		if (ret) {
 417			NV_ERROR(drm, "failed to allocate sw or blit class, %d\n", ret);
 418			nouveau_accel_gr_fini(drm);
 419			return;
 420		}
 421	}
 422
 423	/* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
 424	 * even if notification is never requested, so, allocate a ctxdma on
 425	 * any GPU where it's possible we'll end up using M2MF for BO moves.
 426	 */
 427	if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
 428		ret = nvkm_gpuobj_new(nvxx_device(drm), 32, 0, false, NULL, &drm->notify);
 429		if (ret) {
 430			NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
 431			nouveau_accel_gr_fini(drm);
 432			return;
 433		}
 434
 435		ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
 436				       NvNotify0, NV_DMA_IN_MEMORY,
 437				       &(struct nv_dma_v0) {
 438						.target = NV_DMA_V0_TARGET_VRAM,
 439						.access = NV_DMA_V0_ACCESS_RDWR,
 440						.start = drm->notify->addr,
 441						.limit = drm->notify->addr + 31
 442				       }, sizeof(struct nv_dma_v0),
 443				       &drm->ntfy);
 444		if (ret) {
 445			nouveau_accel_gr_fini(drm);
 446			return;
 447		}
 448	}
 449}
 450
 451static void
 452nouveau_accel_fini(struct nouveau_drm *drm)
 453{
 454	nouveau_accel_ce_fini(drm);
 455	nouveau_accel_gr_fini(drm);
 456	if (drm->fence)
 457		nouveau_fence(drm)->dtor(drm);
 458	nouveau_channels_fini(drm);
 459}
 460
 461static void
 462nouveau_accel_init(struct nouveau_drm *drm)
 463{
 464	struct nvif_device *device = &drm->client.device;
 465	struct nvif_sclass *sclass;
 466	int ret, i, n;
 467
 468	if (nouveau_noaccel)
 469		return;
 470
 471	/* Initialise global support for channels, and synchronisation. */
 472	ret = nouveau_channels_init(drm);
 473	if (ret)
 474		return;
 475
 476	/*XXX: this is crap, but the fence/channel stuff is a little
 477	 *     backwards in some places.  this will be fixed.
 478	 */
 479	ret = n = nvif_object_sclass_get(&device->object, &sclass);
 480	if (ret < 0)
 481		return;
 482
 483	for (ret = -ENOSYS, i = 0; i < n; i++) {
 484		switch (sclass[i].oclass) {
 485		case NV03_CHANNEL_DMA:
 486			ret = nv04_fence_create(drm);
 487			break;
 488		case NV10_CHANNEL_DMA:
 489			ret = nv10_fence_create(drm);
 490			break;
 491		case NV17_CHANNEL_DMA:
 492		case NV40_CHANNEL_DMA:
 493			ret = nv17_fence_create(drm);
 494			break;
 495		case NV50_CHANNEL_GPFIFO:
 496			ret = nv50_fence_create(drm);
 497			break;
 498		case G82_CHANNEL_GPFIFO:
 499			ret = nv84_fence_create(drm);
 500			break;
 501		case FERMI_CHANNEL_GPFIFO:
 502		case KEPLER_CHANNEL_GPFIFO_A:
 503		case KEPLER_CHANNEL_GPFIFO_B:
 504		case MAXWELL_CHANNEL_GPFIFO_A:
 505		case PASCAL_CHANNEL_GPFIFO_A:
 506			ret = nvc0_fence_create(drm);
 507			break;
 508		case VOLTA_CHANNEL_GPFIFO_A:
 509		case TURING_CHANNEL_GPFIFO_A:
 510		case AMPERE_CHANNEL_GPFIFO_A:
 511		case AMPERE_CHANNEL_GPFIFO_B:
 512		case HOPPER_CHANNEL_GPFIFO_A:
 513		case BLACKWELL_CHANNEL_GPFIFO_A:
 514		case BLACKWELL_CHANNEL_GPFIFO_B:
 515			ret = gv100_fence_create(drm);
 516			break;
 517		default:
 518			break;
 519		}
 520	}
 521
 522	nvif_object_sclass_put(&sclass);
 523	if (ret) {
 524		NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
 525		nouveau_accel_fini(drm);
 526		return;
 527	}
 528
 529	/* Volta requires access to a doorbell register for kickoff. */
 530	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
 531		ret = nvif_user_ctor(device, "drmUsermode");
 532		if (ret)
 533			return;
 534	}
 535
 536	/* Allocate channels we need to support various functions. */
 537	nouveau_accel_gr_init(drm);
 538	nouveau_accel_ce_init(drm);
 539
 540	/* Initialise accelerated TTM buffer moves. */
 541	nouveau_bo_move_init(drm);
 542}
 543
 544static void __printf(2, 3)
 545nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
 546{
 547	struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
 548	struct va_format vaf;
 549	va_list va;
 550
 551	va_start(va, fmt);
 552	vaf.fmt = fmt;
 553	vaf.va = &va;
 554	NV_ERROR(drm, "%pV", &vaf);
 555	va_end(va);
 556}
 557
 558static void __printf(2, 3)
 559nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
 560{
 561	struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
 562	struct va_format vaf;
 563	va_list va;
 564
 565	va_start(va, fmt);
 566	vaf.fmt = fmt;
 567	vaf.va = &va;
 568	NV_DEBUG(drm, "%pV", &vaf);
 569	va_end(va);
 570}
 571
 572static const struct nvif_parent_func
 573nouveau_parent = {
 574	.debugf = nouveau_drm_debugf,
 575	.errorf = nouveau_drm_errorf,
 576};
 577
 578static void
 579nouveau_drm_device_fini(struct nouveau_drm *drm)
 580{
 581	struct drm_device *dev = drm->dev;
 582	struct nouveau_cli *cli, *temp_cli;
 583
 584	if (nouveau_pmops_runtime()) {
 585		pm_runtime_get_sync(dev->dev);
 586		pm_runtime_forbid(dev->dev);
 587	}
 588
 589	nouveau_led_fini(dev);
 590	nouveau_dmem_fini(drm);
 591	nouveau_svm_fini(drm);
 592	nouveau_hwmon_fini(dev);
 593	nouveau_debugfs_fini(drm);
 594
 595	if (dev->mode_config.num_crtc)
 596		nouveau_display_fini(dev, false, false);
 597	nouveau_display_destroy(dev);
 598
 599	nouveau_accel_fini(drm);
 600	nouveau_bios_takedown(dev);
 601
 602	nouveau_ttm_fini(drm);
 603	nouveau_vga_fini(drm);
 604
 605	/*
 606	 * There may be existing clients from as-yet unclosed files. For now,
 607	 * clean them up here rather than deferring until the file is closed,
 608	 * but this likely not correct if we want to support hot-unplugging
 609	 * properly.
 610	 */
 611	mutex_lock(&drm->clients_lock);
 612	list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
 613		list_del(&cli->head);
 614		mutex_lock(&cli->mutex);
 615		if (cli->abi16)
 616			nouveau_abi16_fini(cli->abi16);
 617		mutex_unlock(&cli->mutex);
 618		nouveau_cli_fini(cli);
 619		kfree(cli);
 620	}
 621	mutex_unlock(&drm->clients_lock);
 622
 623	nouveau_cli_fini(&drm->client);
 624	destroy_workqueue(drm->sched_wq);
 625	mutex_destroy(&drm->clients_lock);
 626}
 627
 628static int
 629nouveau_drm_device_init(struct nouveau_drm *drm)
 630{
 631	struct drm_device *dev = drm->dev;
 632	int ret;
 633
 634	drm->sched_wq = alloc_workqueue("nouveau_sched_wq_shared", 0,
 635					WQ_MAX_ACTIVE);
 636	if (!drm->sched_wq)
 637		return -ENOMEM;
 638
 639	ret = nouveau_cli_init(drm, "DRM", &drm->client);
 640	if (ret)
 641		goto fail_wq;
 642
 643	INIT_LIST_HEAD(&drm->clients);
 644	mutex_init(&drm->clients_lock);
 645	spin_lock_init(&drm->tile.lock);
 646
 647	/* workaround an odd issue on nvc1 by disabling the device's
 648	 * nosnoop capability.  hopefully won't cause issues until a
 649	 * better fix is found - assuming there is one...
 650	 */
 651	if (drm->client.device.info.chipset == 0xc1)
 652		nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
 653
 654	nouveau_vga_init(drm);
 655
 656	ret = nouveau_ttm_init(drm);
 657	if (ret)
 658		goto fail_ttm;
 659
 660	ret = nouveau_bios_init(dev);
 661	if (ret)
 662		goto fail_bios;
 663
 664	nouveau_accel_init(drm);
 665
 666	ret = nouveau_display_create(dev);
 667	if (ret)
 668		goto fail_dispctor;
 669
 670	if (dev->mode_config.num_crtc) {
 671		ret = nouveau_display_init(dev, false, false);
 672		if (ret)
 673			goto fail_dispinit;
 674	}
 675
 676	nouveau_debugfs_init(drm);
 677	nouveau_hwmon_init(dev);
 678	nouveau_svm_init(drm);
 679	nouveau_dmem_init(drm);
 680	nouveau_led_init(dev);
 681
 682	if (nouveau_pmops_runtime()) {
 683		pm_runtime_use_autosuspend(dev->dev);
 684		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 685		pm_runtime_set_active(dev->dev);
 686		pm_runtime_allow(dev->dev);
 687		pm_runtime_mark_last_busy(dev->dev);
 688		pm_runtime_put(dev->dev);
 689	}
 690
 691	ret = drm_dev_register(drm->dev, 0);
 692	if (ret) {
 693		nouveau_drm_device_fini(drm);
 694		return ret;
 695	}
 696
 697	return 0;
 698fail_dispinit:
 699	nouveau_display_destroy(dev);
 700fail_dispctor:
 701	nouveau_accel_fini(drm);
 702	nouveau_bios_takedown(dev);
 703fail_bios:
 704	nouveau_ttm_fini(drm);
 705fail_ttm:
 706	nouveau_vga_fini(drm);
 707	nouveau_cli_fini(&drm->client);
 708fail_wq:
 709	destroy_workqueue(drm->sched_wq);
 710	return ret;
 711}
 712
 713static void
 714nouveau_drm_device_del(struct nouveau_drm *drm)
 715{
 716	if (drm->dev)
 717		drm_dev_put(drm->dev);
 718
 719	nvif_mmu_dtor(&drm->mmu);
 720	nvif_device_dtor(&drm->device);
 721	nvif_client_dtor(&drm->_client);
 722	nvif_parent_dtor(&drm->parent);
 723
 724	mutex_destroy(&drm->client_mutex);
 725	kfree(drm);
 726}
 727
 728static struct nouveau_drm *
 729nouveau_drm_device_new(const struct drm_driver *drm_driver, struct device *parent,
 730		       struct nvkm_device *device)
 731{
 732	static const struct nvif_mclass
 733	mmus[] = {
 734		{ NVIF_CLASS_MMU_GF100, -1 },
 735		{ NVIF_CLASS_MMU_NV50 , -1 },
 736		{ NVIF_CLASS_MMU_NV04 , -1 },
 737		{}
 738	};
 739	struct nouveau_drm *drm;
 740	int ret;
 741
 742	drm = kzalloc(sizeof(*drm), GFP_KERNEL);
 743	if (!drm)
 744		return ERR_PTR(-ENOMEM);
 745
 746	drm->nvkm = device;
 747
 748	drm->dev = drm_dev_alloc(drm_driver, parent);
 749	if (IS_ERR(drm->dev)) {
 750		ret = PTR_ERR(drm->dev);
 751		goto done;
 752	}
 753
 754	drm->dev->dev_private = drm;
 755	dev_set_drvdata(parent, drm);
 756
 757	nvif_parent_ctor(&nouveau_parent, &drm->parent);
 758	mutex_init(&drm->client_mutex);
 759	drm->_client.object.parent = &drm->parent;
 760
 761	ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, "drm",
 762			       nouveau_name(drm->dev), &drm->_client);
 763	if (ret)
 764		goto done;
 765
 766	ret = nvif_device_ctor(&drm->_client, "drmDevice", &drm->device);
 767	if (ret) {
 768		NV_ERROR(drm, "Device allocation failed: %d\n", ret);
 769		goto done;
 770	}
 771
 772	ret = nvif_device_map(&drm->device);
 773	if (ret) {
 774		NV_ERROR(drm, "Failed to map PRI: %d\n", ret);
 775		goto done;
 776	}
 777
 778	ret = nvif_mclass(&drm->device.object, mmus);
 779	if (ret < 0) {
 780		NV_ERROR(drm, "No supported MMU class\n");
 781		goto done;
 782	}
 783
 784	ret = nvif_mmu_ctor(&drm->device.object, "drmMmu", mmus[ret].oclass, &drm->mmu);
 785	if (ret) {
 786		NV_ERROR(drm, "MMU allocation failed: %d\n", ret);
 787		goto done;
 788	}
 789
 790done:
 791	if (ret) {
 792		nouveau_drm_device_del(drm);
 793		drm = NULL;
 794	}
 795
 796	return ret ? ERR_PTR(ret) : drm;
 797}
 798
 799/*
 800 * On some Intel PCIe bridge controllers doing a
 801 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
 802 * Skipping the intermediate D3hot step seems to make it work again. This is
 803 * probably caused by not meeting the expectation the involved AML code has
 804 * when the GPU is put into D3hot state before invoking it.
 805 *
 806 * This leads to various manifestations of this issue:
 807 *  - AML code execution to power on the GPU hits an infinite loop (as the
 808 *    code waits on device memory to change).
 809 *  - kernel crashes, as all PCI reads return -1, which most code isn't able
 810 *    to handle well enough.
 811 *
 812 * In all cases dmesg will contain at least one line like this:
 813 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
 814 * followed by a lot of nouveau timeouts.
 815 *
 816 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
 817 * documented PCI config space register 0x248 of the Intel PCIe bridge
 818 * controller (0x1901) in order to change the state of the PCIe link between
 819 * the PCIe port and the GPU. There are alternative code paths using other
 820 * registers, which seem to work fine (executed pre Windows 8):
 821 *  - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
 822 *  - 0xb0 bit 0x10 (link disable)
 823 * Changing the conditions inside the firmware by poking into the relevant
 824 * addresses does resolve the issue, but it seemed to be ACPI private memory
 825 * and not any device accessible memory at all, so there is no portable way of
 826 * changing the conditions.
 827 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
 828 *
 829 * The only systems where this behavior can be seen are hybrid graphics laptops
 830 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
 831 * this issue only occurs in combination with listed Intel PCIe bridge
 832 * controllers and the mentioned GPUs or other devices as well.
 833 *
 834 * documentation on the PCIe bridge controller can be found in the
 835 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
 836 * Section "12 PCI Express* Controller (x16) Registers"
 837 */
 838
 839static void quirk_broken_nv_runpm(struct pci_dev *pdev)
 840{
 841	struct nouveau_drm *drm = pci_get_drvdata(pdev);
 842	struct pci_dev *bridge = pci_upstream_bridge(pdev);
 843
 844	if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
 845		return;
 846
 847	switch (bridge->device) {
 848	case 0x1901:
 849		drm->old_pm_cap = pdev->pm_cap;
 850		pdev->pm_cap = 0;
 851		NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
 852		break;
 853	}
 854}
 855
 856static int nouveau_drm_probe(struct pci_dev *pdev,
 857			     const struct pci_device_id *pent)
 858{
 859	struct nvkm_device *device;
 860	struct nouveau_drm *drm;
 861	const struct drm_format_info *format;
 862	int ret;
 863
 864	if (vga_switcheroo_client_probe_defer(pdev))
 865		return -EPROBE_DEFER;
 866
 867	/* We need to check that the chipset is supported before booting
 868	 * fbdev off the hardware, as there's no way to put it back.
 869	 */
 870	ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, &device);
 871	if (ret)
 872		return ret;
 873
 874	/* Remove conflicting drivers (vesafb, efifb etc). */
 875	ret = aperture_remove_conflicting_pci_devices(pdev, driver_pci.name);
 876	if (ret)
 877		return ret;
 878
 879	pci_set_master(pdev);
 880
 881	if (nouveau_atomic)
 882		driver_pci.driver_features |= DRIVER_ATOMIC;
 883
 884	drm = nouveau_drm_device_new(&driver_pci, &pdev->dev, device);
 885	if (IS_ERR(drm)) {
 886		ret = PTR_ERR(drm);
 887		goto fail_nvkm;
 888	}
 889
 890	ret = pci_enable_device(pdev);
 891	if (ret)
 892		goto fail_drm;
 893
 894	ret = nouveau_drm_device_init(drm);
 895	if (ret)
 896		goto fail_pci;
 897
 898	if (drm->client.device.info.ram_size <= 32 * 1024 * 1024)
 899		format = drm_format_info(DRM_FORMAT_C8);
 900	else
 901		format = NULL;
 902
 903	drm_client_setup(drm->dev, format);
 904
 905	quirk_broken_nv_runpm(pdev);
 906	return 0;
 907
 908fail_pci:
 909	pci_disable_device(pdev);
 910fail_drm:
 911	nouveau_drm_device_del(drm);
 912fail_nvkm:
 913	nvkm_device_del(&device);
 914	return ret;
 915}
 916
 917void
 918nouveau_drm_device_remove(struct nouveau_drm *drm)
 919{
 920	struct nvkm_device *device = drm->nvkm;
 921
 922	drm_dev_unplug(drm->dev);
 923
 924	nouveau_drm_device_fini(drm);
 925	nouveau_drm_device_del(drm);
 926	nvkm_device_del(&device);
 927}
 928
 929static void
 930nouveau_drm_remove(struct pci_dev *pdev)
 931{
 932	struct nouveau_drm *drm = pci_get_drvdata(pdev);
 933
 934	/* revert our workaround */
 935	if (drm->old_pm_cap)
 936		pdev->pm_cap = drm->old_pm_cap;
 937	nouveau_drm_device_remove(drm);
 938	pci_disable_device(pdev);
 939}
 940
 941static int
 942nouveau_do_suspend(struct nouveau_drm *drm, bool runtime)
 943{
 944	struct drm_device *dev = drm->dev;
 945	struct ttm_resource_manager *man;
 946	int ret;
 947
 948	nouveau_svm_suspend(drm);
 949	nouveau_dmem_suspend(drm);
 950	nouveau_led_suspend(dev);
 951
 952	if (dev->mode_config.num_crtc) {
 953		NV_DEBUG(drm, "suspending display...\n");
 954		ret = nouveau_display_suspend(dev, runtime);
 955		if (ret)
 956			return ret;
 957	}
 958
 959	NV_DEBUG(drm, "evicting buffers...\n");
 960
 961	man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM);
 962	ttm_resource_manager_evict_all(&drm->ttm.bdev, man);
 963
 964	NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
 965	if (drm->cechan) {
 966		ret = nouveau_channel_idle(drm->cechan);
 967		if (ret)
 968			goto fail_display;
 969	}
 970
 971	if (drm->channel) {
 972		ret = nouveau_channel_idle(drm->channel);
 973		if (ret)
 974			goto fail_display;
 975	}
 976
 977	NV_DEBUG(drm, "suspending fence...\n");
 978	if (drm->fence && nouveau_fence(drm)->suspend) {
 979		if (!nouveau_fence(drm)->suspend(drm)) {
 980			ret = -ENOMEM;
 981			goto fail_display;
 982		}
 983	}
 984
 985	NV_DEBUG(drm, "suspending object tree...\n");
 986	ret = nvif_client_suspend(&drm->_client, runtime);
 987	if (ret)
 988		goto fail_client;
 989
 990	return 0;
 991
 992fail_client:
 993	if (drm->fence && nouveau_fence(drm)->resume)
 994		nouveau_fence(drm)->resume(drm);
 995
 996fail_display:
 997	if (dev->mode_config.num_crtc) {
 998		NV_DEBUG(drm, "resuming display...\n");
 999		nouveau_display_resume(dev, runtime);
1000	}
1001	return ret;
1002}
1003
1004static int
1005nouveau_do_resume(struct nouveau_drm *drm, bool runtime)
1006{
1007	struct drm_device *dev = drm->dev;
1008	int ret = 0;
1009
1010	NV_DEBUG(drm, "resuming object tree...\n");
1011	ret = nvif_client_resume(&drm->_client);
1012	if (ret) {
1013		NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
1014		return ret;
1015	}
1016
1017	NV_DEBUG(drm, "resuming fence...\n");
1018	if (drm->fence && nouveau_fence(drm)->resume)
1019		nouveau_fence(drm)->resume(drm);
1020
1021	nouveau_run_vbios_init(dev);
1022
1023	if (dev->mode_config.num_crtc) {
1024		NV_DEBUG(drm, "resuming display...\n");
1025		nouveau_display_resume(dev, runtime);
1026	}
1027
1028	nouveau_led_resume(dev);
1029	nouveau_dmem_resume(drm);
1030	nouveau_svm_resume(drm);
1031	return 0;
1032}
1033
1034int
1035nouveau_pmops_suspend(struct device *dev)
1036{
1037	struct pci_dev *pdev = to_pci_dev(dev);
1038	struct nouveau_drm *drm = pci_get_drvdata(pdev);
1039	int ret;
1040
1041	if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1042	    drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1043		return 0;
1044
1045	ret = nouveau_do_suspend(drm, false);
1046	if (ret)
1047		return ret;
1048
1049	pci_save_state(pdev);
1050	pci_disable_device(pdev);
1051	pci_set_power_state(pdev, PCI_D3hot);
1052	udelay(200);
1053	return 0;
1054}
1055
1056int
1057nouveau_pmops_resume(struct device *dev)
1058{
1059	struct pci_dev *pdev = to_pci_dev(dev);
1060	struct nouveau_drm *drm = pci_get_drvdata(pdev);
1061	int ret;
1062
1063	if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1064	    drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1065		return 0;
1066
1067	pci_set_power_state(pdev, PCI_D0);
1068	pci_restore_state(pdev);
1069	ret = pci_enable_device(pdev);
1070	if (ret)
1071		return ret;
1072	pci_set_master(pdev);
1073
1074	ret = nouveau_do_resume(drm, false);
1075
1076	/* Monitors may have been connected / disconnected during suspend */
1077	nouveau_display_hpd_resume(drm);
1078
1079	return ret;
1080}
1081
1082static int
1083nouveau_pmops_freeze(struct device *dev)
1084{
1085	struct nouveau_drm *drm = dev_get_drvdata(dev);
1086
1087	if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1088	    drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1089		return 0;
1090
1091	return nouveau_do_suspend(drm, false);
1092}
1093
1094static int
1095nouveau_pmops_thaw(struct device *dev)
1096{
1097	struct nouveau_drm *drm = dev_get_drvdata(dev);
1098
1099	if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1100	    drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1101		return 0;
1102
1103	return nouveau_do_resume(drm, false);
1104}
1105
1106bool
1107nouveau_pmops_runtime(void)
1108{
1109	if (nouveau_runtime_pm == -1)
1110		return nouveau_is_optimus() || nouveau_is_v1_dsm();
1111	return nouveau_runtime_pm == 1;
1112}
1113
1114static int
1115nouveau_pmops_runtime_suspend(struct device *dev)
1116{
1117	struct pci_dev *pdev = to_pci_dev(dev);
1118	struct nouveau_drm *drm = pci_get_drvdata(pdev);
1119	int ret;
1120
1121	if (!nouveau_pmops_runtime()) {
1122		pm_runtime_forbid(dev);
1123		return -EBUSY;
1124	}
1125
1126	nouveau_switcheroo_optimus_dsm();
1127	ret = nouveau_do_suspend(drm, true);
1128	pci_save_state(pdev);
1129	pci_disable_device(pdev);
1130	pci_ignore_hotplug(pdev);
1131	pci_set_power_state(pdev, PCI_D3cold);
1132	drm->dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1133	return ret;
1134}
1135
1136static int
1137nouveau_pmops_runtime_resume(struct device *dev)
1138{
1139	struct pci_dev *pdev = to_pci_dev(dev);
1140	struct nouveau_drm *drm = pci_get_drvdata(pdev);
1141	struct nvif_device *device = &drm->client.device;
1142	int ret;
1143
1144	if (!nouveau_pmops_runtime()) {
1145		pm_runtime_forbid(dev);
1146		return -EBUSY;
1147	}
1148
1149	pci_set_power_state(pdev, PCI_D0);
1150	pci_restore_state(pdev);
1151	ret = pci_enable_device(pdev);
1152	if (ret)
1153		return ret;
1154	pci_set_master(pdev);
1155
1156	ret = nouveau_do_resume(drm, true);
1157	if (ret) {
1158		NV_ERROR(drm, "resume failed with: %d\n", ret);
1159		return ret;
1160	}
1161
1162	/* do magic */
1163	nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1164	drm->dev->switch_power_state = DRM_SWITCH_POWER_ON;
1165
1166	/* Monitors may have been connected / disconnected during suspend */
1167	nouveau_display_hpd_resume(drm);
1168
1169	return ret;
1170}
1171
1172static int
1173nouveau_pmops_runtime_idle(struct device *dev)
1174{
1175	if (!nouveau_pmops_runtime()) {
1176		pm_runtime_forbid(dev);
1177		return -EBUSY;
1178	}
1179
1180	pm_runtime_mark_last_busy(dev);
1181	pm_runtime_autosuspend(dev);
1182	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1183	return 1;
1184}
1185
1186static int
1187nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1188{
1189	struct nouveau_drm *drm = nouveau_drm(dev);
1190	struct nouveau_cli *cli;
1191	char name[32];
1192	int ret;
1193
1194	/* need to bring up power immediately if opening device */
1195	ret = pm_runtime_get_sync(dev->dev);
1196	if (ret < 0 && ret != -EACCES) {
1197		pm_runtime_put_autosuspend(dev->dev);
1198		return ret;
1199	}
1200
1201	rcu_read_lock();
1202	snprintf(name, sizeof(name), "%s[%d]",
1203		 current->comm, pid_nr(rcu_dereference(fpriv->pid)));
1204	rcu_read_unlock();
1205
1206	if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1207		ret = -ENOMEM;
1208		goto done;
1209	}
1210
1211	ret = nouveau_cli_init(drm, name, cli);
1212	if (ret)
1213		goto done;
1214
1215	fpriv->driver_priv = cli;
1216
1217	mutex_lock(&drm->clients_lock);
1218	list_add(&cli->head, &drm->clients);
1219	mutex_unlock(&drm->clients_lock);
1220
1221done:
1222	if (ret && cli) {
1223		nouveau_cli_fini(cli);
1224		kfree(cli);
1225	}
1226
1227	pm_runtime_mark_last_busy(dev->dev);
1228	pm_runtime_put_autosuspend(dev->dev);
1229	return ret;
1230}
1231
1232static void
1233nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1234{
1235	struct nouveau_cli *cli = nouveau_cli(fpriv);
1236	struct nouveau_drm *drm = nouveau_drm(dev);
1237	int dev_index;
1238
1239	/*
1240	 * The device is gone, and as it currently stands all clients are
1241	 * cleaned up in the removal codepath. In the future this may change
1242	 * so that we can support hot-unplugging, but for now we immediately
1243	 * return to avoid a double-free situation.
1244	 */
1245	if (!drm_dev_enter(dev, &dev_index))
1246		return;
1247
1248	pm_runtime_get_sync(dev->dev);
1249
1250	mutex_lock(&cli->mutex);
1251	if (cli->abi16)
1252		nouveau_abi16_fini(cli->abi16);
1253	mutex_unlock(&cli->mutex);
1254
1255	mutex_lock(&drm->clients_lock);
1256	list_del(&cli->head);
1257	mutex_unlock(&drm->clients_lock);
1258
1259	nouveau_cli_fini(cli);
1260	kfree(cli);
1261	pm_runtime_mark_last_busy(dev->dev);
1262	pm_runtime_put_autosuspend(dev->dev);
1263	drm_dev_exit(dev_index);
1264}
1265
1266static const struct drm_ioctl_desc
1267nouveau_ioctls[] = {
1268	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1269	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1270	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1271	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1272	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1273	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1274	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1275	DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1276	DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1277	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1278	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1279	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1280	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1281	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1282	DRM_IOCTL_DEF_DRV(NOUVEAU_VM_INIT, nouveau_uvmm_ioctl_vm_init, DRM_RENDER_ALLOW),
1283	DRM_IOCTL_DEF_DRV(NOUVEAU_VM_BIND, nouveau_uvmm_ioctl_vm_bind, DRM_RENDER_ALLOW),
1284	DRM_IOCTL_DEF_DRV(NOUVEAU_EXEC, nouveau_exec_ioctl_exec, DRM_RENDER_ALLOW),
1285};
1286
1287long
1288nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1289{
1290	struct drm_file *filp = file->private_data;
1291	struct drm_device *dev = filp->minor->dev;
1292	long ret;
1293
1294	ret = pm_runtime_get_sync(dev->dev);
1295	if (ret < 0 && ret != -EACCES) {
1296		pm_runtime_put_autosuspend(dev->dev);
1297		return ret;
1298	}
1299
1300	switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1301	case DRM_NOUVEAU_NVIF:
1302		ret = nouveau_abi16_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1303		break;
1304	default:
1305		ret = drm_ioctl(file, cmd, arg);
1306		break;
1307	}
1308
1309	pm_runtime_mark_last_busy(dev->dev);
1310	pm_runtime_put_autosuspend(dev->dev);
1311	return ret;
1312}
1313
1314static const struct file_operations
1315nouveau_driver_fops = {
1316	.owner = THIS_MODULE,
1317	.open = drm_open,
1318	.release = drm_release,
1319	.unlocked_ioctl = nouveau_drm_ioctl,
1320	.mmap = drm_gem_mmap,
1321	.poll = drm_poll,
1322	.read = drm_read,
1323#if defined(CONFIG_COMPAT)
1324	.compat_ioctl = nouveau_compat_ioctl,
1325#endif
1326	.llseek = noop_llseek,
1327	.fop_flags = FOP_UNSIGNED_OFFSET,
1328};
1329
1330static struct drm_driver
1331driver_stub = {
1332	.driver_features = DRIVER_GEM |
1333			   DRIVER_SYNCOBJ | DRIVER_SYNCOBJ_TIMELINE |
1334			   DRIVER_GEM_GPUVA |
1335			   DRIVER_MODESET |
1336			   DRIVER_RENDER,
1337	.open = nouveau_drm_open,
1338	.postclose = nouveau_drm_postclose,
1339
1340#if defined(CONFIG_DEBUG_FS)
1341	.debugfs_init = nouveau_drm_debugfs_init,
1342#endif
1343
1344	.ioctls = nouveau_ioctls,
1345	.num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1346	.fops = &nouveau_driver_fops,
1347
1348	.gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1349
1350	.dumb_create = nouveau_display_dumb_create,
1351	.dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1352
1353	DRM_FBDEV_TTM_DRIVER_OPS,
1354
1355	.name = DRIVER_NAME,
1356	.desc = DRIVER_DESC,
1357	.major = DRIVER_MAJOR,
1358	.minor = DRIVER_MINOR,
1359	.patchlevel = DRIVER_PATCHLEVEL,
1360};
1361
1362static struct pci_device_id
1363nouveau_drm_pci_table[] = {
1364	{
1365		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1366		.class = PCI_BASE_CLASS_DISPLAY << 16,
1367		.class_mask  = 0xff << 16,
1368	},
1369	{
1370		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1371		.class = PCI_BASE_CLASS_DISPLAY << 16,
1372		.class_mask  = 0xff << 16,
1373	},
1374	{}
1375};
1376
1377static void nouveau_display_options(void)
1378{
1379	DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1380
1381	DRM_DEBUG_DRIVER("... tv_disable   : %d\n", nouveau_tv_disable);
1382	DRM_DEBUG_DRIVER("... ignorelid    : %d\n", nouveau_ignorelid);
1383	DRM_DEBUG_DRIVER("... duallink     : %d\n", nouveau_duallink);
1384	DRM_DEBUG_DRIVER("... config       : %s\n", nouveau_config);
1385	DRM_DEBUG_DRIVER("... debug        : %s\n", nouveau_debug);
1386	DRM_DEBUG_DRIVER("... noaccel      : %d\n", nouveau_noaccel);
1387	DRM_DEBUG_DRIVER("... modeset      : %d\n", nouveau_modeset);
1388	DRM_DEBUG_DRIVER("... runpm        : %d\n", nouveau_runtime_pm);
1389	DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1390	DRM_DEBUG_DRIVER("... hdmimhz      : %d\n", nouveau_hdmimhz);
1391}
1392
1393static const struct dev_pm_ops nouveau_pm_ops = {
1394	.suspend = nouveau_pmops_suspend,
1395	.resume = nouveau_pmops_resume,
1396	.freeze = nouveau_pmops_freeze,
1397	.thaw = nouveau_pmops_thaw,
1398	.poweroff = nouveau_pmops_freeze,
1399	.restore = nouveau_pmops_resume,
1400	.runtime_suspend = nouveau_pmops_runtime_suspend,
1401	.runtime_resume = nouveau_pmops_runtime_resume,
1402	.runtime_idle = nouveau_pmops_runtime_idle,
1403};
1404
1405static struct pci_driver
1406nouveau_drm_pci_driver = {
1407	.name = "nouveau",
1408	.id_table = nouveau_drm_pci_table,
1409	.probe = nouveau_drm_probe,
1410	.remove = nouveau_drm_remove,
1411	.driver.pm = &nouveau_pm_ops,
1412};
1413
1414struct drm_device *
1415nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1416			       struct platform_device *pdev,
1417			       struct nvkm_device **pdevice)
1418{
1419	struct nouveau_drm *drm;
1420	int err;
1421
1422	err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, pdevice);
1423	if (err)
1424		goto err_free;
1425
1426	drm = nouveau_drm_device_new(&driver_platform, &pdev->dev, *pdevice);
1427	if (IS_ERR(drm)) {
1428		err = PTR_ERR(drm);
1429		goto err_free;
1430	}
1431
1432	err = nouveau_drm_device_init(drm);
1433	if (err)
1434		goto err_put;
1435
1436	return drm->dev;
1437
1438err_put:
1439	nouveau_drm_device_del(drm);
1440err_free:
1441	nvkm_device_del(pdevice);
1442
1443	return ERR_PTR(err);
1444}
1445
1446static int __init
1447nouveau_drm_init(void)
1448{
1449	int ret;
1450
1451	driver_pci = driver_stub;
1452	driver_platform = driver_stub;
1453
1454	nouveau_display_options();
1455
1456	if (nouveau_modeset == -1) {
1457		if (drm_firmware_drivers_only())
1458			nouveau_modeset = 0;
1459	}
1460
1461	if (!nouveau_modeset)
1462		return 0;
1463
1464	nouveau_module_debugfs_init();
1465
1466#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1467	platform_driver_register(&nouveau_platform_driver);
1468#endif
1469
1470	nouveau_register_dsm_handler();
1471	nouveau_backlight_ctor();
1472
1473#ifdef CONFIG_PCI
1474	ret = pci_register_driver(&nouveau_drm_pci_driver);
1475	if (ret) {
1476		nouveau_module_debugfs_fini();
1477		return ret;
1478	}
1479#endif
1480
1481	return 0;
1482}
1483
1484static void __exit
1485nouveau_drm_exit(void)
1486{
1487	if (!nouveau_modeset)
1488		return;
1489
1490#ifdef CONFIG_PCI
1491	pci_unregister_driver(&nouveau_drm_pci_driver);
1492#endif
1493	nouveau_backlight_dtor();
1494	nouveau_unregister_dsm_handler();
1495
1496#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1497	platform_driver_unregister(&nouveau_platform_driver);
1498#endif
1499	if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1500		mmu_notifier_synchronize();
1501
1502#ifdef CONFIG_DEBUG_FS
1503	nvif_log_shutdown(&gsp_logs);
1504#endif
1505
1506	nouveau_module_debugfs_fini();
1507}
1508
1509module_init(nouveau_drm_init);
1510module_exit(nouveau_drm_exit);
1511
1512MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1513MODULE_AUTHOR(DRIVER_AUTHOR);
1514MODULE_DESCRIPTION(DRIVER_DESC);
1515MODULE_LICENSE("GPL and additional rights");