clc36f.h

  1/* SPDX-License-Identifier: MIT
  2 *
  3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
  4 */
  5#ifndef _clc36f_h_
  6#define _clc36f_h_
  7
  8#define NVC36F_NON_STALL_INTERRUPT                                 (0x00000020)
  9#define NVC36F_NON_STALL_INTERRUPT_HANDLE                                 31:0
 10// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
 11// specifying the page address for a targeted TLB invalidate and the uTLB for
 12// a targeted REPLAY_CANCEL for UVM.
 13// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
 14// rearranged fields.
 15#define NVC36F_MEM_OP_A                                            (0x00000028)
 16#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID        5:0  // only relevant for REPLAY_CANCEL_TARGETED
 17#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE                   5:0  // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
 18#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID               10:6  // only relevant for REPLAY_CANCEL_TARGETED
 19#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID                6:0  // only relevant for REPLAY_CANCEL_VA_GLOBAL
 20#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR                         11:11
 21#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN                 0x00000001
 22#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS                0x00000000
 23#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO                    31:12
 24#define NVC36F_MEM_OP_B                                            (0x0000002c)
 25#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI                     31:0
 26#define NVC36F_MEM_OP_C                                            (0x00000030)
 27#define NVC36F_MEM_OP_C_MEMBAR_TYPE                                        2:0
 28#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR                      0x00000000
 29#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR                          0x00000001
 30#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB                                 0:0
 31#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE                      0x00000000
 32#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL                      0x00000001  // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
 33#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC                                 1:1
 34#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE                   0x00000000
 35#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE                  0x00000001
 36#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY                              4:2  // only relevant if GPC ENABLE
 37#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE                  0x00000000
 38#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START                 0x00000001
 39#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL         0x00000002
 40#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED       0x00000003
 41#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL         0x00000004
 42#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL      0x00000005
 43#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE                            6:5  // only relevant if GPC ENABLE
 44#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE                0x00000000
 45#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY            0x00000001
 46#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE           0x00000002
 47#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE                         9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
 48#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ                 0
 49#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE                1
 50#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG        2
 51#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD               3
 52#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK          4
 53#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL           5
 54#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC     6
 55#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL                  7
 56#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL                    9:7  // Invalidate affects this level and all below
 57#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL         0x00000000  // Invalidate tlb caches at all levels of the page table
 58#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY    0x00000001
 59#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0  0x00000002
 60#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1  0x00000003
 61#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2  0x00000004
 62#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3  0x00000005
 63#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4  0x00000006
 64#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5  0x00000007
 65#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE                          11:10  // only relevant if PDB_ONE
 66#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM             0x00000000
 67#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT    0x00000002
 68#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
 69#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO                       31:12  // only relevant if PDB_ONE
 70#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG            19:0
 71// MEM_OP_D MUST be preceded by MEM_OPs A-C.
 72#define NVC36F_MEM_OP_D                                            (0x00000034)
 73#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI                        26:0  // only relevant if PDB_ONE
 74#define NVC36F_MEM_OP_D_OPERATION                                        31:27
 75#define NVC36F_MEM_OP_D_OPERATION_MEMBAR                            0x00000005
 76#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE                0x00000009
 77#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED       0x0000000a
 78#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE             0x0000000d
 79#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE              0x0000000e
 80// CLEAN_LINES is an alias for Tegra/GPU IP usage
 81#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES         0x0000000e
 82#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS                 0x0000000f
 83#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY                    0x00000010
 84#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS     0x00000015
 85#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR                0x00000016
 86#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE                            1:0
 87#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC                0x00000000
 88#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC                0x00000001
 89#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL                 0x00000002
 90#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED            0x00000003
 91#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE                   2:2
 92#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC       0x00000000
 93#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC       0x00000001
 94#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK                   6:3
 95#define NVC36F_SEM_ADDR_LO                                         (0x0000005c)
 96#define NVC36F_SEM_ADDR_LO_OFFSET                                         31:2
 97#define NVC36F_SEM_ADDR_HI                                         (0x00000060)
 98#define NVC36F_SEM_ADDR_HI_OFFSET                                          7:0
 99#define NVC36F_SEM_PAYLOAD_LO                                      (0x00000064)
100#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD                                     31:0
101#define NVC36F_SEM_PAYLOAD_HI                                      (0x00000068)
102#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD                                     31:0
103#define NVC36F_SEM_EXECUTE                                         (0x0000006c)
104#define NVC36F_SEM_EXECUTE_OPERATION                                       2:0
105#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE                        0x00000000
106#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE                        0x00000001
107#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ                 0x00000002
108#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ                   0x00000003
109#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND                        0x00000004
110#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR                        0x00000005
111#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION                      0x00000006
112#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG                            12:12
113#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS                   0x00000000
114#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN                    0x00000001
115#define NVC36F_SEM_EXECUTE_RELEASE_WFI                                   20:20
116#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS                          0x00000000
117#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN                           0x00000001
118#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE                                  24:24
119#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT                       0x00000000
120#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT                       0x00000001
121#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP                             25:25
122#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS                    0x00000000
123#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN                     0x00000001
124#define NVC36F_SEM_EXECUTE_REDUCTION                                     30:27
125#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN                           0x00000000
126#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX                           0x00000001
127#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR                           0x00000002
128#define NVC36F_SEM_EXECUTE_REDUCTION_IAND                           0x00000003
129#define NVC36F_SEM_EXECUTE_REDUCTION_IOR                            0x00000004
130#define NVC36F_SEM_EXECUTE_REDUCTION_IADD                           0x00000005
131#define NVC36F_SEM_EXECUTE_REDUCTION_INC                            0x00000006
132#define NVC36F_SEM_EXECUTE_REDUCTION_DEC                            0x00000007
133#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT                              31:31
134#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED                  0x00000000
135#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED                0x00000001
136
137#endif