gv100_fence.c

 1/* SPDX-License-Identifier: MIT
 2 *
 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
 4 */
 5#include "nouveau_drv.h"
 6#include "nouveau_dma.h"
 7#include "nouveau_fence.h"
 8
 9#include "nv50_display.h"
10
11#include <nvif/push906f.h>
12
13#include <nvhw/class/clc36f.h>
14
15static int
16gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
17{
18	struct nvif_push *push = &chan->chan.push;
19	int ret;
20
21	ret = PUSH_WAIT(push, 13);
22	if (ret)
23		return ret;
24
25	PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
26				SEM_ADDR_HI, upper_32_bits(virtual),
27				SEM_PAYLOAD_LO, sequence);
28
29	PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
30		  NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) |
31		  NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) |
32		  NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
33		  NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));
34
35	PUSH_MTHD(push, NVC36F, MEM_OP_A, 0,
36				MEM_OP_B, 0,
37				MEM_OP_C, NVDEF(NVC36F, MEM_OP_C, MEMBAR_TYPE, SYS_MEMBAR),
38				MEM_OP_D, NVDEF(NVC36F, MEM_OP_D, OPERATION, MEMBAR));
39
40	PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
41
42	PUSH_KICK(push);
43	return 0;
44}
45
46static int
47gv100_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
48{
49	struct nvif_push *push = &chan->chan.push;
50	int ret;
51
52	ret = PUSH_WAIT(push, 6);
53	if (ret)
54		return ret;
55
56	PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
57				SEM_ADDR_HI, upper_32_bits(virtual),
58				SEM_PAYLOAD_LO, sequence);
59
60	PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
61		  NVDEF(NVC36F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) |
62		  NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) |
63		  NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT));
64
65	PUSH_KICK(push);
66	return 0;
67}
68
69static int
70gv100_fence_context_new(struct nouveau_channel *chan)
71{
72	struct nv84_fence_chan *fctx;
73	int ret;
74
75	ret = nv84_fence_context_new(chan);
76	if (ret)
77		return ret;
78
79	fctx = chan->fence;
80	fctx->base.emit32 = gv100_fence_emit32;
81	fctx->base.sync32 = gv100_fence_sync32;
82	return 0;
83}
84
85int
86gv100_fence_create(struct nouveau_drm *drm)
87{
88	struct nv84_fence_priv *priv;
89	int ret;
90
91	ret = nv84_fence_create(drm);
92	if (ret)
93		return ret;
94
95	priv = drm->fence;
96	priv->base.context_new = gv100_fence_context_new;
97	return 0;
98}