head.c

  1/*
  2 * Copyright 2018 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22#include "head.h"
 23#include "base.h"
 24#include "core.h"
 25#include "curs.h"
 26#include "ovly.h"
 27#include "crc.h"
 28
 29#include <nvif/class.h>
 30#include <nvif/event.h>
 31#include <nvif/cl0046.h>
 32
 33#include <drm/drm_atomic.h>
 34#include <drm/drm_atomic_helper.h>
 35#include <drm/drm_edid.h>
 36#include <drm/drm_vblank.h>
 37#include "nouveau_connector.h"
 38
 39void
 40nv50_head_flush_clr(struct nv50_head *head,
 41		    struct nv50_head_atom *asyh, bool flush)
 42{
 43	union nv50_head_atom_mask clr = {
 44		.mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
 45	};
 46
 47	lockdep_assert_held(&head->disp->mutex);
 48
 49	if (clr.crc)  nv50_crc_atomic_clr(head);
 50	if (clr.olut) head->func->olut_clr(head);
 51	if (clr.core) head->func->core_clr(head);
 52	if (clr.curs) head->func->curs_clr(head);
 53}
 54
 55void
 56nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh)
 57{
 58	if (asyh->set.curs   ) head->func->curs_set(head, asyh);
 59	if (asyh->set.olut   ) {
 60		asyh->olut.offset = nv50_lut_load(&head->olut,
 61						  asyh->olut.buffer,
 62						  asyh->state.gamma_lut,
 63						  asyh->olut.load);
 64		head->func->olut_set(head, asyh);
 65	}
 66}
 67
 68void
 69nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
 70{
 71	lockdep_assert_held(&head->disp->mutex);
 72
 73	if (asyh->set.view   ) head->func->view    (head, asyh);
 74	if (asyh->set.mode   ) head->func->mode    (head, asyh);
 75	if (asyh->set.core   ) head->func->core_set(head, asyh);
 76	if (asyh->set.base   ) head->func->base    (head, asyh);
 77	if (asyh->set.ovly   ) head->func->ovly    (head, asyh);
 78	if (asyh->set.dither ) head->func->dither  (head, asyh);
 79	if (asyh->set.procamp) head->func->procamp (head, asyh);
 80	if (asyh->set.crc    ) nv50_crc_atomic_set (head, asyh);
 81	if (asyh->set.or     ) head->func->or      (head, asyh);
 82}
 83
 84static void
 85nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
 86			       struct nv50_head_atom *asyh,
 87			       struct nouveau_conn_atom *asyc)
 88{
 89	const int vib = asyc->procamp.color_vibrance - 100;
 90	const int hue = asyc->procamp.vibrant_hue - 90;
 91	const int adj = (vib > 0) ? 50 : 0;
 92	asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
 93	asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
 94	asyh->set.procamp = true;
 95}
 96
 97static void
 98nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
 99			      struct nv50_head_atom *asyh,
100			      struct nouveau_conn_atom *asyc)
101{
102	u32 mode = 0x00;
103
104	if (asyc->dither.mode) {
105		if (asyc->dither.mode == DITHERING_MODE_AUTO) {
106			if (asyh->base.depth > asyh->or.bpc * 3)
107				mode = DITHERING_MODE_DYNAMIC2X2;
108		} else {
109			mode = asyc->dither.mode;
110		}
111
112		if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
113			if (asyh->or.bpc >= 8)
114				mode |= DITHERING_DEPTH_8BPC;
115		} else {
116			mode |= asyc->dither.depth;
117		}
118	}
119
120	asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);
121	asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);
122	asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);
123	asyh->set.dither = true;
124}
125
126static void
127nv50_head_atomic_check_view(struct nv50_head_atom *armh,
128			    struct nv50_head_atom *asyh,
129			    struct nouveau_conn_atom *asyc)
130{
131	struct drm_connector *connector = asyc->state.connector;
132	struct drm_display_mode *omode = &asyh->state.adjusted_mode;
133	struct drm_display_mode *umode = &asyh->state.mode;
134	int mode = asyc->scaler.mode;
135	int umode_vdisplay, omode_hdisplay, omode_vdisplay;
136
137	if (!asyc->scaler.full) {
138		if (mode == DRM_MODE_SCALE_NONE)
139			omode = umode;
140	} else {
141		/* Non-EDID LVDS/eDP mode. */
142		mode = DRM_MODE_SCALE_FULLSCREEN;
143	}
144
145	/* For the user-specified mode, we must ignore doublescan and
146	 * the like, but honor frame packing.
147	 */
148	umode_vdisplay = umode->vdisplay;
149	if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
150		umode_vdisplay += umode->vtotal;
151	asyh->view.iW = umode->hdisplay;
152	asyh->view.iH = umode_vdisplay;
153	/* For the output mode, we can just use the stock helper. */
154	drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
155	asyh->view.oW = omode_hdisplay;
156	asyh->view.oH = omode_vdisplay;
157
158	/* Add overscan compensation if necessary, will keep the aspect
159	 * ratio the same as the backend mode unless overridden by the
160	 * user setting both hborder and vborder properties.
161	 */
162	if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
163	    (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
164	     connector->display_info.is_hdmi))) {
165		u32 bX = asyc->scaler.underscan.hborder;
166		u32 bY = asyc->scaler.underscan.vborder;
167		u32 r = (asyh->view.oH << 19) / asyh->view.oW;
168
169		if (bX) {
170			asyh->view.oW -= (bX * 2);
171			if (bY) asyh->view.oH -= (bY * 2);
172			else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
173		} else {
174			asyh->view.oW -= (asyh->view.oW >> 4) + 32;
175			if (bY) asyh->view.oH -= (bY * 2);
176			else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
177		}
178	}
179
180	/* Handle CENTER/ASPECT scaling, taking into account the areas
181	 * removed already for overscan compensation.
182	 */
183	switch (mode) {
184	case DRM_MODE_SCALE_CENTER:
185		/* NOTE: This will cause scaling when the input is
186		 * larger than the output.
187		 */
188		asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
189		asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
190		break;
191	case DRM_MODE_SCALE_ASPECT:
192		/* Determine whether the scaling should be on width or on
193		 * height. This is done by comparing the aspect ratios of the
194		 * sizes. If the output AR is larger than input AR, that means
195		 * we want to change the width (letterboxed on the
196		 * left/right), otherwise on the height (letterboxed on the
197		 * top/bottom).
198		 *
199		 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
200		 * screen will have letterboxes on the left/right. However a
201		 * 16:9 (1.777) AR image on that same screen will have
202		 * letterboxes on the top/bottom.
203		 *
204		 * inputAR = iW / iH; outputAR = oW / oH
205		 * outputAR > inputAR is equivalent to oW * iH > iW * oH
206		 */
207		if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
208			/* Recompute output width, i.e. left/right letterbox */
209			u32 r = (asyh->view.iW << 19) / asyh->view.iH;
210			asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
211		} else {
212			/* Recompute output height, i.e. top/bottom letterbox */
213			u32 r = (asyh->view.iH << 19) / asyh->view.iW;
214			asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
215		}
216		break;
217	default:
218		break;
219	}
220
221	asyh->set.view = true;
222}
223
224static int
225nv50_head_atomic_check_lut(struct nv50_head *head,
226			   struct nv50_head_atom *asyh)
227{
228	struct drm_device *dev = head->base.base.dev;
229	struct drm_crtc *crtc = &head->base.base;
230	struct nv50_disp *disp = nv50_disp(dev);
231	struct nouveau_drm *drm = nouveau_drm(dev);
232	struct drm_property_blob *olut = asyh->state.gamma_lut,
233				 *ilut = asyh->state.degamma_lut;
234	int size;
235
236	/* Ensure that the ilut is valid */
237	if (ilut) {
238		size = drm_color_lut_size(ilut);
239		if (!head->func->ilut_check(size)) {
240			NV_ATOMIC(drm, "Invalid size %d for degamma on [CRTC:%d:%s]\n",
241				  size, crtc->base.id, crtc->name);
242			return -EINVAL;
243		}
244	}
245
246	/* Determine whether core output LUT should be enabled. */
247	if (olut) {
248		/* Check if any window(s) have stolen the core output LUT
249		 * to as an input LUT for legacy gamma + I8 colour format.
250		 */
251		if (asyh->wndw.olut) {
252			/* If any window has stolen the core output LUT,
253			 * all of them must.
254			 */
255			if (asyh->wndw.olut != asyh->wndw.mask)
256				return -EINVAL;
257			olut = NULL;
258		}
259	}
260
261	if (!olut) {
262		if (!head->func->olut_identity) {
263			asyh->olut.handle = 0;
264			return 0;
265		}
266		size = 0;
267	} else {
268		size = drm_color_lut_size(olut);
269	}
270
271	if (!head->func->olut(head, asyh, size)) {
272		NV_ATOMIC(drm, "Invalid size %d for gamma on [CRTC:%d:%s]\n",
273			  size, crtc->base.id, crtc->name);
274		return -EINVAL;
275	}
276	asyh->olut.handle = disp->core->chan.vram.handle;
277	asyh->olut.buffer = !asyh->olut.buffer;
278
279	return 0;
280}
281
282static void
283nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
284{
285	struct drm_display_mode *mode = &asyh->state.adjusted_mode;
286	struct nv50_head_mode *m = &asyh->mode;
287	u32 blankus;
288
289	drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
290
291	/*
292	 * DRM modes are defined in terms of a repeating interval
293	 * starting with the active display area.  The hardware modes
294	 * are defined in terms of a repeating interval starting one
295	 * unit (pixel or line) into the sync pulse.  So, add bias.
296	 */
297
298	m->h.active = mode->crtc_htotal;
299	m->h.synce  = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
300	m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
301	m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
302
303	m->v.active = mode->crtc_vtotal;
304	m->v.synce  = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
305	m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
306	m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
307
308	/*XXX: Safe underestimate, even "0" works */
309	blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
310	blankus *= 1000;
311	blankus /= mode->crtc_clock;
312	m->v.blankus = blankus;
313
314	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
315		m->v.blank2e =  m->v.active + m->v.blanke;
316		m->v.blank2s =  m->v.blank2e + mode->crtc_vdisplay;
317		m->v.active  = (m->v.active * 2) + 1;
318		m->interlace = true;
319	} else {
320		m->v.blank2e = 0;
321		m->v.blank2s = 1;
322		m->interlace = false;
323	}
324	m->clock = mode->crtc_clock;
325
326	asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
327	asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
328	asyh->set.or = head->func->or != NULL;
329	asyh->set.mode = true;
330}
331
332static int
333nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
334{
335	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
336									      crtc);
337	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
338									  crtc);
339	struct nouveau_drm *drm = nouveau_drm(crtc->dev);
340	struct nv50_head *head = nv50_head(crtc);
341	struct nv50_head_atom *armh = nv50_head_atom(old_crtc_state);
342	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
343	struct nouveau_conn_atom *asyc = NULL;
344	struct drm_connector_state *conns;
345	struct drm_connector *conn;
346	int i, ret;
347	bool check_lut = asyh->state.color_mgmt_changed ||
348			 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw));
349
350	NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
351
352	if (check_lut) {
353		ret = nv50_head_atomic_check_lut(head, asyh);
354		if (ret)
355			return ret;
356	}
357
358	if (asyh->state.active) {
359		for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
360			if (conns->crtc == crtc) {
361				asyc = nouveau_conn_atom(conns);
362				break;
363			}
364		}
365
366		if (armh->state.active) {
367			if (asyc) {
368				if (asyh->state.mode_changed)
369					asyc->set.scaler = true;
370				if (armh->base.depth != asyh->base.depth)
371					asyc->set.dither = true;
372			}
373		} else {
374			if (asyc)
375				asyc->set.mask = ~0;
376			asyh->set.mask = ~0;
377			asyh->set.or = head->func->or != NULL;
378		}
379
380		if (asyh->state.mode_changed || asyh->state.connectors_changed)
381			nv50_head_atomic_check_mode(head, asyh);
382
383		if (check_lut)
384			asyh->olut.visible = asyh->olut.handle != 0;
385
386		if (asyc) {
387			if (asyc->set.scaler)
388				nv50_head_atomic_check_view(armh, asyh, asyc);
389			if (asyc->set.dither)
390				nv50_head_atomic_check_dither(armh, asyh, asyc);
391			if (asyc->set.procamp)
392				nv50_head_atomic_check_procamp(armh, asyh, asyc);
393		}
394
395		if (head->func->core_calc) {
396			head->func->core_calc(head, asyh);
397			if (!asyh->core.visible)
398				asyh->olut.visible = false;
399		}
400
401		asyh->set.base = armh->base.cpp != asyh->base.cpp;
402		asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
403	} else {
404		asyh->olut.visible = false;
405		asyh->core.visible = false;
406		asyh->curs.visible = false;
407		asyh->base.cpp = 0;
408		asyh->ovly.cpp = 0;
409	}
410
411	if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
412		if (asyh->core.visible) {
413			if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
414				asyh->set.core = true;
415		} else
416		if (armh->core.visible) {
417			asyh->clr.core = true;
418		}
419
420		if (asyh->curs.visible) {
421			if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
422				asyh->set.curs = true;
423		} else
424		if (armh->curs.visible) {
425			asyh->clr.curs = true;
426		}
427
428		if (asyh->olut.visible) {
429			if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
430				asyh->set.olut = true;
431		} else
432		if (armh->olut.visible) {
433			asyh->clr.olut = true;
434		}
435	} else {
436		asyh->clr.olut = armh->olut.visible;
437		asyh->clr.core = armh->core.visible;
438		asyh->clr.curs = armh->curs.visible;
439		asyh->set.olut = asyh->olut.visible;
440		asyh->set.core = asyh->core.visible;
441		asyh->set.curs = asyh->curs.visible;
442	}
443
444	ret = nv50_crc_atomic_check_head(head, asyh, armh);
445	if (ret)
446		return ret;
447
448	if (asyh->clr.mask || asyh->set.mask)
449		nv50_atom(asyh->state.state)->lock_core = true;
450	return 0;
451}
452
453static const struct drm_crtc_helper_funcs
454nv50_head_help = {
455	.atomic_check = nv50_head_atomic_check,
456	.get_scanout_position = nouveau_display_scanoutpos,
457};
458
459static void
460nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
461			       struct drm_crtc_state *state)
462{
463	struct nv50_head_atom *asyh = nv50_head_atom(state);
464	__drm_atomic_helper_crtc_destroy_state(&asyh->state);
465	kfree(asyh);
466}
467
468static struct drm_crtc_state *
469nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
470{
471	struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
472	struct nv50_head_atom *asyh;
473	if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
474		return NULL;
475	__drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
476	asyh->wndw = armh->wndw;
477	asyh->view = armh->view;
478	asyh->mode = armh->mode;
479	asyh->olut = armh->olut;
480	asyh->core = armh->core;
481	asyh->curs = armh->curs;
482	asyh->base = armh->base;
483	asyh->ovly = armh->ovly;
484	asyh->dither = armh->dither;
485	asyh->procamp = armh->procamp;
486	asyh->crc = armh->crc;
487	asyh->or = armh->or;
488	asyh->dp = armh->dp;
489	asyh->clr.mask = 0;
490	asyh->set.mask = 0;
491	return &asyh->state;
492}
493
494static void
495nv50_head_reset(struct drm_crtc *crtc)
496{
497	struct nv50_head_atom *asyh;
498
499	if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
500		return;
501
502	if (crtc->state)
503		nv50_head_atomic_destroy_state(crtc, crtc->state);
504
505	__drm_atomic_helper_crtc_reset(crtc, &asyh->state);
506}
507
508static int
509nv50_head_late_register(struct drm_crtc *crtc)
510{
511	return nv50_head_crc_late_register(nv50_head(crtc));
512}
513
514static void
515nv50_head_destroy(struct drm_crtc *crtc)
516{
517	struct nv50_head *head = nv50_head(crtc);
518
519	nvif_event_dtor(&head->base.vblank);
520	nvif_head_dtor(&head->base.head);
521	nv50_lut_fini(&head->olut);
522	drm_crtc_cleanup(crtc);
523	kfree(head);
524}
525
526static const struct drm_crtc_funcs
527nv50_head_func = {
528	.reset = nv50_head_reset,
529	.destroy = nv50_head_destroy,
530	.set_config = drm_atomic_helper_set_config,
531	.page_flip = drm_atomic_helper_page_flip,
532	.atomic_duplicate_state = nv50_head_atomic_duplicate_state,
533	.atomic_destroy_state = nv50_head_atomic_destroy_state,
534	.enable_vblank = nouveau_display_vblank_enable,
535	.disable_vblank = nouveau_display_vblank_disable,
536	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
537	.late_register = nv50_head_late_register,
538};
539
540static const struct drm_crtc_funcs
541nvd9_head_func = {
542	.reset = nv50_head_reset,
543	.destroy = nv50_head_destroy,
544	.set_config = drm_atomic_helper_set_config,
545	.page_flip = drm_atomic_helper_page_flip,
546	.atomic_duplicate_state = nv50_head_atomic_duplicate_state,
547	.atomic_destroy_state = nv50_head_atomic_destroy_state,
548	.enable_vblank = nouveau_display_vblank_enable,
549	.disable_vblank = nouveau_display_vblank_disable,
550	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
551	.verify_crc_source = nv50_crc_verify_source,
552	.get_crc_sources = nv50_crc_get_sources,
553	.set_crc_source = nv50_crc_set_source,
554	.late_register = nv50_head_late_register,
555};
556
557static int
558nv50_head_vblank_handler(struct nvif_event *event, void *repv, u32 repc)
559{
560	struct nouveau_crtc *nv_crtc = container_of(event, struct nouveau_crtc, vblank);
561
562	if (drm_crtc_handle_vblank(&nv_crtc->base))
563		nv50_crc_handle_vblank(nv50_head(&nv_crtc->base));
564
565	return NVIF_EVENT_KEEP;
566}
567
568struct nv50_head *
569nv50_head_create(struct drm_device *dev, int index)
570{
571	struct nouveau_drm *drm = nouveau_drm(dev);
572	struct nv50_disp *disp = nv50_disp(dev);
573	struct nv50_head *head;
574	struct nv50_wndw *base, *ovly, *curs;
575	struct nouveau_crtc *nv_crtc;
576	struct drm_crtc *crtc;
577	const struct drm_crtc_funcs *funcs;
578	int ret;
579
580	head = kzalloc(sizeof(*head), GFP_KERNEL);
581	if (!head)
582		return ERR_PTR(-ENOMEM);
583
584	head->func = disp->core->func->head;
585	head->disp = disp;
586	head->base.index = index;
587
588	if (disp->disp->object.oclass < GF110_DISP)
589		funcs = &nv50_head_func;
590	else
591		funcs = &nvd9_head_func;
592
593	if (disp->disp->object.oclass < GV100_DISP) {
594		ret = nv50_base_new(drm, head->base.index, &base);
595		ret = nv50_ovly_new(drm, head->base.index, &ovly);
596	} else {
597		ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,
598				    head->base.index * 2 + 0, &base);
599		ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,
600				    head->base.index * 2 + 1, &ovly);
601	}
602	if (ret == 0)
603		ret = nv50_curs_new(drm, head->base.index, &curs);
604	if (ret) {
605		kfree(head);
606		return ERR_PTR(ret);
607	}
608
609	nv_crtc = &head->base;
610	crtc = &nv_crtc->base;
611	drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
612				  funcs, "head-%d", head->base.index);
613	drm_crtc_helper_add(crtc, &nv50_head_help);
614	/* Keep the legacy gamma size at 256 to avoid compatibility issues */
615	drm_mode_crtc_set_gamma_size(crtc, 256);
616	drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,
617				   disp->disp->object.oclass >= GF110_DISP,
618				   head->func->olut_size);
619
620	if (head->func->olut_set) {
621		ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
622		if (ret) {
623			nv50_head_destroy(crtc);
624			return ERR_PTR(ret);
625		}
626	}
627
628	ret = nvif_head_ctor(disp->disp, head->base.base.name, head->base.index, &head->base.head);
629	if (ret)
630		return ERR_PTR(ret);
631
632	ret = nvif_head_vblank_event_ctor(&head->base.head, "kmsVbl", nv50_head_vblank_handler,
633					  false, &nv_crtc->vblank);
634	if (ret)
635		return ERR_PTR(ret);
636
637	return head;
638}