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disp.h

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linux-6.19.14/drivers/gpu/drm/nouveau/dispnv50/disp.h C
  1#ifndef __NV50_KMS_H__
  2#define __NV50_KMS_H__
  3#include <linux/workqueue.h>
  4#include <nvif/mem.h>
  5#include <nvif/push.h>
  6
  7#include "nouveau_display.h"
  8
  9struct nv50_msto;
 10struct nouveau_encoder;
 11
 12struct nv50_disp {
 13	struct nvif_disp *disp;
 14	struct nv50_core *core;
 15	struct nvif_object caps;
 16
 17#define NV50_DISP_SYNC(c, o)                                ((c) * 0x040 + (o))
 18#define NV50_DISP_CORE_NTFY                       NV50_DISP_SYNC(0      , 0x00)
 19#define NV50_DISP_WNDW_SEM0(c)                    NV50_DISP_SYNC(1 + (c), 0x00)
 20#define NV50_DISP_WNDW_SEM1(c)                    NV50_DISP_SYNC(1 + (c), 0x10)
 21#define NV50_DISP_WNDW_NTFY(c)                    NV50_DISP_SYNC(1 + (c), 0x20)
 22#define NV50_DISP_BASE_SEM0(c)                    NV50_DISP_WNDW_SEM0(0 + (c))
 23#define NV50_DISP_BASE_SEM1(c)                    NV50_DISP_WNDW_SEM1(0 + (c))
 24#define NV50_DISP_BASE_NTFY(c)                    NV50_DISP_WNDW_NTFY(0 + (c))
 25#define NV50_DISP_OVLY_SEM0(c)                    NV50_DISP_WNDW_SEM0(4 + (c))
 26#define NV50_DISP_OVLY_SEM1(c)                    NV50_DISP_WNDW_SEM1(4 + (c))
 27#define NV50_DISP_OVLY_NTFY(c)                    NV50_DISP_WNDW_NTFY(4 + (c))
 28	struct nouveau_bo *sync;
 29
 30	struct mutex mutex;
 31};
 32
 33static inline struct nv50_disp *
 34nv50_disp(struct drm_device *dev)
 35{
 36	return nouveau_display(dev)->priv;
 37}
 38
 39struct nv50_disp_interlock {
 40	enum nv50_disp_interlock_type {
 41		NV50_DISP_INTERLOCK_CORE = 0,
 42		NV50_DISP_INTERLOCK_CURS,
 43		NV50_DISP_INTERLOCK_BASE,
 44		NV50_DISP_INTERLOCK_OVLY,
 45		NV50_DISP_INTERLOCK_WNDW,
 46		NV50_DISP_INTERLOCK_WIMM,
 47		NV50_DISP_INTERLOCK__SIZE
 48	} type;
 49	u32 data;
 50	u32 wimm;
 51};
 52
 53void corec37d_ntfy_init(struct nouveau_bo *, u32);
 54
 55void head907d_olut_load(struct drm_color_lut *, int size, void __iomem *);
 56
 57struct nv50_chan {
 58	struct nvif_object user;
 59	struct nvif_device *device;
 60};
 61
 62struct nv50_dmac {
 63	struct nv50_chan base;
 64
 65	struct nvif_push push;
 66
 67	struct nvif_object sync;
 68	struct nvif_object vram;
 69
 70	u32 cur;
 71	u32 put;
 72	u32 max;
 73};
 74
 75struct nv50_outp_atom {
 76	struct list_head head;
 77
 78	struct drm_encoder *encoder;
 79
 80	bool disabled;
 81	bool enabled;
 82
 83	union nv50_outp_atom_mask {
 84		struct {
 85			bool ctrl:1;
 86		};
 87		u8 mask;
 88	} set, clr;
 89};
 90
 91int nv50_dmac_create(struct nouveau_drm *,
 92		     const s32 *oclass, u8 head, void *data, u32 size,
 93		     s64 syncbuf, struct nv50_dmac *dmac);
 94void nv50_dmac_destroy(struct nv50_dmac *);
 95
 96/*
 97 * For normal encoders this just returns the encoder. For active MST encoders,
 98 * this returns the real outp that's driving displays on the topology.
 99 * Inactive MST encoders return NULL, since they would have no real outp to
100 * return anyway.
101 */
102struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder);
103
104extern const u64 disp50xx_modifiers[];
105extern const u64 disp90xx_modifiers[];
106extern const u64 wndwc57e_modifiers[];
107extern const u64 wndwca7e_modifiers[];
108#endif
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