crcca7d.c

 1/* SPDX-License-Identifier: MIT
 2 *
 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
 4 */
 5#include "crcc37d.h"
 6#include "core.h"
 7#include "head.h"
 8
 9#include <nvif/pushc97b.h>
10
11#include <nvhw/class/clca7d.h>
12
13static int
14crcca7d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx)
15{
16	struct nvif_push *push = &head->disp->core->chan.push;
17	const int i = head->base.index;
18	int ret;
19
20	ret = PUSH_WAIT(push, ctx ? 3 : 2);
21	if (ret)
22		return ret;
23
24	if (ctx) {
25		const u32 crc_hi = upper_32_bits(ctx->mem.addr);
26		const u32 crc_lo = lower_32_bits(ctx->mem.addr);
27
28		PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CRC(i), crc_hi,
29
30					HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
31			  NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ADDRESS_LO, crc_lo >> 4) |
32			  NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, TARGET, PHYSICAL_NVM) |
33			  NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, ENABLE));
34	} else {
35		PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
36			  NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, DISABLE));
37	}
38
39	return 0;
40}
41
42static int
43crcca7d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source,
44		struct nv50_crc_notifier_ctx *ctx)
45{
46	struct nvif_push *push = &head->disp->core->chan.push;
47	const int i = head->base.index;
48	int primary_crc, ret;
49
50	if (!source) {
51		ret = PUSH_WAIT(push, 1);
52		if (ret)
53			return ret;
54
55		PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i), 0);
56
57		return crcca7d_set_ctx(head, NULL);
58	}
59
60	switch (source) {
61	case NV50_CRC_SOURCE_TYPE_SOR:
62		primary_crc = NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(or);
63		break;
64	case NV50_CRC_SOURCE_TYPE_SF:
65		primary_crc = NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF;
66		break;
67	default:
68		break;
69	}
70
71	ret = crcca7d_set_ctx(head, ctx);
72	if (ret)
73		return ret;
74
75	ret = PUSH_WAIT(push, 2);
76	if (ret)
77		return ret;
78
79	PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i),
80		  NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
81		  NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
82		  NVVAL(NVCA7D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, primary_crc) |
83		  NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |
84		  NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE));
85
86	return 0;
87}
88
89const struct nv50_crc_func
90crcca7d = {
91	.set_src = crcca7d_set_src,
92	.set_ctx = crcca7d_set_ctx,
93	.get_entry = crcc37d_get_entry,
94	.ctx_finished = crcc37d_ctx_finished,
95	.flip_threshold = CRCC37D_FLIP_THRESHOLD,
96	.num_entries = CRCC37D_MAX_ENTRIES,
97	.notifier_len = sizeof(struct crcc37d_notifier),
98};