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hw.c
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linux-6.19.14/drivers/gpu/drm/nouveau/dispnv04/hw.c
1/* 2 * Copyright 2006 Dave Airlie 3 * Copyright 2007 Maarten Maathuis 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "nouveau_drv.h" 26#include "hw.h" 27 28#include <subdev/bios/pll.h> 29#include <nvif/timer.h> 30 31#define CHIPSET_NFORCE 0x01a0 32#define CHIPSET_NFORCE2 0x01f0 33 34/* 35 * misc hw access wrappers/control functions 36 */ 37 38void 39NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) 40{ 41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); 43} 44 45uint8_t 46NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) 47{ 48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); 50} 51 52void 53NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) 54{ 55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); 57} 58 59uint8_t 60NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) 61{ 62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); 64} 65 66/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) 67 * it affects only the 8 bit vga io regs, which we access using mmio at 68 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* 69 * in general, the set value of cr44 does not matter: reg access works as 70 * expected and values can be set for the appropriate head by using a 0x2000 71 * offset as required 72 * however: 73 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and 74 * cr44 must be set to 0 or 3 for accessing values on the correct head 75 * through the common 0xc03c* addresses 76 * b) in tied mode (4) head B is programmed to the values set on head A, and 77 * access using the head B addresses can have strange results, ergo we leave 78 * tied mode in init once we know to what cr44 should be restored on exit 79 * 80 * the owner parameter is slightly abused: 81 * 0 and 1 are treated as head values and so the set value is (owner * 3) 82 * other values are treated as literal values to set 83 */ 84void 85NVSetOwner(struct drm_device *dev, int owner) 86{ 87 struct nouveau_drm *drm = nouveau_drm(dev); 88 89 if (owner == 1) 90 owner *= 3; 91 92 if (drm->client.device.info.chipset == 0x11) { 93 /* This might seem stupid, but the blob does it and 94 * omitting it often locks the system up. 95 */ 96 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); 97 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); 98 } 99 100 /* CR44 is always changed on CRTC0 */ 101 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); 102 103 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ 104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 106 } 107} 108 109void 110NVBlankScreen(struct drm_device *dev, int head, bool blank) 111{ 112 unsigned char seq1; 113 114 if (nv_two_heads(dev)) 115 NVSetOwner(dev, head); 116 117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 118 119 NVVgaSeqReset(dev, head, true); 120 if (blank) 121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 122 else 123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); 124 NVVgaSeqReset(dev, head, false); 125} 126 127/* 128 * PLL getting 129 */ 130 131static void 132nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, 133 uint32_t pll2, struct nvkm_pll_vals *pllvals) 134{ 135 struct nouveau_drm *drm = nouveau_drm(dev); 136 137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ 138 139 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ 140 pllvals->log2P = (pll1 >> 16) & 0x7; 141 pllvals->N2 = pllvals->M2 = 1; 142 143 if (reg1 <= 0x405c) { 144 pllvals->NM1 = pll2 & 0xffff; 145 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ 146 if (!(pll1 & 0x1100)) 147 pllvals->NM2 = pll2 >> 16; 148 } else { 149 pllvals->NM1 = pll1 & 0xffff; 150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) 151 pllvals->NM2 = pll2 & 0xffff; 152 else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { 153 pllvals->M1 &= 0xf; /* only 4 bits */ 154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 155 pllvals->M2 = (pll1 >> 4) & 0x7; 156 pllvals->N2 = ((pll1 >> 21) & 0x18) | 157 ((pll1 >> 19) & 0x7); 158 } 159 } 160 } 161} 162 163int 164nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 165 struct nvkm_pll_vals *pllvals) 166{ 167 struct nouveau_drm *drm = nouveau_drm(dev); 168 struct nvif_object *device = &drm->client.device.object; 169 struct nvkm_bios *bios = nvxx_bios(drm); 170 uint32_t reg1, pll1, pll2 = 0; 171 struct nvbios_pll pll_lim; 172 int ret; 173 174 ret = nvbios_pll_parse(bios, plltype, &pll_lim); 175 if (ret || !(reg1 = pll_lim.reg)) 176 return -ENOENT; 177 178 pll1 = nvif_rd32(device, reg1); 179 if (reg1 <= 0x405c) 180 pll2 = nvif_rd32(device, reg1 + 4); 181 else if (nv_two_reg_pll(dev)) { 182 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); 183 184 pll2 = nvif_rd32(device, reg2); 185 } 186 187 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { 188 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); 189 190 /* check whether vpll has been forced into single stage mode */ 191 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { 192 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) 193 pll2 = 0; 194 } else 195 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) 196 pll2 = 0; 197 } 198 199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); 200 pllvals->refclk = pll_lim.refclk; 201 return 0; 202} 203 204int 205nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) 206{ 207 /* Avoid divide by zero if called at an inappropriate time */ 208 if (!pv->M1 || !pv->M2) 209 return 0; 210 211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; 212} 213 214int 215nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) 216{ 217 struct pci_dev *pdev = to_pci_dev(dev->dev); 218 struct nvkm_pll_vals pllvals; 219 int ret; 220 int domain; 221 222 domain = pci_domain_nr(pdev->bus); 223 224 if (plltype == PLL_MEMORY && 225 (pdev->device & 0x0ff0) == CHIPSET_NFORCE) { 226 uint32_t mpllP; 227 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3), 228 0x6c, &mpllP); 229 mpllP = (mpllP >> 8) & 0xf; 230 if (!mpllP) 231 mpllP = 4; 232 233 return 400000 / mpllP; 234 } else 235 if (plltype == PLL_MEMORY && 236 (pdev->device & 0xff0) == CHIPSET_NFORCE2) { 237 uint32_t clock; 238 239 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5), 240 0x4c, &clock); 241 return clock / 1000; 242 } 243 244 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); 245 if (ret) 246 return ret; 247 248 return nouveau_hw_pllvals_to_clk(&pllvals); 249} 250 251static void 252nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) 253{ 254 /* the vpll on an unused head can come up with a random value, way 255 * beyond the pll limits. for some reason this causes the chip to 256 * lock up when reading the dac palette regs, so set a valid pll here 257 * when such a condition detected. only seen on nv11 to date 258 */ 259 260 struct nouveau_drm *drm = nouveau_drm(dev); 261 struct nvkm_clk *clk = nvxx_clk(drm); 262 struct nvkm_bios *bios = nvxx_bios(drm); 263 struct nvbios_pll pll_lim; 264 struct nvkm_pll_vals pv; 265 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; 266 267 if (nvbios_pll_parse(bios, pll, &pll_lim)) 268 return; 269 nouveau_hw_get_pllvals(dev, pll, &pv); 270 271 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && 272 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && 273 pv.log2P <= pll_lim.max_p) 274 return; 275 276 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); 277 278 /* set lowest clock within static limits */ 279 pv.M1 = pll_lim.vco1.max_m; 280 pv.N1 = pll_lim.vco1.min_n; 281 pv.log2P = pll_lim.max_p_usable; 282 clk->pll_prog(clk, pll_lim.reg, &pv); 283} 284 285/* 286 * vga font save/restore 287 */ 288 289static void nouveau_vga_font_io(struct drm_device *dev, 290 void __iomem *iovram, 291 bool save, unsigned plane) 292{ 293 unsigned i; 294 295 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); 296 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); 297 for (i = 0; i < 16384; i++) { 298 if (save) { 299 nv04_display(dev)->saved_vga_font[plane][i] = 300 ioread32_native(iovram + i * 4); 301 } else { 302 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], 303 iovram + i * 4); 304 } 305 } 306} 307 308void 309nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) 310{ 311 struct nouveau_drm *drm = nouveau_drm(dev); 312 struct pci_dev *pdev = to_pci_dev(dev->dev); 313 uint8_t misc, gr4, gr5, gr6, seq2, seq4; 314 bool graphicsmode; 315 unsigned plane; 316 void __iomem *iovram; 317 318 if (nv_two_heads(dev)) 319 NVSetOwner(dev, 0); 320 321 NVSetEnablePalette(dev, 0, true); 322 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; 323 NVSetEnablePalette(dev, 0, false); 324 325 if (graphicsmode) /* graphics mode => framebuffer => no need to save */ 326 return; 327 328 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); 329 330 /* map first 64KiB of VRAM, holds VGA fonts etc */ 331 iovram = ioremap(pci_resource_start(pdev, 1), 65536); 332 if (!iovram) { 333 NV_ERROR(drm, "Failed to map VRAM, " 334 "cannot save/restore VGA fonts.\n"); 335 return; 336 } 337 338 if (nv_two_heads(dev)) 339 NVBlankScreen(dev, 1, true); 340 NVBlankScreen(dev, 0, true); 341 342 /* save control regs */ 343 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); 344 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); 345 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); 346 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); 347 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); 348 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); 349 350 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); 351 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); 352 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); 353 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); 354 355 /* store font in planes 0..3 */ 356 for (plane = 0; plane < 4; plane++) 357 nouveau_vga_font_io(dev, iovram, save, plane); 358 359 /* restore control regs */ 360 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); 361 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); 362 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); 363 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); 364 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); 365 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); 366 367 if (nv_two_heads(dev)) 368 NVBlankScreen(dev, 1, false); 369 NVBlankScreen(dev, 0, false); 370 371 iounmap(iovram); 372} 373 374/* 375 * mode state save/load 376 */ 377 378static void 379rd_cio_state(struct drm_device *dev, int head, 380 struct nv04_crtc_reg *crtcstate, int index) 381{ 382 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); 383} 384 385static void 386wr_cio_state(struct drm_device *dev, int head, 387 struct nv04_crtc_reg *crtcstate, int index) 388{ 389 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); 390} 391 392static void 393nv_save_state_ramdac(struct drm_device *dev, int head, 394 struct nv04_mode_state *state) 395{ 396 struct nouveau_drm *drm = nouveau_drm(dev); 397 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 398 int i; 399 400 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 401 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); 402 403 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); 404 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); 405 if (nv_two_heads(dev)) 406 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); 407 if (drm->client.device.info.chipset == 0x11) 408 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); 409 410 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); 411 412 if (nv_gf4_disp_arch(dev)) 413 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); 414 if (drm->client.device.info.chipset >= 0x30) 415 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); 416 417 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); 418 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); 419 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); 420 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); 421 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); 422 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); 423 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); 424 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); 425 426 for (i = 0; i < 7; i++) { 427 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 428 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); 429 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); 430 } 431 432 if (nv_gf4_disp_arch(dev)) { 433 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); 434 for (i = 0; i < 3; i++) { 435 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); 436 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); 437 } 438 } 439 440 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 441 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); 442 if (!nv_gf4_disp_arch(dev) && head == 0) { 443 /* early chips don't allow access to PRAMDAC_TMDS_* without 444 * the head A FPCLK on (nv11 even locks up) */ 445 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & 446 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); 447 } 448 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); 449 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); 450 451 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); 452 453 if (nv_gf4_disp_arch(dev)) 454 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); 455 456 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 457 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); 458 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); 459 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); 460 461 for (i = 0; i < 38; i++) 462 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, 463 NV_PRAMDAC_CTV + 4*i); 464 } 465} 466 467static void 468nv_load_state_ramdac(struct drm_device *dev, int head, 469 struct nv04_mode_state *state) 470{ 471 struct nouveau_drm *drm = nouveau_drm(dev); 472 struct nvkm_clk *clk = nvxx_clk(drm); 473 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 474 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 475 int i; 476 477 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 478 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); 479 480 clk->pll_prog(clk, pllreg, ®p->pllvals); 481 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 482 if (nv_two_heads(dev)) 483 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); 484 if (drm->client.device.info.chipset == 0x11) 485 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); 486 487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); 488 489 if (nv_gf4_disp_arch(dev)) 490 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); 491 if (drm->client.device.info.chipset >= 0x30) 492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); 493 494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); 495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); 496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); 497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); 498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); 499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); 500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); 501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); 502 503 for (i = 0; i < 7; i++) { 504 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 505 506 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); 507 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); 508 } 509 510 if (nv_gf4_disp_arch(dev)) { 511 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); 512 for (i = 0; i < 3; i++) { 513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); 514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); 515 } 516 } 517 518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); 519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); 520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); 521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); 522 523 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); 524 525 if (nv_gf4_disp_arch(dev)) 526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); 527 528 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 529 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); 530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); 531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); 532 533 for (i = 0; i < 38; i++) 534 NVWriteRAMDAC(dev, head, 535 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); 536 } 537} 538 539static void 540nv_save_state_vga(struct drm_device *dev, int head, 541 struct nv04_mode_state *state) 542{ 543 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 544 int i; 545 546 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); 547 548 for (i = 0; i < 25; i++) 549 rd_cio_state(dev, head, regp, i); 550 551 NVSetEnablePalette(dev, head, true); 552 for (i = 0; i < 21; i++) 553 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); 554 NVSetEnablePalette(dev, head, false); 555 556 for (i = 0; i < 9; i++) 557 regp->Graphics[i] = NVReadVgaGr(dev, head, i); 558 559 for (i = 0; i < 5; i++) 560 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); 561} 562 563static void 564nv_load_state_vga(struct drm_device *dev, int head, 565 struct nv04_mode_state *state) 566{ 567 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 568 int i; 569 570 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); 571 572 for (i = 0; i < 5; i++) 573 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); 574 575 nv_lock_vga_crtc_base(dev, head, false); 576 for (i = 0; i < 25; i++) 577 wr_cio_state(dev, head, regp, i); 578 nv_lock_vga_crtc_base(dev, head, true); 579 580 for (i = 0; i < 9; i++) 581 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); 582 583 NVSetEnablePalette(dev, head, true); 584 for (i = 0; i < 21; i++) 585 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); 586 NVSetEnablePalette(dev, head, false); 587} 588 589static void 590nv_save_state_ext(struct drm_device *dev, int head, 591 struct nv04_mode_state *state) 592{ 593 struct nouveau_drm *drm = nouveau_drm(dev); 594 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 595 int i; 596 597 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 598 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 600 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 601 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 602 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 603 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 604 605 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 607 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 608 609 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 610 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 611 612 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 613 rd_cio_state(dev, head, regp, 0x9f); 614 615 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 616 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 619 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 620 621 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 622 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); 623 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); 624 625 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 626 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); 627 628 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 629 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); 630 631 if (nv_two_heads(dev)) 632 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); 633 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); 634 } 635 636 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); 637 638 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 640 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 641 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 642 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 643 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); 644 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 645 } 646 /* NV11 and NV20 don't have this, they stop at 0x52. */ 647 if (nv_gf4_disp_arch(dev)) { 648 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); 649 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); 650 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); 651 652 for (i = 0; i < 0x10; i++) 653 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); 654 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); 655 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); 656 657 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); 658 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); 659 } 660 661 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); 662} 663 664static void 665nv_load_state_ext(struct drm_device *dev, int head, 666 struct nv04_mode_state *state) 667{ 668 struct nouveau_drm *drm = nouveau_drm(dev); 669 struct nvif_object *device = &drm->client.device.object; 670 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 671 uint32_t reg900; 672 int i; 673 674 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 675 if (nv_two_heads(dev)) 676 /* setting ENGINE_CTRL (EC) *must* come before 677 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in 678 * EC that should not be overwritten by writing stale EC 679 */ 680 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); 681 682 nvif_wr32(device, NV_PVIDEO_STOP, 1); 683 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); 684 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); 685 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); 686 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); 687 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); 688 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); 689 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); 690 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); 691 692 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); 693 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); 694 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); 695 696 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 697 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); 698 699 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 700 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); 701 702 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); 703 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) 704 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); 705 else 706 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); 707 } 708 } 709 710 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); 711 712 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 714 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 715 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 716 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 717 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 718 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 721 722 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 723 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 724 725 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 726 wr_cio_state(dev, head, regp, 0x9f); 727 728 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 732 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 733 nv_fix_nv40_hw_cursor(dev, head); 734 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 735 736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 738 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 739 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 740 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 741 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 742 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 743 } 744 /* NV11 and NV20 stop at 0x52. */ 745 if (nv_gf4_disp_arch(dev)) { 746 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { 747 /* Not waiting for vertical retrace before modifying 748 CRE_53/CRE_54 causes lockups. */ 749 nvif_msec(&drm->client.device, 650, 750 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 751 break; 752 ); 753 nvif_msec(&drm->client.device, 650, 754 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 755 break; 756 ); 757 } 758 759 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 760 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 761 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 762 763 for (i = 0; i < 0x10; i++) 764 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); 765 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); 766 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); 767 768 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); 769 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); 770 } 771 772 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); 773} 774 775static void 776nv_save_state_palette(struct drm_device *dev, int head, 777 struct nv04_mode_state *state) 778{ 779 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 780 int head_offset = head * NV_PRMDIO_SIZE, i; 781 782 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 783 NV_PRMDIO_PIXEL_MASK_MASK); 784 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); 785 786 for (i = 0; i < 768; i++) { 787 state->crtc_reg[head].DAC[i] = nvif_rd08(device, 788 NV_PRMDIO_PALETTE_DATA + head_offset); 789 } 790 791 NVSetEnablePalette(dev, head, false); 792} 793 794void 795nouveau_hw_load_state_palette(struct drm_device *dev, int head, 796 struct nv04_mode_state *state) 797{ 798 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 799 int head_offset = head * NV_PRMDIO_SIZE, i; 800 801 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 802 NV_PRMDIO_PIXEL_MASK_MASK); 803 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); 804 805 for (i = 0; i < 768; i++) { 806 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, 807 state->crtc_reg[head].DAC[i]); 808 } 809 810 NVSetEnablePalette(dev, head, false); 811} 812 813void nouveau_hw_save_state(struct drm_device *dev, int head, 814 struct nv04_mode_state *state) 815{ 816 struct nouveau_drm *drm = nouveau_drm(dev); 817 818 if (drm->client.device.info.chipset == 0x11) 819 /* NB: no attempt is made to restore the bad pll later on */ 820 nouveau_hw_fix_bad_vpll(dev, head); 821 nv_save_state_ramdac(dev, head, state); 822 nv_save_state_vga(dev, head, state); 823 nv_save_state_palette(dev, head, state); 824 nv_save_state_ext(dev, head, state); 825} 826 827void nouveau_hw_load_state(struct drm_device *dev, int head, 828 struct nv04_mode_state *state) 829{ 830 NVVgaProtect(dev, head, true); 831 nv_load_state_ramdac(dev, head, state); 832 nv_load_state_ext(dev, head, state); 833 nouveau_hw_load_state_palette(dev, head, state); 834 nv_load_state_vga(dev, head, state); 835 NVVgaProtect(dev, head, false); 836}
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